/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_gpc_no_tpc_h__ #define __ga102_dev_gpc_no_tpc_h__ /* This file is autogenerated. Do not edit */ #define NV_PGPC 0x00007fff:0x00000000 /* RW--D */ #define NV_PGPC_PRI /* ----L */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK 0x00002280 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK 0x00002284 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x00002288 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK 0x0000228c /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x00002290 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x00002294 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK 0x000020e8 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK 0x00002298 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0000229c /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x000023d0 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x000023f0 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x000023f4 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x000023f8 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x000023fc /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0000218c+(i)*16) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x000022b0+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK 0x00002190 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x00002194 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK 0x00002198 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0000219c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK 0x000021a0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x000021a4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x000021a8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x000021b0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK 0x000021bc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x000021e0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x000021e4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK 0x000021e8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK 0x000021ec /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x000021f0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK 0x000021f4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x000021f8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK 0x000021fc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK 0x00002220 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x00002224 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0000222c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET 0x00002000 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_HALT 4:4 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT 15:8 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1 8:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ1_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2 9:9 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ2_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3 10:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ3_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4 11:11 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ4_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5 12:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ5_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6 13:13 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ6_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7 14:14 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ7_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8 15:15 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_EXT_EXTIRQ8_SET 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_DMA 16:16 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR 0x00002004 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT 0x00002008 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ1_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ2_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ3_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ4_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ5_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ6_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ7_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_EXT_EXTIRQ8_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE 0x0000200c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x00002290 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1 8:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ1_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2 9:9 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ2_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3 10:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ3_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4 11:11 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ4_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5 12:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ5_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6 13:13 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ6_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7 14:14 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ7_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8 15:15 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_EXT_EXTIRQ8_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK 0x000020e0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x000021a4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1 8:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ1_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2 9:9 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ2_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3 10:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ3_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4 11:11 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ4_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5 12:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ5_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6 13:13 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ6_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7 14:14 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ7_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8 15:15 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_ENABLE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_EXT_EXTIRQ8_DISABLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET 0x00002010 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x00002290 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_HALT 4:4 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_DMA 16:16 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR 0x00002014 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x00002290 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1 8:8 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2 9:9 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ2_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3 10:10 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ3_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4 11:11 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ4_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5 12:12 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ5_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6 13:13 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ6_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7 14:14 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ7_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8 15:15 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_EXT_EXTIRQ8_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK 0x00002018 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_HALT 4:4 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1 8:8 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ1_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2 9:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ2_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3 10:10 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ3_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4 11:11 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ4_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5 12:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ5_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6 13:13 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ6_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7 14:14 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ7_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8 15:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_EXT_EXTIRQ8_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_DMA 16:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST 0x0000201c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x00002290 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT 15:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ1_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ2_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ3_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ4_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5 12:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ5_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6 13:13 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ6_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7 14:14 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ7_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8 15:15 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_HOST_EXT_EXTIRQ8_FALCON 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT 31:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1 24:24 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ1_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2 25:25 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ2_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3 26:26 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ3_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4 27:27 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ4_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5 28:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ5_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ6_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ7_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST_TARGET_EXT_EXTIRQ8_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2 0x0000203c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x00002290 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRINT 0x00002020 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x000021a0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRVAL 0x00002024 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x000021a0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL 0x00002028 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x000021a0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER0 0x0000202c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x000021bc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER0_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER1 0x00002030 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x000021bc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PTIMER1_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRVAL 0x00002034 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0000229c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL 0x00002038 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0000229c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDDATA 0x00002064 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID 0x00002068 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_ID 11:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_PRIV 15:15 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_WPEND 16:16 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDWDAT 0x0000206c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCOUNT 0x00002070 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDPOP 0x00002074 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDPOP_POP 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDRAMSZ 0x00002078 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX 0x00002050 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX 0x00002054 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK 0x00002058 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX0 0x00002040 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX1 0x00002044 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN 0x00002048 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE 0x0000204c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x000021e0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE 0x0000205c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x000021e4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE 0x00002060 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x000023d0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SFTRESET 0x0000207c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SFTRESET_EXT 0:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL 0x000020a4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR 0x000020ac /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR_LSB 5:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR_LSB_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR_MSB 11:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ADDR_EXT 11:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL 0x0000210c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFBASE 0x00002110 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFMOFFS 0x00002114 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD 0x00002118 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFFBOFFS 0x0000211c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB 0x00002120 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP 0x00002124 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x000022c0 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x000022c4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x000022c8 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x000022cc /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x000022d0 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x000022d4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x000022d8 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x000022dc /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL 0x000022e0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH 0x000022e4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW 0x000022e8 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x00002190 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC(i) (0x00002180+(i)*16) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC__SIZE_1 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_OFFS 7:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_BLK 23:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SECURE 28:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMD(i) (0x00002184+(i)*16) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMD__SIZE_1 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMD_DATA 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT(i) (0x00002188+(i)*16) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT__SIZE_1 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT_TAG 15:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT_FAULT_CORRECTED 16:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT_FAULT_CORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED 17:17 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEMT_FAULT_UNCORRECTED_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC(i) (0x000021c0+(i)*8) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_OFFS 7:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_OFFS_INIT 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_BLK 23:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_BLK_INIT 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCW 24:24 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCR 25:25 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_VA 28:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MISS 29:29 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMD(i) (0x000021c4+(i)*8) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMD__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMD_DATA 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT(i) (0x00002210+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT_TAG 15:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT_FAULTED 16:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEMT_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEML(i) (0x000022a0+(i)*4) /* -W-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEML__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEML__PRIV_LEVEL_MASK NV_PGPC_PRI_GPCCS_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEML_LVL 2:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_DUMMY 0x00002258 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x00002284 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_DUMMY 0x000021b4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x00002280 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x00002300+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x000023f0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x00002310+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x000023f4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x00002320+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x000023f8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x00002330+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x000023fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER 0x000023d4 /* R-I4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG 0x00002108 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1 0x0000212c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000002 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2 0x000020f4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SHA 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BMEM 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_KMEM 4:4 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_VHR 7:7 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HS 8:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV 10:10 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG3 0x00002278 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_CGCTL 0x000020a0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2 0x00002134 /* RWI4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2__PRIV_LEVEL_MASK 0x000021e8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG 17:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_ENABLED 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG__PROD 0x000A0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL 0x00002240 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL__PRIV_LEVEL_MASK 0x00002298 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_LSMODE 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_HSMODE 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_UCODE_LEVEL 5:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1 0x00002250 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL 0x000020e4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL__PRIV_LEVEL_MASK 0x000020e8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERB 0x000022ec /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERB_DATA 31:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERB_DATA_CORRECTED_ERR 0xeafe0c00 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERB_DATA_UNCORRECTED_ERR 0xeafe1cff /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX 0x000022f0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_DATA 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRADDR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE 31:24 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PF 0x000000f0 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PF 0x000000f1 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_SCP 0x000000f2 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_SCP 0x000000f3 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_DMA 0x000000f4 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_DMA 0x000000f5 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IMEM_PMB 0x000000f6 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_PARITY_IMEM_PMB 0x000000f7 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_LDST 0x000000f8 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_PMB 0x000000f9 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_DMA 0x000000fa /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DMEM_SCP 0x000000fb /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_SHA 0x000000fc /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_SHA 0x000000fd /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_CORRECTED_RISCV 0x000000fe /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_UNCORRECTED_RISCV 0x000000ff /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_SBE_IROM 0x000000e0 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_MAILBOX_ERRCODE_DBE_IROM 0x000000e1 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL 0x000022f4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x000021b0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN 16:16 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_FUSE_OPT_ECC_EN_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_EXC_ON_DMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_HALT_ON_IMEM_ERR_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS 5:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_INIT 0x00000002 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_DMEM_PARITY_DIS_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS 1:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_INIT 0x00000002 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_CTRL_IMEM_ECC_DIS_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR 0x000022f8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR_HI 0x000022fc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SAFETY_ERR_ADDR_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_OS 0x00002080 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_OS_VERSION 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_RM 0x00002084 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_RM_CONFIG 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM 0x00002088 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x000021ec /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_MODE 0x0000208c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x000021ec /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM 0x000020a8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM__PRIV_LEVEL_MASK 0x000021ec /* */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1 0x00002090 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x00002294 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUGINFO 0x00002094 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN 0x00002270 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x000021f0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI 0x000020d0 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI__PRIV_LEVEL_MASK 0x000021f4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXPC 19:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXCAUSE_DMEM_FAULT_INS 0x00000014 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI2 0x000020bc /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI2__PRIV_LEVEL_MASK 0x000021f4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR 0x000020d4 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x000021f8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL 0x00002100 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x00002288 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS 0x00002130 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG 0x00002138 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC 0x00002104 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x00002194 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL 0x00002254 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x000021a8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_VAL 9:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_VAL_INIT 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_CYA 31:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1 0x00002098 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x000021fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_PC 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_EN 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2 0x0000209c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x000021fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_PC 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_EN 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3 0x000020b0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x000021fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_PC 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_EN 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4 0x000020b4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x000021fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_PC 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_EN 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5 0x000020b8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x000021fc /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_PC 23:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_EN 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD 0x00002200 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x00002220 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_FAULTED 13:13 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_FAULTED_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_FAULTED_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_FAULTED_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_PARM 31:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK 31:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_ADDR 0x00002204 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x00002220 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_WDATA 0x00002208 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x00002220 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA 0x0000220c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x00002220 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0 0x000020d8 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x00002224 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_VALID 28:28 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3 0x000020dc /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX 0x00002148 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0000219c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEPC 0x0000214c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0000219c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEPC_PC 23:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEINFO 0x0000217c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0000219c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL 0x00002140 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD 26:24 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG 0x0000215c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMSTAT 0x00002144 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0 0x00002150 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1 0x00002154 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLCTL 0x00002158 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL 0x00002260 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD 26:24 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_DMSTAT 0x00002264 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0000228c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMSTAT_VAL 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMVACTL 0x00002268 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x00002198 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_DMVACTL_BOUND_INIT 0x00000014 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT 0x00002244 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0000222c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_ADDR 0x0000224c /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0000222c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_INFO 0x00002248 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0000222c /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA 0x00002500 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA_V 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA_V_ELPG_LIST 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA_V_GPCRG_LIST 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA_A 0x0000250c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_METHOD_DATA_A_V 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH 0x00002504 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_PRIV 31:31 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR 11:0 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_NOP 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI_SAVE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI_RESTORE 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BIND_POINTER 0x00000003 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BIND_POINTER_ONLY 0x00000060 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE 0x00000004 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_HALT_PIPELINE_NEW 0x00000007 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_UNHALT_PIPELINE 0x00000005 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CONTEXT_RESET 0x00000006 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISCOVER_IMAGE_SIZE 0x00000010 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_PREPARE_FOR_INITIALIZATION 0x00000011 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_ONLY 0x00000008 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI_GOLDEN_SAVE 0x00000009 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI_SAVE_RESTORE 0x0000000a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_WFI 0x0000000b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_NOCHSW_MODE 0x0000000c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x0000000d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISABLE_RAMCHAIN_SCRUB 0x0000000e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x0000000f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_RESTORE_GOLDEN 0x00000015 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x00000016 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISCOVER_PM_IMAGE_SIZE 0x00000025 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x0000001a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_INIT_MME_SHADOW_RAM 0x0000002a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_INIT_BUNDLE_DECODERS 0x0000002b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x0000002c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x0000002d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_SMC_LTS_MASK_INDEX 0x0000002e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_ASSIGN_SMC_LTS_MASK 0x0000002f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x00000030 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_BIND_INSTANCE 0x00000031 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x00000032 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SAVE_REGLIST 0x00000033 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_RESTORE_REGLIST 0x00000034 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_UCODE_RECONFIG 0x00000035 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CHECK_GPCCS_INIT_COMPLETE 0x00000036 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_STOP_CTXSW 0x00000038 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_START_CTXSW 0x00000039 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x0000003a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_DISABLE_ACCESS_COUNTER 0x0000003c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_INSTANCE 0x0000003d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_LO 0x0000003e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_COMPRESSED_INIT_LIST_BIND_VIRTUAL_ADDRESS_HI 0x0000003f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_METHOD_INIT 0x00000040 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_COMPUTE 0x00000041 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_2D 0x00000042 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_3D 0x00000043 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_BUNDLE_INIT_MEM2MEM 0x00000044 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x00000054 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x00000055 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x00000056 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_CALCULATE 0x00000057 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x00000058 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x00000059 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_INJECT_STACK_CANARY_ERROR 0x00000070 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SHUTDOWN_UCODE 0x00000012 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS 0x00000013 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_CONTEXT_ADDRESS_HI 0x0000001e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_PRIV_OFFSET 0x00000014 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x0000001c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x0000001f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_GFXP_RC_OFFSET 0x0000001d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x00000017 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x00000022 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_PRIV_OFFSET 0x00000018 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_ZCULL_MODE 0x00000019 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CBC_CLEAR_ACTIVE 0x0000001b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_FMODEL_TESTS 0x00000020 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_WATCHDOG_TIMEOUT 0x00000021 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SET_GFID 0x00000024 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS 0x00000026 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x00000023 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_PM_PRIV_OFFSET 0x00000027 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SEND_PM_MODE 0x00000028 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_TEST_MODE 0x00000029 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_CONTROL_ZBC_TABLES_SAVE 0x00000061 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_START 0x00000062 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SAVE_SM_PERF_COUNTERS_END 0x00000063 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_RESTORE_SM_PERF_COUNTERS 0x00000064 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_START 0x00000069 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_SMPC_GLOBAL_MODE_STOP 0x0000006a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_RESTORE_HWPM_CONTROL_REGS 0x00000065 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_SAVE_TASKS 0x0000006b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_ADR_PERFORM_PRE_RESTORE_TASKS 0x0000006c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A 0x00002508 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_PRIV 31:31 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR 11:0 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_NOP 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI_RESTORE 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER 0x00000003 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_BIND_POINTER_ONLY 0x00000060 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE 0x00000004 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_HALT_PIPELINE_NEW 0x00000007 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_UNHALT_PIPELINE 0x00000005 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CONTEXT_RESET 0x00000006 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_IMAGE_SIZE 0x00000010 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_PREPARE_FOR_INITIALIZATION 0x00000011 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_ONLY 0x00000008 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI_GOLDEN_SAVE 0x00000009 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI_SAVE_RESTORE 0x0000000a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_WFI 0x0000000b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_NOCHSW_MODE 0x0000000c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_ALLOW_SWDX_DIRECT_CTXSW_SKIP 0x0000000d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISABLE_RAMCHAIN_SCRUB 0x0000000e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISABLE_SWDX_DIRECT_CTXSW_SCRUB 0x0000000f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_RESTORE_GOLDEN 0x00000015 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_ZCULL_IMAGE_SIZE 0x00000016 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PM_IMAGE_SIZE 0x00000025 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_PREEMPTION_IMAGE_SIZE 0x0000001a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_INIT_MME_SHADOW_RAM 0x0000002a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_INIT_BUNDLE_DECODERS 0x0000002b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_LO 0x0000002c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_GLOBAL_PRIV_ACCESS_MAP_ADDR_HI 0x0000002d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_SMC_LTS_MASK_INDEX 0x0000002e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_ASSIGN_SMC_LTS_MASK 0x0000002f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISCOVER_REGLIST_IMAGE_SIZE 0x00000030 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_BIND_INSTANCE 0x00000031 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_REGLIST_VIRTUAL_ADDRESS 0x00000032 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SAVE_REGLIST 0x00000033 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_RESTORE_REGLIST 0x00000034 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_UCODE_RECONFIG 0x00000035 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CHECK_GPCCS_INIT_COMPLETE 0x00000036 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_STOP_CTXSW 0x00000038 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_START_CTXSW 0x00000039 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CONFIGURE_INTERRUPT_COMPLETION_OPTION 0x0000003a /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_DISABLE_ACCESS_COUNTER 0x0000003c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_SIZE 0x00000054 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_LO 0x00000055 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_LO 0x00000056 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_CALCULATE 0x00000057 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_IN_SURF_OFFSET_HI 0x00000058 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CRC_CHECK_SET_OUT_SURF_OFFSET_HI 0x00000059 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_READ_PHYS_MEM 0x00000067 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_ENABLE_PHYS_MEM_READS 0x00000068 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SHUTDOWN_UCODE 0x00000012 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS 0x00000013 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_CONTEXT_ADDRESS_HI 0x0000001e /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_PRIV_OFFSET 0x00000014 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS 0x0000001c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_CONTEXT_ADDRESS_HI 0x0000001f /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_GFXP_RC_OFFSET 0x0000001d /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS 0x00000017 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_CONTEXT_ADDRESS_HI 0x00000022 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_PRIV_OFFSET 0x00000018 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_ZCULL_MODE 0x00000019 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CBC_CLEAR_ACTIVE 0x0000001b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_FMODEL_TESTS 0x00000020 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_WATCHDOG_TIMEOUT 0x00000021 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SET_GFID 0x00000024 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS 0x00000026 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_CONTEXT_ADDRESS_HI 0x00000023 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_PRIV_OFFSET 0x00000027 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SEND_PM_MODE 0x00000028 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_TEST_MODE 0x00000029 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_PCIE_TRAINING 0x00000050 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_CONTROL_ZBC_TABLES_SAVE 0x00000061 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_START 0x00000062 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_SAVE_SM_PERF_COUNTERS_END 0x00000063 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_RESTORE_SM_PERF_COUNTERS 0x00000064 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_RESTORE_HWPM_CONTROL_REGS 0x00000065 /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_SAVE_TASKS 0x0000006b /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_PERFORM_PRE_RESTORE_TASKS 0x0000006c /* -W--V */ #define NV_PGPC_PRI_GPCCS_METHOD_PUSH_A_ADR_INJECT_STACK_CANARY_ERROR 0x00000070 /* -W--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_DATA 0x000028b8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_DATA_FIELD 31:0 /* RWXVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG 0x000028bc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_ENGINE_RESET 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CONTEXT_RESET 0x00000002 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_INSTANCE_BIND 0x00000003 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_SAVE_ENGINE_REGS 0x00000006 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_RESTORE_ENGINE_REGS 0x00000007 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_SAVE 0x00000008 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE 0x0000000e /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE 0x00000010 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE 0x00000011 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE 0x00000009 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_SAVE_ONLY 0x0000000a /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_SAVE_ONLY 0x00000005 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_SAVE_ONLY 0x00000012 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_SAVE_ONLY 0x00000013 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CTA_PREEMPT_RESTORE 0x0000000f /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GFXP_PREEMPT_RESTORE 0x00000014 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_CILP_PREEMPT_RESTORE 0x00000015 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_RESTORE 0x0000000b /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_START_GOLDEN_RESTORE 0x0000000c /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_PATCH_BUFFER_END 0x0000000d /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_STREAM_TAG_ACTION_CTXSW_END 0x00000004 /* -W--T */ #define NV_PGPC_PRI_GPCCS_CTXSW_FORCE_NONIDLE 0x00002424 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_ACTIVE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_FORCE_NONIDLE_OVERRIDE_INACTIVE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE 0x00002420 /* R--4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE_FALCON 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE_FORCED 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE_RC_LANES 2:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE_PRIV_SEQUENCER 3:3 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_IDLESTATE_GPCCS 15:15 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_GPC_0 0x00002c04 /* R--4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_GPC_0_HWW 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_GPC_0_CTXSW_HALT 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_GPC_0_STOP_SM 2:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1 0x00002400 /* R--4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_CONSTANT_0 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_LOCAL_PRIV_ERROR 1:1 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_RC_LANES 2:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_RC_LANES_IDLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_RC_LANES_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET 3:3 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_ACTIVE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_CONTEXT_RESET_DISABLED 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL 4:4 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_BUSY 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRI_SEQUENCER_TO_FUNNEL_IDLE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER 5:5 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_IDLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_SEQUENCER_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_READ 6:6 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_READ_DONE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_READ_NOT_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WRACK 7:7 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WRACK_DONE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WRACK_NOT_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP0 8:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP0_DONE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP0_NOT_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP1 9:9 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP1_DONE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_COMP1_NOT_DONE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER 10:10 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_DFD_TRIGGER_INACTIVE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER 11:11 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_WATCHDOG_TRIGGER_INACTIVE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_ARB_BUSY 12:12 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_ARB_NACK 13:13 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_ARB_HALTED 14:14 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_ARB_FLUSH_WHEN_BUSY 15:15 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_CTXSW_CHECKSUM_MISMATCH 16:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL 28:28 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_VIOLATION 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_PL_IDLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_ERROR 29:29 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP 30:30 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_WRITE_DROPPED 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_DECODE_TRAP_IDLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_CTXSW_STATUS_1_PRIV_UCODE_TRAP_INACTIVE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG 0x00002404 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL0_BIT 4:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL0_BIT_V0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL0_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL1_BIT 12:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL1_BIT_V0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG 13:13 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SEL1_STATUS_REG_CTXSW_STATUS_1 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_COMBINATION 16:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_COMBINATION_OR 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_COMBINATION_AND 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SENSE 18:17 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SENSE_RISING_EDGE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SENSE_FALLING_EDGE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_1 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_CFG_SENSE_LEVEL_0 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_WATCHDOG 0x00002430 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_WATCHDOG_COUNT 29:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_WATCHDOG_COUNT_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_WATCHDOG_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_WATCHDOG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_WATCHDOG_ENABLE_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK 0x00002434 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_0 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_1 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_2 2:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_2_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_2_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_3 3:3 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_3_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_3_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_4 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_4_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_4_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_5 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_5_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_5_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_6 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_6_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_6_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_7 7:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_7_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_INT_ACK_7_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL 0x00002614 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_HALT 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_HALT_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_HALT_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER 2:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_HALT_SEQUENCER_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_GPC_CONTEXT_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_ZCULL_RT_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_RESET_CTL_TBCS_HOST2ALL_RESET_DISABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ENGINE_RESET_CTL 0x00002610 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET 0:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_ENABLED 0x00000000 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ENGINE_RESET_CTL_GPC_ENGINE_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_CTL_SIGS 0x0000288c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_CTL_SIGS_CTXSW_FREEZE_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX(i) (0x00002800+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX__SIZE_1 18 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PASS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FAIL 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_PASS 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_BIND_POINTER_FAIL 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_MAGIC 0x12345678 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_WAIT_FOR_MODS 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_STOP_WAIT_FOR_MODS 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_1 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_2 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SYNC_POINT_3 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_INIT_FAILED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_METHOD 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_METHOD_QUEUE_OVERFLOW 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_FIRMWARE_METHOD_PARAMETER 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SIDEBAND_METHOD_QUEUE_OVERFLOW 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_METHOD_QUEUE_OVERFLOW 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_BECS_RC_NON_ZERO 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_BAD_CTXSW_IMAGE 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_GPCCS 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SECURE_FAIL_FECS_AND_GPCCS 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_WITH_VPR_CONTEXT 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PRI_SEQ_ERROR 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_CTXSW_CHECKSUM_MISMATCH 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_CSB_ERROR 0x00000022 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PATCH_BUFFER_ACCESS_VIOLATION 0x00000023 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FALCON_STACK_CANARY_CHECK_FAILED 0x00000024 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_1_FAILED 0x00000025 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SCRUB_STEP_CHECK_2_FAILED 0x00000026 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_INDEX_OOB 0x00000027 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_POINTER_OVERFLOW 0x00000028 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_OFFSET_OVERFLOW 0x00000029 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_TIMESTAMP_BUFFER_FULL 0x00000030 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_ARBITER_COMMANDS 0x00000031 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_NUM_GPC_MISMATCH 0x00000032 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_NUM_TPC_MISMATCH 0x00000033 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GFXP_IN_SMC_MODE 0x00000034 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_SMC_IN_LEGACY 0x00000035 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_RESTORE_LEGACY_IN_SMC 0x00000036 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SMC_LTS_MASK_INDEX_OUT_OF_BOUNDS 0x00000037 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SYS_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000038 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GPC_RAMCHAIN_IMAGE_SIZE_MISMATCH 0x00000039 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SYS_PRI_IMAGE_SIZE_MISMATCH 0x00000040 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GPC_PRI_IMAGE_SIZE_MISMATCH 0x00000041 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_MAX_LTS_PER_LTC 0x00000042 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_NUM_PPC_MISMATCH 0x00000043 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_TRIVIAL_ACK_WITHOUT_NOCHSW 0x00000044 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_SECOND_RESTORE_WITH_NOCHSW 0x00000045 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_INVALID_PRIV_ACCESS_MAP_CONFIG 0x00000046 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_LTC_COUNT_OVERFLOW 0x00000047 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_REV_ID_CHECK_FAILED 0x00000048 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_CHIP_ID_CHECK_FAILED 0x00000049 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_ILLEGAL_FALCON_LEVEL 0x00000050 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_SEC_NOT_ENABLED 0x00000051 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_PRIV_ACCESS_VIOLATION 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_FIRMWARE_MTHD_VERIF_VIOLATION 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_OOB 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_NOT_IN_WHITELIST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_PRIV_ACCESS_MAP_ALLOW_NONE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_KILL 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_OOB 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_MAILBOX_VALUE_GLOBAL_ACCESS_MAP_NOT_IN_WHITELIST 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET(i) (0x00002848+(i)*4) /* -W-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET__SIZE_1 6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_SET_VALUE 31:0 /* -W-VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR(i) (0x00002860+(i)*4) /* -W-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR__SIZE_1 6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_CLEAR_VALUE 31:0 /* -W-VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX(i) (0x000028c0+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX__SIZE_1 6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_FUNCTION_TRACING_MAILBOX_VALUE 31:0 /* -W-VF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK 0x00002878 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_LOCAL_FALCON_ENABLED 0x00080040 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1(i) (0x000028d8+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__SIZE_1 3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE 31:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP1__PRIV_LEVEL_MASK 0x00002878 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK 0x0000287c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_LEVEL3_ENABLED 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2(i) (0x000028e4+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__SIZE_1 3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE 31:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP2__PRIV_LEVEL_MASK 0x0000287c /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK 0x000028fc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3(i) (0x000028f0+(i)*4) /* RW-4A */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__SIZE_1 3 /* */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE 31:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3_VALUE_DEFAULT 0x00000000 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_CTXSW_SECURE_SCRATCH_GROUP3__PRIV_LEVEL_MASK 0x000028fc /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK 0x00002428 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_SOURCE_FALCON_FECS_GPCCS_ENABLED 0x00080174 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */ #define NV_PGPC_PRI_GPCCS_COMP_FS_CONFIG 0x0000240c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_COMP_FS_CONFIG__PRIV_LEVEL_MASK 0x00002428 /* */ #define NV_PGPC_PRI_GPCCS_COMP_FS_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_FS_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_ACTIVE_CONFIG 0x00002410 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_COMP_ACTIVE_CONFIG__PRIV_LEVEL_MASK 0x00002428 /* */ #define NV_PGPC_PRI_GPCCS_COMP_ACTIVE_CONFIG_EN 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_ACTIVE_CONFIG_EN_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_FINISHED 0x00002414 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_COMP_FINISHED__PRIV_LEVEL_MASK 0x00002428 /* */ #define NV_PGPC_PRI_GPCCS_COMP_FINISHED_BITS 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_COMP_FINISHED_BITS_RESET 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE(i) (0x00002418+(i)*4) /* -W-4A */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE__SIZE_1 2 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE__PRIV_LEVEL_MASK 0x00002428 /* */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT0 0:0 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT0_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT0_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT1 1:1 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT1_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT1_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT2 2:2 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT2_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT2_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT3 3:3 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT3_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT3_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT4 4:4 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT4_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT4_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT5 5:5 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT5_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT5_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT6 6:6 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT6_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT6_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT7 7:7 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT7_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT7_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT8 8:8 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT8_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT8_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT9 9:9 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT9_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT9_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT10 10:10 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT10_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT10_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT11 11:11 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT11_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT11_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT12 12:12 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT12_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT12_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT13 13:13 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT13_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT13_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT14 14:14 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT14_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT14_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT15 15:15 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT15_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT15_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT16 16:16 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT16_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT16_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT17 17:17 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT17_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT17_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT18 18:18 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT18_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT18_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT19 19:19 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT19_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT19_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT20 20:20 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT20_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT20_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT21 21:21 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT21_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT21_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT22 22:22 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT22_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT22_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT23 23:23 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT23_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT23_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT24 24:24 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT24_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT24_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT25 25:25 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT25_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT25_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT26 26:26 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT26_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT26_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT27 27:27 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT27_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT27_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT28 28:28 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT28_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT28_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT29 29:29 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT29_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT29_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT30 30:30 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT30_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT30_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT31 31:31 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT31_SET 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_COMP_SET_DONE_BIT31_I 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_FS 0x00002604 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FS_NUM_AVAILABLE_GPCS 4:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FS_NUM_AVAILABLE_FBPS 20:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FS_NUM_AVAILABLE_LTCS 28:24 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FS_GPC 0x00002608 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FS_GPC_NUM_AVAILABLE_TPCS 4:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FS_GPC_NUM_AVAILABLE_ZCULLS 20:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_FS_GPC_NUM_AVAILABLE_ROPS 25:21 /* R--VF */ #define NV_PGPC_PRI_GPCCS_GPC_INFO 0x00002618 /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_INFO_GLOBAL_GPC_ID 4:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_GPC_INFO_SMC_LOCAL_GPC_ID 12:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_GPC_INFO_UGPU_ID 13:13 /* R--VF */ #define NV_PGPC_PRI_GPCCS_SMC_CONFIGURATION 0x0000261c /* R--4R */ #define NV_PGPC_PRI_GPCCS_SMC_CONFIGURATION_MODE 0:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_SMC_CONFIGURATION_MODE_LEGACY_MODE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_SMC_CONFIGURATION_MODE_SMC_MODE 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_SMC_CONFIGURATION_SMC_ENGINE_ID 20:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON 0x00002620 /* R--4R */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_IMEM_SZ 7:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_IMEM_SZ_4K 0x00000010 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_IMEM_SZ_6K 0x00000018 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_IMEM_SZ_8K 0x00000020 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_IMEM_SZ_12K 0x00000030 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_DMEM_SZ 15:8 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_DMEM_SZ_2K 0x00000008 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_DMEM_SZ_4K 0x00000010 /* R---V */ #define NV_PGPC_PRI_GPCCS_CFG_FALCON_DMEM_SZ_8K 0x00000020 /* R---V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS 0x00002cfc /* RW-4R */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC0 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC0_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC0_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC1 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC1_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC1_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC2 2:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC2_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC2_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC3 3:3 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC3_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC3_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC4 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC4_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC4_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC5 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC5_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC5_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC6 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC6_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC6_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC7 7:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC7_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_TPCCS_STATUS_TPC7_BUSY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANES 0x00002880 /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANES_NUM_CHAINS 5:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN 0x00002884 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE0 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE0_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE0_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE1 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE1_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE1_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE2 2:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE2_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE2_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE3 3:3 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE3_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE3_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE4 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE4_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE4_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE5 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE5_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE5_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE6 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE6_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE6_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE7 7:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE7_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE7_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE8 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE8_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE8_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE9 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE9_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE9_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE10 10:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE10_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE10_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE11 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE11_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE11_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE12 12:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE12_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE12_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE13 13:13 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE13_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE13_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE14 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE14_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE14_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE15 15:15 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE15_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE15_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE16 16:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE16_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE16_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE17 17:17 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE17_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RUN_LANE17_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS 0x00002888 /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE0 0:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE0_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE0_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE1 1:1 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE1_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE1_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE2 2:2 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE2_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE2_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE3 3:3 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE3_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE3_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE4 4:4 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE4_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE4_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE5 5:5 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE5_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE5_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE6 6:6 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE6_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE6_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE7 7:7 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE7_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE7_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE8 8:8 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE8_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE8_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE9 9:9 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE9_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE9_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE10 10:10 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE10_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE10_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE11 11:11 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE11_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE11_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE12 12:12 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE12_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE12_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE13 13:13 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE13_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE13_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE14 14:14 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE14_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE14_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE15 15:15 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE15_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE15_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE16 16:16 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE16_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE16_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE17 17:17 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE17_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_STATUS_LANE17_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SCRUB 0x00002640 /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SCRUB_STATUS 31:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SCRUB_STATUS_INIT 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SCRUB_STATUS_CLEAN 0xffffffff /* R---V */ #define NV_PGPC_PRI_GPCCS_SIMULATION_OPTIONS 0x00002644 /* R--4R */ #define NV_PGPC_PRI_GPCCS_SIMULATION_OPTIONS_MODEL 1:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_SIMULATION_OPTIONS_MODEL_GATES 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_SIMULATION_OPTIONS_MODEL_RTL 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_SIMULATION_OPTIONS_MODEL_FMODEL 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS 0x00002678 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_IMEM_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_DMEM_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_IMEM_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_DMEM_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_RESET 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_RESET_TASK 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_STATUS_RESET_INIT 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT 0x0000267c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT 0x00002680 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS 0x00002684 /* R--4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS_INDEX 22:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS_ROW_ADDRESS 19:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM 22:20 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_IMEM 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_ADDRESS_SOURCE_RAM_FALCON_DMEM 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK 0x00002688 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL 0x0000268c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL__PRIV_LEVEL_MASK 0x00002688 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO 0x00002690 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_ADDRESS 25:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_ADDRESS_V 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE 30:29 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_INVALID 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_READ 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_ACK 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_TRANSACTION_TYPE_WRITE_NO_ACK 0x00000003 /* R---V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_SOURCE 31:31 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_SOURCE_PRI_SEQ 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_INFO_SOURCE_FALCON_CSB 0x00000001 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_CODE 0x00002694 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_CODE_VALUE 31:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_CODE_VALUE_V 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_SUBID_INFO 0x000026a0 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID 7:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_SUBID_INFO_TRANSACTION_SUBID_V 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID 15:8 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PRI_ERROR_SUBID_INFO_RETURN_SUBID_V 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK 0x00002950 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_ramchain_cmd_wr_secure" /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_FUSE0 0x000fffff /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_IFF_GPCCS_FECS_GSP_SEC2_FUSE1 0x0008007c /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL 0x00002904 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_COMPRESSION 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_COMPRESSION_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_COMPRESSION_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET 9:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_BLOAT_BUDGET_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS 27:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CONTROL_COMPRESSION_SETTINGS__0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVE_OFFSET 0x00002908 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_OFFSET 0x0000290c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_OFFSET_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_OFFSET_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_OFFSET 0x0000292c /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_OFFSET_V 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_OFFSET_V_0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_SUBOFFSET 0x00002930 /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V 5:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CURRENT_SUBOFFSET_V_0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SIZE 0x00002910 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SIZE__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SIZE_V 23:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SIZE_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET 0x00002914 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET_V 13:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_PREFETCH_OFFSET_V_10 0x0000000a /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_WORDS 0x00002934 /* R--4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_WORDS__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_WORDS_V 23:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_WORDS_V_0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_WORDS 0x00002938 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_WORDS__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_WORDS_V 23:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_RESTORE_WORDS_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_DATA 0x00002918 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_DATA__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_DATA_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC 0x0000291c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC_RAMID 9:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC_RAMID_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC_OFFSET 31:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_LOC_OFFSET_V 0x0000000f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG 0x00002920 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_DELAY 6:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_DELAY_V 0x00000041 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_CREDITS 21:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_CREDITS_V 0x0000003f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_CFG_AUTOSEEK_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS 0x0000293c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS_V 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS_V_3 0x00000003 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS_V_WFI 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_RCCLASS_V_GFXP 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS 0x00002924 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD 4:0 /* RW-VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_IDLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SEEK 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_DISCOVER_LENGTH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SAVE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RESTORE 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_LOAD 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_READ_POP 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_WRITE_PUSH 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_ENABLE 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_RAMID_DISABLE 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_ENABLE 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_DISABLE 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_ENABLE 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CHAIN_DISABLE 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_CLASS_OVERRIDE 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_FLUSH 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_LAST_CMD_SUSPEND 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_CURRENT 9:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_CURRENT_IDLE 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_STATUS_CURRENT_BUSY 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC 0x00002928 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD 4:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_SEEK 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_DISCOVER_LENGTH 0x00000002 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_SAVE 0x00000003 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_RESTORE 0x00000004 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_LOAD 0x00000005 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_READ_POP 0x00000006 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_WRITE_PUSH 0x00000007 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_ENABLE 0x00000008 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_RAMID_DISABLE 0x00000009 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_ENABLE 0x0000000a /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_DISABLE 0x0000000b /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_ENABLE 0x0000000c /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_CHAIN_DISABLE 0x0000000d /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_CLASS_OVERRIDE 0x0000000e /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_FLUSH 0x0000000f /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_SUSPEND 0x00000010 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CMD_EXEC_CMD_SCRUB 0x00000011 /* -W--T */ #define NV_PGPC_PRI_GPCCS_RC_LANE_COMPUTED_CHECKSUM 0x00002944 /* R-E4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_CHECKSUM 0x00002948 /* R-E4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS 31:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM 0x0000294c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM__PRIV_LEVEL_MASK 0x00002950 /* */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_CTRL_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_CTRL_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_STATUS_MATCH 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_RC_LANE_CHECKSUM_STATUS_MISMATCH 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK 0x00002760 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLED_FUSE1 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pri_sequencer_wr_secure" /* */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000fffff /* RWB-V */ #define NV_PGPC_PRI_GPCCS_PVS_PRIV_LEVEL_MASK_SOURCE_ENABLE_LOCAL_FALCON_JTAG_IFF_SEC2_ENABLED_FUSE1 0x00080144 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_OFFSET 0x00002700 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_OFFSET__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_OFFSET 0x00002704 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_OFFSET__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_OFFSET_V 31:0 /* RW-VF */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_OFFSET_V_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_COUNT 0x00002748 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_COUNT_V 15:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PVS_SAVE_COUNT_V_0 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_COUNT 0x0000274c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_COUNT__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_COUNT_V 15:0 /* RW-VF */ #define NV_PGPC_PRI_GPCCS_PVS_RESTORE_COUNT_V_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_CURRENT_OFFSET 0x00002708 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PVS_CURRENT_OFFSET_V 31:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_PVS_CURRENT_SUBOFFSET 0x0000270c /* R--4R */ #define NV_PGPC_PRI_GPCCS_PVS_CURRENT_SUBOFFSET_V 5:0 /* R-XVF */ #define NV_PGPC_PRI_GPCCS_PVS_REGISTER_BASE_ADDR 0x00002710 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_REGISTER_BASE_ADDR_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_REGISTER_BASE_ADDR 0x00002724 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PV_REGISTER_BASE_ADDR__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_REGISTER_BASE_ADDR_V 25:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_REGISTER_BASE_ADDR_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_ST_CONSTANT 0x00002744 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_ST_CONSTANT__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_ST_CONSTANT_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_ST_CONSTANT_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE 0x00002714 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_MODE__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES 4:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FIFO_FREE_ENTRIES_IV 0x00000010 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES 12:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FIFO_TOTAL_ENTRIES_IV 0x00000010 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_DIRECTION 16:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_DIRECTION_SAVE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_DIRECTION_RESTORE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_START 17:17 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_START_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_START_T 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FINISH 18:18 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FINISH_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_FINISH_T 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_NO_ADDR_INC 19:19 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_NO_ADDR_INC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_NO_ADDR_INC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_PRIV_LEVEL 29:28 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_PRIV_LEVEL_NONE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL 30:30 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_MODE_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL 0x00002740 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_PREFETCH_CTL_OFFSET_10 0x0000000a /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_INCREMENT 0x00002718 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_INCREMENT__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_INCREMENT_V 15:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_INCREMENT_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_MASK 0x0000271c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_MASK__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_MASK_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_INDEX_MASK_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH 0x00002720 /* -W-4R */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_USE_BASE_ADDR 0:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_USE_INDEXER 1:1 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_ADDR 25:2 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_REGISTER_COUNT 30:26 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL 31:31 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_DATA 25:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_COUNT 11:0 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD 30:26 /* -WXVF */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_NOP 0x00000000 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_WAIT 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_STORE_CONSTANT 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SKIP_DATA 0x00000003 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PVS_FIFO_PUSH_SPECIAL_CMD_SET_REG_COUNT 0x00000004 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ 0x00002728 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_ADDR 25:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_ADDR_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_CMD 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_CMD_NONE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_CMD_GO 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A 0x00002734 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_ADDR 25:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_ADDR_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_CMD 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_CMD_NONE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_A_CMD_GO 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B 0x00002738 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_USE_BASE_ADDR_NOT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_ADDR 25:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_ADDR_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL 26:26 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_LOWER_PRIV_LEVEL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS 28:27 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_IDLE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_STATUS_DONE 0x00000002 /* R---V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE 30:29 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_READ 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_UNDEF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_TRANS_TYPE_WRITE_ACK 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_CMD 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_CMD_NONE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_B_CMD_GO 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA 0x0000272c /* R--4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA_V 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA_A 0x00002754 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA_A_V 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA_B 0x00002758 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_READ_DATA_B_V 31:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA 0x00002730 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_A 0x0000273c /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_A__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_A_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_A_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_B 0x00002750 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_B__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_B_V 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_WRITE_DATA_B_V_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_STATUS 0x00002764 /* R--4R */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL 1:0 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_A 5:4 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PV_PRIV_REQ_STATUS_PRIV_LEVEL_B 9:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PVS_COMPUTED_CHECKSUM 0x00002774 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PVS_COMPUTED_CHECKSUM__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_COMPUTED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_SAVED_CHECKSUM 0x00002778 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_PVS_SAVED_CHECKSUM__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_SAVED_CHECKSUM_RESULTS 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_SAVED_CHECKSUM_RESULTS_START 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM 0x0000277c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM__PRIV_LEVEL_MASK 0x00002760 /* */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_CTRL 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_CTRL_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_CTRL_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_STATUS 8:8 /* R--VF */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_STATUS_MATCH 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_PVS_CHECKSUM_STATUS_MISMATCH 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_ARB_LANE_CTL 0x00002a00 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_LANE_CTL_RETURN_FIFO_ENTRIES_V 0x00000008 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_LANE_CTL_WRR_WEIGHT 6:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_LANE_CTL_WRR_WEIGHT_V 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_BASE_ADDR 0x00002a04 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_BASE_ADDR_F 31:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_HI_BASE_ADDR 0x00002a38 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_HI_BASE_ADDR_F 8:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_HI_BASE_ADDR_F_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL 0x00002a3c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_ENGINE_ID 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_VEID0 0x00000040 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_ENGINE_ID_BAR2_FN0 0x000000c0 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_VEID 21:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_VEID_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_GFID 29:24 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_ENGINE_CTL_GFID_0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL 0x00002a08 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL_OFFSET 13:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_PREFETCH_CTL_OFFSET_V 0x0000000a /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK 0x00002a28 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD 0x00002a10 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD__PRIV_LEVEL_MASK 0x00002a28 /* */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD 4:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_FLUSH 0x00000005 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_SOFT_FLUSH 0x00000006 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_BIND_INST_BLK_PTR 0x00000007 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_MMU_TLB_INVALIDATE 0x00000009 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_PREFETCH 0x0000000a /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHYSICAL_L2_CACHE_MGMT 0x0000000b /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_VIRTUAL_L2_CACHE_MGMT 0x0000000c /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_PEER_INVALIDATE 0x0000000d /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_L2_SYSMEM_INVALIDATE 0x0000000e /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_CLEAN_COMPTAGS 0x0000000f /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_FB_OP_PHY_L2_FLUSH_DIRTY 0x00000010 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_CMD_MEMBAR 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_SUB_OP 8:7 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_SUB_OP_INVALIDATE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_SUB_OP_CLEAN 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_SUB_OP_DEMOTE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE 9:9 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACCESS_CTR_NOTIFICATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK 17:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_DEFAULT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_TLB 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_MEM 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_NONE_REQUIRED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_GLOBALLY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_ACK_INTRANODE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_HALT 30:30 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_HALT_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_HALT_REQUEST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_UNHALT 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_UNHALT_V 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CTX_CMD_UNHALT_REQUEST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL 0x00002a14 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_WR 1:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_WR_FIRST 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_WR_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_WR_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_RD 9:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_RD_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_RD_NORMAL 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_L2_EVICTION_CTL_RD_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_PRIV 0x00002a18 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_PRIV_OVERRIDE 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_PRIV_OVERRIDE_PRIV 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_PRIV_OVERRIDE_NONPRIV 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS 0x00002a1c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_CLEAR 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_CLEAR_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_CLEAR_CLEAR 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_ACK 1:1 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_ACK_OK 0x00000001 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_ACK_NACK 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_SUBID 15:2 /* R--VF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_OUTSTANDING_TRANSACTIONS 23:16 /* R--VF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_BUFFER_NOT_EMPTY 24:24 /* R--VF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY 28:28 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_DEFAULT 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_FLUSH_WHEN_BUSY_ERROR 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_HALTED 30:30 /* R--VF */ #define NV_PGPC_PRI_GPCCS_ARB_STATUS_BUSY 31:31 /* R--VF */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE 0x00002a20 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_CMD 4:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_CMD_VIRTUAL 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_VID_MEM 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_CMD_PHYS_SYS_MEM_COHERENT 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_CMD_OVERRIDE_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR 0x00002a2c /* RWE4R */ #define NV_PGPC_PRI_GPCCS_ARB_WPR__PRIV_LEVEL_MASK 0x00002a28 /* */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_RC_ID 1:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_RC_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_RC_SECURE_LEVEL 5:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_RC_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PVS_ID 9:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PVS_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PVS_SECURE_LEVEL 13:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_PVS_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_ID 17:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_ID_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_SECURE_LEVEL 21:20 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_SECURE_LEVEL_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES 24:24 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_BLOCKED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_WPR_CMD_OVERRIDE_PHYSICAL_WRITES_ALLOWED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK 0x00002a30 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000c /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWB-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG 0x00002a34 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG__PRIV_LEVEL_MASK 0x00002a30 /* */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T0 3:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T0_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T1 7:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T1_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T2 11:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T3 15:12 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T3_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T4 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T4_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T5 23:20 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T5_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T6 27:24 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T6_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T7 31:28 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_ARB_FALCON_REGIONCFG_T7_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON 0x000028a0 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL 6:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_FB_CMD 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_FB_CMD2 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_FB_CMD3 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_FB_DATA 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_0 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_1 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_0 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_1 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_2 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_3 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_4 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_5 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_6 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_7 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_8 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_9 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_10 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_11 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_12 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_13 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_14 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_15 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_17 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_18 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_0 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_1 0x0000001a /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_2 0x0000001b /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_3 0x0000001c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_4 0x0000001d /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_5 0x0000001e /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_6 0x0000001f /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_7 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_8 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_9 0x00000022 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_RC_10 0x00000023 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_0 0x00000024 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_1 0x00000025 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_2 0x00000026 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_3 0x00000027 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_4 0x00000028 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_5 0x00000029 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_6 0x0000002a /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_7 0x0000002b /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_9 0x0000002d /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_10 0x0000002e /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PROBE_0 0x0000002f /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PROBE_1 0x00000030 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_ARB_0 0x00000031 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_ARB_1 0x00000032 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_ERR 0x00000033 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_2 0x00000034 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_3 0x00000035 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_4 0x00000036 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_5 0x00000037 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_MISC_6 0x00000038 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_19 0x00000039 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_20 0x0000003a /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_21 0x0000003b /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_22 0x0000003c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_23 0x0000003d /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_24 0x0000003e /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_25 0x0000003f /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_26 0x00000040 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_27 0x00000041 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_28 0x00000042 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_29 0x00000043 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_30 0x00000044 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_31 0x00000045 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_32 0x00000046 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_33 0x00000047 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_34 0x00000048 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_35 0x00000049 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_PRI_36 0x0000004a /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATIC_PATTERN_55_8_GROUP 0x0000004b /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATIC_PATTERN_AA_8_GROUP 0x0000004c /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_11 0x0000004d /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_12 0x0000004e /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_13 0x0000004f /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_14 0x00000050 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_STATUS_15 0x00000051 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_CTXSW_0 0x00000052 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_SEL_ECC_ERR 0x00000053 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_CTRL_ENABLE 8:8 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM 0x000028a8 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT0 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT1 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT2 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT3 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT4 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT5 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT6 0x00000040 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_PROBE_TOGGLE_BIT7 0x00000080 /* RW--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET 23:16 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_INIT 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT0 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT1 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT2 0x00000004 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT3 0x00000008 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT4 0x00000010 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT5 0x00000020 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT6 0x00000040 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_SET_BIT7 0x00000080 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR 31:24 /* -WEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_INIT 0x00000000 /* -WE-V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT0 0x00000001 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT1 0x00000002 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT2 0x00000004 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT3 0x00000008 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT4 0x00000010 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT5 0x00000020 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT6 0x00000040 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_PM_CLEAR_BIT7 0x00000080 /* -W--V */ #define NV_PGPC_PRI_GPCCS_PERFMON_MODE 0x000028a4 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_PERFMON_MODE_PROBE 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_PERFMON_MODE_PROBE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0 0x00002c80 /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP 2:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_SETUP_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR 5:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_CRSTR_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL 8:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_ZCULL_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP 11:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_WIDCLIP_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR 14:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_FRSTR_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC 17:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_TC_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB 20:18 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_RASTERARB_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP 23:21 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_PROP_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS 26:24 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY0_GPCCS_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1 0x00002c84 /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD 2:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMPD_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD 5:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMSD_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT 8:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPMREPORT_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX 11:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_SWDX_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS 14:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_WDXPS_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC 17:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GCC_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0 20:18 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GPCMMU0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC 23:21 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY1_GNIC_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2 0x00002c88 /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0 2:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1 5:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2 8:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_PES2_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0 11:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1 14:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2 17:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_CBMGR2_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0 20:18 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1 23:21 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2 26:24 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY2_WWDX2_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3 0x00002c8c /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0 2:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1 5:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2 8:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC2_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3 11:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC3_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4 14:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC4_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5 17:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY3_TPC5_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4 0x00002c9c /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0 2:0 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1 5:3 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_CROP1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0 8:6 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1 11:9 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_ZROP1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0 14:12 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH0_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1 17:15 /* R-IVF */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_EMPTY 0x0 /* R-I-V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_ACTIVE 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_PAUSED 0x2 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_QUIESCENT 0x3 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_PREEMPTED 0x4 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_STALLED 0x5 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_FAULTED 0x6 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_ACTIVITY4_RRH1_HALTED 0x7 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION 0x00002c90 /* R--4R */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PROP 0:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PROP_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PROP_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZCULL 1:1 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZCULL_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZCULL_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GCC 2:2 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GCC_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GCC_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_SETUP 3:3 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_SETUP_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_SETUP_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES0 4:4 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES1 5:5 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES1_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES2 6:6 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES2_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_PES2_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCMMU0 13:13 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCMMU0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCMMU0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCCS 14:14 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCCS_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_GPCCS_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_TPC 8+15:16 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_TPC_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_TPC_0_NOT_PENDING 0x00000000 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_TPC_0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP0 26:26 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP0 27:27 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH0 28:28 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH0_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH0_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP1 29:29 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_CROP1_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP1 30:30 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_ZROP1_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH1 31:31 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH1_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_RRH1_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN 0x00002c94 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PROP 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PROP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PROP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZCULL 1:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZCULL_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZCULL_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GCC 2:2 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GCC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GCC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_SETUP 3:3 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_SETUP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_SETUP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES0 4:4 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES1 5:5 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES2 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES2_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_PES2_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCMMU0 13:13 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCMMU0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCCS 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCCS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_GPCCS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_TPC 8+15:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_TPC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_TPC_0_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_TPC_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP0 26:26 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP0 27:27 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH0 28:28 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP1 29:29 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_CROP1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP1 30:30 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_ZROP1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH1 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_GPC_EXCEPTION_EN_RRH1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_HWW_ESR 0x00002c98 /* R--4R */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_CORRECTED 0:0 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_UNCORRECTED 1:1 /* R-EVF */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_GPCCS_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_GPCCS_DEBUG 0x00002698 /* RW-4R */ #define NV_PGPC_PRI_GPCCS_DEBUG_STATUS_FILTER 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_DEBUG_STATUS_FILTER_INIT 0x16 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_DEBUG_STATUS_FILTER_20 0x14 /* RW--V */ #define NV_PGPC_PRI_GPCCS_DEBUG_STATUS_FILTER_22 0x16 /* RW--V */ #define NV_PGPC_PRI_GPCCS_STOP_SM 0x0000269c /* RW-4R */ #define NV_PGPC_PRI_GPCCS_STOP_SM_BIT 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_STOP_SM_BIT_CLR 0x0 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_STOP_SM_BIT_SET 0x1 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG 0x00002890 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_DLY_CNT__PROD 0x0000003F /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GPCCS_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GPCCS_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GPCCS_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GPCCS_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GPCCS_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_CG1 0x00002894 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG1_SLCG 15:1 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_CG1_SLCG_DISABLED 0x00007FFF /* RWE-V */ #define NV_PGPC_PRI_GPCCS_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG 0x000028b0 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_DLY_CNT__PROD 0x0000003F /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPCCS_FALCON_CG1 0x000028B4 /* RWE4R */ #define NV_PGPC_PRI_GPCCS_FALCON_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPCCS_FALCON_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPCCS_FALCON_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP 0x000005FF:0x00000400 /* RW--L */ #define NV_PGPC_PRI_PROP_DEBUG1 0x00000400 /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_3D 2:2 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_3D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_3D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_3D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_2D 3:3 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_2D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_2D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_FRSTR_2D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_3D 4:4 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_3D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_3D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_3D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_2D 5:5 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_2D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_2D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_CSB_2D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SBFILTER 7:7 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SBFILTER_ENABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SBFILTER_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SBFILTER_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_FORCE_NO_COMPRESSION 8:8 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_FORCE_NO_COMPRESSION_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_FORCE_NO_COMPRESSION_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_FORCE_NO_COMPRESSION_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_ZCOMPRESS 9:9 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_ZCOMPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_ZCOMPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_ZCOMPRESS_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_CCOMPRESS 10:10 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_CCOMPRESS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_CCOMPRESS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_CCOMPRESS_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_BLENDOPT 11:11 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_BLENDOPT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_BLENDOPT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_BLENDOPT_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SKIP_ZROP 12:12 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SKIP_ZROP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SKIP_ZROP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SKIP_ZROP_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB 18:17 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_Z_PRIORITY 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_C_PRIORITY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_ROUND_ROBIN 0x00000002 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_XPG_VADDR_REPLAY_ARB_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT 20:20 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_TRUNCATION_REDUCTION_OPT_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER 22:21 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_TIER_1_2_3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_FULL_ITER_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER 23:23 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_COLOR_MODULATION_AVOID_NULL_ITER_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END 24:24 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_TIR_FORCE_EOCP_AT_FRSTR_END_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_ROP_SLICE 26:25 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_ROP_SLICE_NONE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP0 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_ROP_SLICE_ROP1 0x00000002 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_SWALLOW_ROP_SLICE_BOTH 0x00000003 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM 27:27 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_KILL_BUNDLES_TO_FS_RDM_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT 28:28 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_ASSUME_FULL_CPIX_FOR_BIN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_VISIBLE_EARLY_Z 30:30 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_VISIBLE_EARLY_Z_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_VISIBLE_EARLY_Z_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_VISIBLE_EARLY_Z_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG1_RDM_DETERMINISM_MODE 31:31 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG1_RDM_DETERMINISM_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_RDM_DETERMINISM_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG1_RDM_DETERMINISM_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2 0x00000404 /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_2D_CHECK 0:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_2D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_2D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_2D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_3D_CHECK 1:1 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_3D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_3D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PITCH_3D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_ZT_CHECK 2:2 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_ZT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK 3:3 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_ZT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_CT_CHECK 4:4 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_CT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_CT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_WIDTH_3D_CT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_CT_CHECK 5:5 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_HEIGHT_3D_CT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_2D_CHECK 6:6 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_2D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_2D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_2D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_ZT_CHECK 7:7 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_ZT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_ZT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_ZT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_CT_CHECK 8:8 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_CT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_CT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_3D_CT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_2D_CHECK 9:9 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_2D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK 10:10 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_MEMLAYOUT_3D_CT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_2D_CHECK 11:11 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_2D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_2D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_2D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_3D_CHECK 12:12 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_3D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_3D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_ZBLEND_3D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK 13:13 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_2D_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK 14:14 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_ZT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK 15:15 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_KIND_SYSMEM_3D_CT_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD 18:16 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_ALWAYS 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_COMPOK_Z_PLANES_THRESHOLD_NEVER 0x00000007 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_SSAA_CHECK 19:19 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_SSAA_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_SSAA_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_SSAA_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_ZBUF_CHECK 20:20 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_ZBUF_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_ZBUF_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_TIR_ZBUF_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK 21:21 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG2_PSI_SSAA_CONF_PIX_CHECK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG3 0x00000408 /* RWE4R */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_ERROR 0:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_ERROR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_ERROR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO 11:8 /* R-EVF */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_SEEN_PIXOUT_EOST_SHADER_COVG 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_UPSTREAM_STALL_AT_EOST 0x2 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_AND_PROP_COVG_EOST_MATCHING 0x3 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_SHADER_COVG_EOST_MATCHING 0x4 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_EOST_MATCHING 0x5 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_MRT_OVERFLOW 0x6 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_CONSTANT_COLOR_NO_PIXOUT_RETIRE 0x7 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_PIXOUT_EOST_ON_LAST_RENDER_TARGET 0x8 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_CDP_ASSERTION_INFO_UNEXPECTED_PIXOUT_PACKET 0x9 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE 21:16 /* RWEVF */ #define NV_PGPC_PRI_PROP_DEBUG3_MAX_THREADS_IN_C_BINNING_TILE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE 29:24 /* RWEVF */ #define NV_PGPC_PRI_PROP_DEBUG3_MAX_THREADS_IN_Z_BINNING_TILE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_DEBUG3_TIR_PSS_COLOR_ERROR 30:30 /* R-EVF */ #define NV_PGPC_PRI_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_NOT_PENDING 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_PROP_DEBUG3_TIR_PSS_COLOR_ERROR_PENDING 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_DEBUG4 0x0000040c /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE 8:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_INIT 0x00000008 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D 10:10 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_2D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D 11:11 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_QUADS_PER_SUBTILE_OVERRIDE_3D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE 22:12 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE 23:23 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG4_MAX_PRIMS_PER_SUBTILE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS 24:24 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP0 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG4_NEXT_ROP_FOR_BYPASS_ROP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_DEBUG5 0x00000410 /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG5_CSLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG5_CSLF_WR_LIMIT_INIT 0x00000fff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG5_ZTLF_WR_LIMIT 28:16 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG5_ZTLF_WR_LIMIT_INIT 0x00001fff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG6 0x00000414 /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG6_CZLF_WR_LIMIT 11:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG6_CZLF_WR_LIMIT_INIT 0x00000fff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG6_ZPASS_WR_LIMIT 27:16 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG6_ZPASS_WR_LIMIT_INIT 0x00000fff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG7 0x00000418 /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG7_CDP_COVG_WR_LIMIT 12:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG7_CDP_COVG_WR_LIMIT_INIT 0x00001fff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG7_PXB_C_WR_LIMIT 26:16 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG7_PXB_C_WR_LIMIT_INIT 0x000007ff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG8 0x0000041C /* RWI4R */ #define NV_PGPC_PRI_PROP_DEBUG8_CBF_WR_LIMIT 10:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG8_CBF_WR_LIMIT_INIT 0x000003ff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG8_ZBF_WR_LIMIT 20:11 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG8_ZBF_WR_LIMIT_INIT 0x000001ff /* RWI-V */ #define NV_PGPC_PRI_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE 31:23 /* RWIVF */ #define NV_PGPC_PRI_PROP_DEBUG8_MAX_CPIX_IN_C_BINNING_TILE_INIT 0x000001c0 /* RWI-V */ #define NV_PGPC_PRI_PROP_HWW_ESR 0x00000420 /* RWE4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_2D_VIOL 0:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_3D_VIOL 1:1 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_PITCH_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL 2:2 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL 3:3 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_CT_VIOL 4:4 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_WIDTH_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL 5:5 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_HEIGHT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_2D_VIOL 6:6 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_ZT_VIOL 7:7 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_CT_VIOL 8:8 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL 9:9 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL 10:10 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_MEMLAYOUT_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_2D_VIOL 11:11 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_3D_VIOL 12:12 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_3D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_ZBLEND_3D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL 13:13 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_2D_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL 14:14 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_ZT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL 15:15 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_KIND_SYSMEM_3D_CT_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_SSAA_VIOL 16:16 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_SSAA_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_SSAA_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL 17:17 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_PSI_SSAA_CONF_PIX_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_ZBUF_VIOL 18:18 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_ZBUF_VIOL_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_TIR_ZBUF_VIOL_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_PROP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGPC_PRI_PROP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGPC_PRI_PROP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_COORD 0x00000434 /* R--4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_COORD_X 15:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_COORD_X_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_COORD_Y 31:16 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_COORD_Y_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT 0x00000438 /* R--4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_DST 6:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_DST_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_CT 14:8 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_CT_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_ZT 19:16 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_ZT_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_BLEND_3D 20:20 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_BLEND_3D_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_LOGICOP_3D 21:21 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_LOGICOP_3D_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_AA_SAMPLES 27:24 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_AA_SAMPLES_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_OPERATION_2D 30:28 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_FORMAT_OPERATION_2D_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE 0x0000043C /* R--4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_PTE_KIND 2:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_PTE_KIND_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_MMU_RESP 16:16 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_MMU_RESP_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_APERTURE 21:20 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_APERTURE_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_DST_C_TO_Z 22:22 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_DST_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_C_TO_Z 23:23 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_C_TO_Z_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_COMPTAG_VLD 24:24 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_COMPTAG_VLD_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_PITCH_ACTIVE 25:25 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE_PITCH_ACTIVE_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE2 0x00000440 /* R--4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE2_LAYER 11:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE2_LAYER_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE2_CT_TARGET 18:16 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_STATE2_CT_TARGET_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_HWW_ESR_OFFSET 0x00000444 /* R--4R */ #define NV_PGPC_PRI_PROP_HWW_ESR_OFFSET_V 31:0 /* R-EVF */ #define NV_PGPC_PRI_PROP_HWW_ESR_OFFSET_V_INIT 0x0 /* R-E-V */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_LO 0x00000450 /* RWI4R */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_HI 0x00000454 /* RWI4R */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_PS_INVOCATIONS_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_LO 0x00000460 /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_HI 0x00000464 /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_LO 0x0000046C /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_HI 0x00000470 /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_CNT_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_STATE_0 0x00000480 /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_0_MMU_REQ_COUNT 9:0 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_0_ZLAT_NUM_SUBID_ALLOCATED 20:10 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_0_ZLAT_LAST_SUBID_ACCEPTED_BY_ZSB 31:21 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1 0x00000484 /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB 2:0 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA 5:3 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBA_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM 8:6 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBM_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC 11:9 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBC_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD 14:12 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBD_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF 17:15 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_CSB_CSBF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB 20:18 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI 23:21 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBI_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO 29:27 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_1_SUB_SUBUNIT_STATUS_ZSB_ZSBO_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2 0x00000488 /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP 2:0 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI 5:3 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_TPI_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG 8:6 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CPG_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT 11:9 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_FUT_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF 14:12 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CSLF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF 17:15 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_CZLF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF 20:18 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_TP_ZTLF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT 23:21 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR 26:24 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPR_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF 29:27 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_2_SUB_SUBUNIT_STATUS_ZLAT_ZPF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3 0x0000048C /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG 5:3 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA 8:6 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBA_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA 11:9 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBA_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID 14:12 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_CBID_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID 17:15 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_ZBID_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF 23:21 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_PAF_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC 26:24 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGC_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ 29:27 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_3_SUB_SUBUNIT_STATUS_XPG_VAGZ_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4 0x00000490 /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP 2:0 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_VARP_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS 5:3 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_ZBS_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS 8:6 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_4_SUB_SUBUNIT_STATUS_XPG_CBS_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6 0x00000498 /* R--4R */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP 2:0 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO 8:6 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_CFIFO_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP 11:9 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TP2CDP_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH 14:12 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_DATAPATH_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM 17:15 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PIXOUT_SM_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB 20:18 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_PXB_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES 23:21 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_STATES_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD 26:24 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_TWOD_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT 29:27 /* R--VF */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_EMPTY 0x00000000 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_ACTIVE 0x00000001 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_PAUSED 0x00000002 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_QUIESCENT 0x00000003 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_STALLED 0x00000005 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_FAULTED 0x00000006 /* R---V */ #define NV_PGPC_PRI_PROP_STATE_6_SUB_SUBUNIT_STATUS_CDP_GPM2PROP_PIXOUT_HALTED 0x00000007 /* R---V */ #define NV_PGPC_PRI_PROP_PM_CTRL 0x000004A0 /* RWE4R */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL 7:0 /* RWEVF */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_10 0x0000000a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_11 0x0000000b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_12 0x0000000c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_13 0x0000000d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_14 0x0000000e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_15 0x0000000f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_26 0x0000001a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_27 0x0000001b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_28 0x0000001c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_29 0x0000001d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_30 0x0000001e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_31 0x0000001f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_42 0x0000002a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_43 0x0000002b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_44 0x0000002c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_45 0x0000002d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_46 0x0000002e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_47 0x0000002f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_48 0x00000030 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_49 0x00000031 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_50 0x00000032 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_51 0x00000033 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_52 0x00000034 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_53 0x00000035 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_54 0x00000036 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_55 0x00000037 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_56 0x00000038 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_57 0x00000039 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_58 0x0000003a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_59 0x0000003b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_60 0x0000003c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_61 0x0000003d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_62 0x0000003e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_63 0x0000003f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_64 0x00000040 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_65 0x00000041 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_66 0x00000042 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_67 0x00000043 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_68 0x00000044 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_69 0x00000045 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_70 0x00000046 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_71 0x00000047 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_72 0x00000048 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_73 0x00000049 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_74 0x0000004a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_75 0x0000004b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_76 0x0000004c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_77 0x0000004d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_78 0x0000004e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_79 0x0000004f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_80 0x00000050 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_81 0x00000051 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_82 0x00000052 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_83 0x00000053 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_84 0x00000054 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_85 0x00000055 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_86 0x00000056 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_87 0x00000057 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_88 0x00000058 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_89 0x00000059 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_90 0x0000005a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_91 0x0000005b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_92 0x0000005c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_93 0x0000005d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_94 0x0000005e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_95 0x0000005f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_96 0x00000060 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_97 0x00000061 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_98 0x00000062 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_99 0x00000063 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_100 0x00000064 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_101 0x00000065 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_102 0x00000066 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_103 0x00000067 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_104 0x00000068 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_105 0x00000069 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_106 0x0000006a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_107 0x0000006b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_108 0x0000006c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_109 0x0000006d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_110 0x0000006e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_111 0x0000006f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_112 0x00000070 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_113 0x00000071 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_114 0x00000072 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_115 0x00000073 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_116 0x00000074 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_117 0x00000075 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_118 0x00000076 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_119 0x00000077 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_120 0x00000078 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_121 0x00000079 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_122 0x0000007a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_123 0x0000007b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_124 0x0000007c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_125 0x0000007d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_126 0x0000007e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_127 0x0000007f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_128 0x00000080 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_129 0x00000081 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_130 0x00000082 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_131 0x00000083 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_132 0x00000084 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_133 0x00000085 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_134 0x00000086 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_135 0x00000087 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_136 0x00000088 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_137 0x00000089 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_138 0x0000008a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_139 0x0000008b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_140 0x0000008c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_141 0x0000008d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_142 0x0000008e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_143 0x0000008f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_144 0x00000090 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_145 0x00000091 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_146 0x00000092 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_147 0x00000093 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_148 0x00000094 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_149 0x00000095 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_150 0x00000096 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_151 0x00000097 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_152 0x00000098 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_153 0x00000099 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_154 0x0000009a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_155 0x0000009b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_156 0x0000009c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_157 0x0000009d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_158 0x0000009e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_159 0x0000009f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_160 0x000000a0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_161 0x000000a1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_162 0x000000a2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_163 0x000000a3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_164 0x000000a4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_165 0x000000a5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_166 0x000000a6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_167 0x000000a7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_168 0x000000a8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_169 0x000000a9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_170 0x000000aa /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_171 0x000000ab /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_172 0x000000ac /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_173 0x000000ad /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_174 0x000000ae /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_175 0x000000af /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_176 0x000000b0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_177 0x000000b1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_178 0x000000b2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_179 0x000000b3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_180 0x000000b4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_181 0x000000b5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_182 0x000000b6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_183 0x000000b7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_184 0x000000b8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_185 0x000000b9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_186 0x000000ba /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_187 0x000000bb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_188 0x000000bc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_189 0x000000bd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_190 0x000000be /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_191 0x000000bf /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_192 0x000000c0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_193 0x000000c1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_194 0x000000c2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_195 0x000000c3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_196 0x000000c4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_197 0x000000c5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_198 0x000000c6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_199 0x000000c7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_200 0x000000c8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_201 0x000000c9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_202 0x000000ca /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_203 0x000000cb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_204 0x000000cc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_205 0x000000cd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_206 0x000000ce /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_207 0x000000cf /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_208 0x000000d0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_209 0x000000d1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_210 0x000000d2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_211 0x000000d3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_212 0x000000d4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_213 0x000000d5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_214 0x000000d6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_215 0x000000d7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_216 0x000000d8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_217 0x000000d9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_218 0x000000da /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_219 0x000000db /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_220 0x000000dc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_221 0x000000dd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_222 0x000000de /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_223 0x000000df /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_224 0x000000e0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_225 0x000000e1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_226 0x000000e2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_227 0x000000e3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_228 0x000000e4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_229 0x000000e5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_230 0x000000e6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_231 0x000000e7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_232 0x000000e8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_233 0x000000e9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_234 0x000000ea /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_235 0x000000eb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_236 0x000000ec /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_237 0x000000ed /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_238 0x000000ee /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_239 0x000000ef /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_240 0x000000f0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_241 0x000000f1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_242 0x000000f2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_243 0x000000f3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_244 0x000000f4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_245 0x000000f5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_246 0x000000f6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_247 0x000000f7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_248 0x000000f8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_249 0x000000f9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_250 0x000000fa /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_251 0x000000fb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_252 0x000000fc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_GRP_253 0x000000fd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_55_8_GROUP 0x000000fe /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_STATIC_PATTERN_AA_8_GROUP 0x000000ff /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2 15:8 /* RWEVF */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_10 0x0000000a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_11 0x0000000b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_12 0x0000000c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_13 0x0000000d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_14 0x0000000e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_15 0x0000000f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_26 0x0000001a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_27 0x0000001b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_28 0x0000001c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_29 0x0000001d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_30 0x0000001e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_31 0x0000001f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_42 0x0000002a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_43 0x0000002b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_44 0x0000002c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_45 0x0000002d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_46 0x0000002e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_47 0x0000002f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_48 0x00000030 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_49 0x00000031 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_50 0x00000032 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_51 0x00000033 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_52 0x00000034 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_53 0x00000035 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_54 0x00000036 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_55 0x00000037 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_56 0x00000038 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_57 0x00000039 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_58 0x0000003a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_59 0x0000003b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_60 0x0000003c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_61 0x0000003d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_62 0x0000003e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_63 0x0000003f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_64 0x00000040 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_65 0x00000041 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_66 0x00000042 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_67 0x00000043 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_68 0x00000044 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_69 0x00000045 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_70 0x00000046 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_71 0x00000047 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_72 0x00000048 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_73 0x00000049 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_74 0x0000004a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_75 0x0000004b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_76 0x0000004c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_77 0x0000004d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_78 0x0000004e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_79 0x0000004f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_80 0x00000050 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_81 0x00000051 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_82 0x00000052 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_83 0x00000053 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_84 0x00000054 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_85 0x00000055 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_86 0x00000056 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_87 0x00000057 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_88 0x00000058 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_89 0x00000059 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_90 0x0000005a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_91 0x0000005b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_92 0x0000005c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_93 0x0000005d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_94 0x0000005e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_95 0x0000005f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_96 0x00000060 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_97 0x00000061 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_98 0x00000062 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_99 0x00000063 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_100 0x00000064 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_101 0x00000065 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_102 0x00000066 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_103 0x00000067 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_104 0x00000068 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_105 0x00000069 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_106 0x0000006a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_107 0x0000006b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_108 0x0000006c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_109 0x0000006d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_110 0x0000006e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_111 0x0000006f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_112 0x00000070 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_113 0x00000071 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_114 0x00000072 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_115 0x00000073 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_116 0x00000074 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_117 0x00000075 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_118 0x00000076 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_119 0x00000077 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_120 0x00000078 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_121 0x00000079 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_122 0x0000007a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_123 0x0000007b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_124 0x0000007c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_125 0x0000007d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_126 0x0000007e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_127 0x0000007f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_128 0x00000080 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_129 0x00000081 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_130 0x00000082 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_131 0x00000083 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_132 0x00000084 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_133 0x00000085 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_134 0x00000086 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_135 0x00000087 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_136 0x00000088 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_137 0x00000089 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_138 0x0000008a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_139 0x0000008b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_140 0x0000008c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_141 0x0000008d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_142 0x0000008e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_143 0x0000008f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_144 0x00000090 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_145 0x00000091 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_146 0x00000092 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_147 0x00000093 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_148 0x00000094 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_149 0x00000095 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_150 0x00000096 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_151 0x00000097 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_152 0x00000098 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_153 0x00000099 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_154 0x0000009a /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_155 0x0000009b /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_156 0x0000009c /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_157 0x0000009d /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_158 0x0000009e /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_159 0x0000009f /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_160 0x000000a0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_161 0x000000a1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_162 0x000000a2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_163 0x000000a3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_164 0x000000a4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_165 0x000000a5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_166 0x000000a6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_167 0x000000a7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_168 0x000000a8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_169 0x000000a9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_170 0x000000aa /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_171 0x000000ab /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_172 0x000000ac /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_173 0x000000ad /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_174 0x000000ae /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_175 0x000000af /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_176 0x000000b0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_177 0x000000b1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_178 0x000000b2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_179 0x000000b3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_180 0x000000b4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_181 0x000000b5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_182 0x000000b6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_183 0x000000b7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_184 0x000000b8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_185 0x000000b9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_186 0x000000ba /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_187 0x000000bb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_188 0x000000bc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_189 0x000000bd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_190 0x000000be /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_191 0x000000bf /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_192 0x000000c0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_193 0x000000c1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_194 0x000000c2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_195 0x000000c3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_196 0x000000c4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_197 0x000000c5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_198 0x000000c6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_199 0x000000c7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_200 0x000000c8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_201 0x000000c9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_202 0x000000ca /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_203 0x000000cb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_204 0x000000cc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_205 0x000000cd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_206 0x000000ce /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_207 0x000000cf /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_208 0x000000d0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_209 0x000000d1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_210 0x000000d2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_211 0x000000d3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_212 0x000000d4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_213 0x000000d5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_214 0x000000d6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_215 0x000000d7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_216 0x000000d8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_217 0x000000d9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_218 0x000000da /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_219 0x000000db /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_220 0x000000dc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_221 0x000000dd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_222 0x000000de /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_223 0x000000df /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_224 0x000000e0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_225 0x000000e1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_226 0x000000e2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_227 0x000000e3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_228 0x000000e4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_229 0x000000e5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_230 0x000000e6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_231 0x000000e7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_232 0x000000e8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_233 0x000000e9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_234 0x000000ea /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_235 0x000000eb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_236 0x000000ec /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_237 0x000000ed /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_238 0x000000ee /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_239 0x000000ef /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_240 0x000000f0 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_241 0x000000f1 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_242 0x000000f2 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_243 0x000000f3 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_244 0x000000f4 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_245 0x000000f5 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_246 0x000000f6 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_247 0x000000f7 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_248 0x000000f8 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_249 0x000000f9 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_250 0x000000fa /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_251 0x000000fb /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_252 0x000000fc /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_GRP_253 0x000000fd /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_55_8_GROUP 0x000000fe /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_STATIC_PATTERN_AA_8_GROUP 0x000000ff /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_PERF_SEL2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_PM_CTRL_XPG2ZLAT_LAT 30:30 /* RWEVF */ #define NV_PGPC_PRI_PROP_PM_CTRL_XPG2ZLAT_LAT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_XPG2ZLAT_LAT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_XPG2ZLAT_LAT_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_PROP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_PROP_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_LO 0x000004a4 /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_HI 0x000004a8 /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_LO 0x000004ac /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_HI 0x000004b0 /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_LO 0x000004b8 /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_HI 0x000004bc /* RWI4R */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO 0x000004c0 /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_LO_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI 0x000004c4 /* RWI4R */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V 31:0 /* RWIVF */ #define NV_PGPC_PRI_PROP_EZ_ZPASS_INTERVAL_ACCUM_HI_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_PROP_CG 0x00000500 /* RWE4R */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_PROP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_PROP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_PROP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_PROP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_PROP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_PROP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_PROP_CG1 0x00000504 /* RWE4R */ #define NV_PGPC_PRI_PROP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_PROP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_PROP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_CG1_SLCG 24:1 /* RWEVF */ #define NV_PGPC_PRI_PROP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_PROP_CG1_SLCG_DISABLED 0x00FFFFFF /* RWE-V */ #define NV_PGPC_PRI_PROP_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR 0x0000067F:0x00000600 /* RW--L */ #define NV_PGPC_PRI_FRSTR_DEBUG 0x00000600 /* RWI4R */ #define NV_PGPC_PRI_FRSTR_DEBUG_OPTIMIZE_4X4 0:0 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_OPTIMIZE_4X4_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_OPTIMIZE_4X4_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_OPTIMIZE_4X4_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_3EDGE_ALIASED 4:4 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_3EDGE_ALIASED_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_3EDGE_ALIASED_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_3EDGE_ALIASED_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_2EDGE_ALIASED 1:1 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_2EDGE_ALIASED_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_2EDGE_ALIASED_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_2EDGE_ALIASED_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_4EDGE_4X4 2:2 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_4EDGE_4X4_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_4EDGE_4X4_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PROC_4EDGE_4X4_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_POWER_FIXES 3:3 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_POWER_FIXES_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_POWER_FIXES_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_POWER_FIXES_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA 10:10 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_REDUCED_PRECISION_EDGE_DATA_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER2 11:11 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER2_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER2_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER2_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER3 12:12 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER3_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER3_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER3_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 5:5 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS 7:7 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_ZERO_LOWER_THREE_ZC_BITS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER8 8:8 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER8_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER8_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_DEBUG_PLACEHOLDER8_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG 9:9 /* RWIVF */ #define NV_PGPC_PRI_FRSTR_DEBUG_USE_INNER_COVG_AS_OUTER_COVG_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL 0x00000604 /* RWE4R */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRPa 0x0000000a /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRPb 0x0000000b /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRPc 0x0000000c /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_GRPd 0x0000000d /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x0000000e /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x0000000f /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG 0x00000608 /* RWE4R */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_FRSTR_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_FRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_FRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_FRSTR_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_FRSTR_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_FRSTR_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_FRSTR_CG1 0x0000060C /* RWE4R */ #define NV_PGPC_PRI_FRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGPC_PRI_FRSTR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_FRSTR_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_FRSTR_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP 0x000006FF:0x00000680 /* RW--L */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL 0x00000680 /* RWE4R */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRPA 0x0000000a /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRPB 0x0000000b /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRPC 0x0000000c /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_GRPD 0x0000000d /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x0000000e /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x0000000f /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG 0x00000684 /* RWI4R */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER0 0:0 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER0_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER0_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER0_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER1 1:1 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER1_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER1_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER1_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER2 2:2 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER2_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER2_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_PLACEHOLDER2_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_GFXP_DISABLE 3:3 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_GFXP_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE 4:4 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_BLKACTIVITY_DISABLE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE 5:5 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_FORCE_STIPPLE_FOR_PSAA_RATE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING 6:6 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_MODS_VPRS_BYPASS_FOR_PROP_TESTING_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 7:7 /* RWIVF */ #define NV_PGPC_PRI_WIDCLIP_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_WIDCLIP_CG 0x00000688 /* RWE4R */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WIDCLIP_CG1 0x0000068C /* RWE4R */ #define NV_PGPC_PRI_WIDCLIP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG1_SLCG 4:1 /* RWEVF */ #define NV_PGPC_PRI_WIDCLIP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WIDCLIP_CG1_SLCG_DISABLED 0x0000000F /* RWE-V */ #define NV_PGPC_PRI_WIDCLIP_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC 0x000007FF:0x00000700 /* RW--L */ #define NV_PGPC_PRI_TC_FLUSH 0x00000700 /* RWI4R */ #define NV_PGPC_PRI_TC_FLUSH_CRITERION 1:0 /* RWIVF */ #define NV_PGPC_PRI_TC_FLUSH_CRITERION_DISABLE 0x0 /* RW--V */ #define NV_PGPC_PRI_TC_FLUSH_CRITERION_END_OF_CBE 0x1 /* RW--V */ #define NV_PGPC_PRI_TC_FLUSH_CRITERION_TIMEOUT 0x2 /* RWI-V */ #define NV_PGPC_PRI_TC_TIMEOUT 0x00000704 /* RWI4R */ #define NV_PGPC_PRI_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGPC_PRI_TC_TIMEOUT_VALUE_INIT 0x00000080 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0 0x00000708 /* RWI4R */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE 8:0 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_COALESCE_BUFFER_SIZE_INIT 0x00 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_NUM_OF_TILES 14:9 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_NUM_OF_TILES_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS 15:15 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_DISABLE 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_FORCE_CONFLICT_DETECTION_TO_VPRS_ENABLE 0x1 /* RW--V */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_CBES_ACTIVE 26:16 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_LIMIT_CBES_ACTIVE_INIT 0x000 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE 27:27 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_DISABLE 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_FLUSH_ON_VPRS_CHANGE_ENABLE 0x1 /* RW--V */ #define NV_PGPC_PRI_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT 29:29 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_PSI_FORCE_FLUSH_ON_CONFLICT_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_BLKACTIVITY_DISABLE 30:30 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_BLKACTIVITY_DISABLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_TC_DEBUG0_BLKACTIVITY_DISABLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_TC_DEBUG0_BLKACTIVITY_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_RTAI_FLUSH 31:31 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG0_RTAI_FLUSH_ON_OVERRIDE 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG0_RTAI_FLUSH_ALWAYS 0x1 /* RW--V */ #define NV_PGPC_PRI_TC_DEBUG1 0x0000070c /* RWI4R */ #define NV_PGPC_PRI_TC_DEBUG1_LIMIT_TILES_INFLIGHT 10:0 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_LIMIT_TILES_INFLIGHT_INIT 0x000 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE11 11:11 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE11_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE12 12:12 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE12_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE13 13:13 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE13_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE14 14:14 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE14_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE15 15:15 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_SPARE15_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_LIMIT_TRANS_INFLIGHT 28:16 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_LIMIT_TRANS_INFLIGHT_INIT 0x000 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE 29:29 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_LOCAL_TIMEOUT_OVERRIDE_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1 30:30 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_PSI_LIMIT_TILES_MIN_1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS 31:31 /* RWIVF */ #define NV_PGPC_PRI_TC_DEBUG1_PSI_DO_NOT_SPLIT_QUADS_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_TC_TILE_SIZE 0x00000710 /* RWI4R */ #define NV_PGPC_PRI_TC_TILE_SIZE_MAX 1:0 /* RWIVF */ #define NV_PGPC_PRI_TC_TILE_SIZE_MAX_16X16 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_TC_TILE_SIZE_MAX_16X8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_TILE_SIZE_MAX_8X8 0x00000002 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL 0x00000714 /* RWE4R */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPA 0x0000000a /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPB 0x0000000b /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPC 0x0000000c /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPD 0x0000000d /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPE 0x0000000e /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_GRPF 0x0000000f /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x00000010 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x00000011 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_TC_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG 0x00000718 /* RWE4R */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_TC_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_TC_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_TC_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_TC_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_TC_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_TC_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_TC_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_TC_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_TC_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_TC_CG1 0x0000071C /* RWE4R */ #define NV_PGPC_PRI_TC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_TC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_TC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_TC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC_CG1_SLCG 9:1 /* RWEVF */ #define NV_PGPC_PRI_TC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_TC_CG1_SLCG_DISABLED 0x000001FF /* RWE-V */ #define NV_PGPC_PRI_TC_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB 0x000003FF:0x00000380 /* RW--L */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS 0x00000380 /* RWI4R */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SETUP 1:0 /* RWIVF */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SETUP_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SETUP_EVICT_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SETUP_EVICT_LAST 0x00000002 /* RWI-V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_WIDREQ 3:2 /* RWIVF */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_WIDREQ_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_WIDREQ_EVICT_NORMAL 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_WIDREQ_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_ZCULL 5:4 /* RWIVF */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_ZCULL_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_ZCULL_EVICT_NORMAL 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_ZCULL_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SWDX 7:6 /* RWIVF */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SWDX_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SWDX_EVICT_NORMAL 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_RASTERARB_LINE_CLASS_SWDX_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL 0x00000384 /* RWE4R */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRPa 0x0000000a /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRPb 0x0000000b /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRPc 0x0000000c /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_GRPd 0x0000000d /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x0000000e /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x0000000f /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_RASTERARB_CG2 0x00000388 /* RWE4R */ #define NV_PGPC_PRI_RASTERARB_CG2_SLCG 0:0 /* RWEVF */ #define NV_PGPC_PRI_RASTERARB_CG2_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_RASTERARB_CG2_SLCG_DISABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_RASTERARB_CG2_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP 0x0000087F:0x00000800 /* RW--L */ #define NV_PGPC_PRI_SETUP_DEBUG 0x00000800 /* RWI4R */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO 0:0 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_NAN_IS_ZERO_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO 1:1 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_POLY_OFFSET_ZERO_X_NAN_IS_ZERO_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET 2:2 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_DO_NOT_USE_ABS_Z_GAMUT_MAX_FOR_POFFSET_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_THRESHOLD 3:3 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_THRESHOLD_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_THRESHOLD_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_THRESHOLD_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_BLKACTIVITY_DISABLE 5:5 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_BLKACTIVITY_DISABLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_BLKACTIVITY_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_THRESHOLD 15:8 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_THRESHOLD_INIT 0x86 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES 16:16 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_COMPUTES_STIPPLE_PHASE_FOR_LINES_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT 17:17 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP_MS_POINT_BBOX_BLOAT_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX 18:18 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_TIGHTEN_ALIASED_TRI_BBOX_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE 19:19 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_USE_24_FRACTIONAL_BIT_STIPPLE_PHASE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE0 20:20 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE0_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE1 21:21 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE1_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY 25:25 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_CONSERVATIVE_RASTER_TIER1_ONLY_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE6 26:26 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SPARE6_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE 27:27 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SETUP2PE_EARLY_THROTTLE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK 28:28 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_ALIASED_LINE_BBOX_SHRINK_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_TRI_CORNER_CLIPPING 29:29 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_TRI_CORNER_CLIPPING_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_TRI_CORNER_CLIPPING_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_TRI_CORNER_CLIPPING_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_NEAR_FAR_CULLING 30:30 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_NEAR_FAR_CULLING_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_NEAR_FAR_CULLING_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_NEAR_FAR_CULLING_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK 31:31 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_SMOOTH_LINE_BBOX_SHRINK_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET 0x00000830 /* RWI4R */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT 27:0 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_AMOUNT_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16 28:28 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_Z_GAMUT_OFFSET_ZF32_AS_Z16_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2 0x00000808 /* RWI4R */ #define NV_PGPC_PRI_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY 0:0 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_ALIASED_LINE_BBOX_EXPANSION_LEGACY_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS 1:1 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LATE_Z_FOR_COLOR_CLEARS_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS 2:2 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER1_BEHAVIOR_FOR_LINES_AND_POINTS_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE 3:3 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_ENABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_DISABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_TIER4_LINE_BUG_CHANGE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH 4:4 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_LINE_LENGTH_ZERO_CULL_PATH_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE 5:5 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG2_FIX_NEGATIVE_ZERO_COMPARE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE6 6:6 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE6_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE7 7:7 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE7_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE8 8:8 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE8_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE9 9:9 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE9_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE10 10:10 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE10_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE11 11:11 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE11_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE12 12:12 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE12_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE13 13:13 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE13_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE14 14:14 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE14_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE15 15:15 /* RWIVF */ #define NV_PGPC_PRI_SETUP_DEBUG2_SPARE15_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_CG 0x00000828 /* RWE4R */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_SETUP_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_SETUP_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_SETUP_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_SETUP_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_SETUP_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SETUP_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SETUP_CG1 0x0000082C /* RWE4R */ #define NV_PGPC_PRI_SETUP_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGPC_PRI_SETUP_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_CG1_SLCG_DISABLED 0x0000FFFF /* RWE-V */ #define NV_PGPC_PRI_SETUP_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE 0x00000810 /* RWI4R */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12 27:0 /* RWIVF */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_ADDR_39_12_ALIGN_BITS 0x0000000c /* */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_VALID 31:31 /* RWIVF */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_VALID_FALSE 0 /* RWI-V */ #define NV_PGPC_PRI_SETUP_RM_ATTRIB_CB_BASE_VALID_TRUE 1 /* RW--V */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT0 0x00000814 /* RWE4R */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE 9:0 /* RWEVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT0_SWDX2SETUP_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE 26:16 /* RWEVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT0_TAG_LATENCY_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1 0x00000818 /* RWE4R */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_RRRAM_VALUE 9:0 /* RWEVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_RRRAM_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE 24:14 /* RWEVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_SETUP2PE_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE 31:25 /* RWEVF */ #define NV_PGPC_PRI_SETUP_DEBUG_LIMIT1_PRIM_PTR_MSB_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_PM_CTRL 0x0000081c /* RWE4R */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL 5:0 /* RWEVF */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPa 0x0000000a /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPb 0x0000000b /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPc 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPd 0x0000000d /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPe 0x0000000e /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_GRPf 0x0000000f /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early0 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early1 0x00000011 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early2 0x00000012 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early3 0x00000013 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early4 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early5 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_early6 0x0000002a /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late0 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late1 0x00000015 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late2 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late3 0x00000017 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late4 0x00000021 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late5 0x00000027 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_pe2setup_late6 0x0000002b /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early0 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early1 0x00000019 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early2 0x0000001a /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early3 0x0000001b /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early4 0x00000022 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early5 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_early6 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late0 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late1 0x0000001d /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late2 0x0000001e /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late3 0x0000001f /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late4 0x00000023 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late5 0x00000029 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_setup2pe_late6 0x0000002d /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_5_GROUP 0x00000025 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_STATIC_PATTERN_0A_5_GROUP 0x00000026 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_SETUP_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SETUP_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SETUP_HWW_ESR 0x00000824 /* RWE4R */ #define NV_PGPC_PRI_SETUP_HWW_ESR_INTR 0:0 /* R-EVF */ #define NV_PGPC_PRI_SETUP_HWW_ESR_INTR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_INTR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_LDCONST_OOB 1:1 /* R-EVF */ #define NV_PGPC_PRI_SETUP_HWW_ESR_LDCONST_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_LDCONST_OOB_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_POOLPAGE_INVALID 4:4 /* R-EVF */ #define NV_PGPC_PRI_SETUP_HWW_ESR_POOLPAGE_INVALID_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_POOLPAGE_INVALID_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGPC_PRI_SETUP_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGPC_PRI_SETUP_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_SETUP_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGPC_PRI_SETUP_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGPC_PRI_CRSTR 0x00000BFF:0x00000B00 /* RW--L */ #define NV_PGPC_PRI_CRSTR_DEBUG 0x00000B00 /* RWI4R */ #define NV_PGPC_PRI_CRSTR_DEBUG_SEARCH 0:0 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_SEARCH_DISABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_SEARCH_ENABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_SEARCH_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOXDISC 1:1 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOXDISC_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOXDISC_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOXDISC_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOX2X2OPT 2:2 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOX2X2OPT_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOX2X2OPT_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BBOX2X2OPT_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BLKACTIVITY_DISABLE 3:3 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_BLKACTIVITY_DISABLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_BLKACTIVITY_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL 4:4 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_LANA_CLOCKGATE_CONTROL_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 5:5 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 6:6 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_GFXP_SYNC_DISABLE 7:7 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_GFXP_SYNC_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_INNER_COVG 8:8 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_INNER_COVG_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_INNER_COVG_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_CRSTR_DEBUG_INNER_COVG_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS 9:9 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_POINTS_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES 10:10 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_LINES_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS 11:11 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INNER_CVG_FOR_TRIS_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION 12:12 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_FULLY_COVERED_OPTIMIZATION_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_VPRS_CACHE 13:13 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_VPRS_CACHE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES 14:14 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_SEARCH_UPDATES_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES 15:15 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_DISABLE_INDEPENDENT_ENGINES_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_DEBUG_SAVED 31:16 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_DEBUG_SAVED_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL 0x00000B04 /* RWE4R */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL 3:0 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRPA 0x0000000a /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRPB 0x0000000b /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRPC 0x0000000c /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_GRPD 0x0000000d /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_5_4_GROUP 0x0000000e /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_STATIC_PATTERN_A_4_GROUP 0x0000000f /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP(i) (0x00000b08+(i)*4) /* RWI4A */ #define NV_PGPC_PRI_CRSTR_GPC_MAP__SIZE_1 43 /* */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE0 4:0 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE1 9:5 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE1_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE2 14:10 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE2_INIT 0x00000002 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE3 19:15 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE3_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE4 24:20 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE4_INIT 0x00000004 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE5 29:25 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_GPC_MAP_TILE5_INIT 0x00000005 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_MAP_TABLE_CONFIG 0x00000BB8 /* RWI4R */ #define NV_PGPC_PRI_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET 7:0 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_MAP_TABLE_CONFIG_ROW_OFFSET_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES 15:8 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_MAP_TABLE_CONFIG_NUM_ENTRIES_INIT 0x1 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_CG 0x00000BBC /* RWE4R */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_CRSTR_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_CRSTR_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_CRSTR_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_CRSTR_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_CRSTR_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_CRSTR_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_CRSTR_CG1 0x00000BC0 /* RWE4R */ #define NV_PGPC_PRI_CRSTR_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGPC_PRI_CRSTR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_CRSTR_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_CRSTR_HEAVY_BUNDLE_ADDITIONS 0x00000BF0 /* RWI4R */ #define NV_PGPC_PRI_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGPC_PRI_CRSTR_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX 0x000008C0 /* RW-4R */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_ADDRESS 15:0 /* RWXVF */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT 20:16 /* RWXVF */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZNEAR3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR0 0x00000008 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR1 0x00000009 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR2 0x0000000A /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR3 0x0000000B /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR4 0x0000000C /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR5 0x0000000D /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR6 0x0000000E /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_ZFAR7 0x0000000F /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL0 0x00000010 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL1 0x00000011 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL2 0x00000012 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL3 0x00000013 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL4 0x00000014 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL5 0x00000015 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL6 0x00000016 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_SELECT_STENCIL7 0x00000017 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_WRITE 31:31 /* RWXVF */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_WRITE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_INDEX_WRITE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_DATA 0x000008C4 /* RW-4R */ #define NV_PGPC_PRI_ZCULL_ZCRAM_DATA_VALUE 31:0 /* RWXVF */ #define NV_PGPC_PRI_ZCULL_PM_CTRL 0x000008C8 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL 4:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRPA 0x0000000a /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRPB 0x0000000b /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_OCCLUDERS 0x0000000c /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP_AGG2_PARTIAL_FLUSH 0x0000000d /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP_ZSLVR 0x0000000e /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_GRP_4X2_COUNT 0x0000000f /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_15_6_GROUP 0x00000010 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_STATIC_PATTERN_2A_6_GROUP 0x00000011 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_PERF_SEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_PM_CTRL_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0 0x000008CC /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1 3:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_COARSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_ZCULLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_SCULLED 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_ZACCEPT 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_ZREJECT 0x00000004 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_DBCULLED 0x00000005 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_FCULLED 0x00000006 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_CULLED 0x00000007 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_ZFAIL_NO_CULL 0x00000008 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT1_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2 6:4 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_ZCULL_ENABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_SCULL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_DBCULL_ENABLE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_ZACCEPT_ENABLE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_ZSAMPLED_OUTSIDE_PRIM 0x00000004 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_8X8_INSIDE 0x00000005 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_REGION_VALID 0x00000006 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3 9:8 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3_PIPE0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3_PIPE1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3_PIPE2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3_PIPE3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_0_PM_SELECT3_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1 0x000008D0 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS 31:31 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_NF_PASS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS 29:29 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_DB_PASS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS 27:27 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_SEVEN_EIGHTS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL 26:26 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZFAIL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS 25:25 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_RESULT_ZPASS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_CULL 24:24 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_CULL 23:23 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_S_CULL 22:22 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_S_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_S_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_DB_CULL 21:21 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_DB_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_DB_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_NF_CULL 20:20 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_NF_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_NF_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE 19:19 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_CACHE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE 18:18 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_ZNEAR_MERGE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER 17:17 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_ONE_QUARTER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER 16:16 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISCARD_THRESH_THREE_QUARTER_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_READ_CACHE 15:15 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_READ_CACHE_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_READ_CACHE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM 14:14 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_FORCE_Z_PER_PRIM_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL 13:13 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STICKY_SCULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS 12:12 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_STENCIL_SUBSETS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL 11:11 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCLUSION_QUERY_ACCEL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE 10:10 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_CULL_TO_NEAR_SIDE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP 9:9 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_PER_PRIM_CLAMP_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ALWAYS_SYNCED 8:8 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ALWAYS_SYNCED_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ALWAYS_SYNCED_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256 7:7 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_ZPASS_COUNT_AT_256_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL 6:6 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NF_CULL_IF_Z_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_PACKET_KILL 5:5 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_PACKET_KILL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NO_PACKET_KILL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK 4:4 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_NON_BLOCKING_BLOCK_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER 3:3 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_Z_PER_SLIVER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL 2:2 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_REVERSED_ZFUNC_CULL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP 1:1 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_0 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_DISABLE_OCCL_OVERLAP_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR 0:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_1_INVALIDATE_UPON_WRONG_DIR_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2 0x000008D4 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO 0:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_ZNEAR_NON_MONO_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION 1:1 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_0 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_SAVE_RESTORE_WITH_NO_ALLOCATION_PERMISSION_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z 3:3 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_FORCE_Z_PER_TILE_SHADER_Z_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE 4:4 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_GEN_ROP_STATE_BUNDLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE 5:5 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_GEN_SYNC_BUNDLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER 6:6 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_ZFAIL_NEARER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP 7:7 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_DISABLE_CONSERVATIVE_Z_CLAMP_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER 8:8 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_MORE_CONSERVATIVE_Z_PER_SLIVER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL 9:9 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_LANA_CLOCKGATE_CONTROL_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ 16:16 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_UPDATE_WRITE_WITHOUT_READ_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_17 17:17 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_17_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_18 18:18 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_18_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_19 19:19 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_19_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_20 20:20 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_20_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_21 21:21 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_21_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_22 22:22 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_22_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_23 23:23 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_23_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_24 24:24 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_24_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_25 25:25 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_25_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_26 26:26 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_26_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_27 27:27 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_27_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_28 28:28 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_28_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_29 29:29 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_29_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_30 30:30 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_30_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_31 31:31 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_2_SPARE_31_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CTX1 0x000008D8 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE 2:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_PROC_CUR_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES 3:3 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_BETWEEN_PRIMITIVES_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE 5:4 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_NON_BLOCKING_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN 6:6 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_STENCIL_WRITTEN_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX1_PRI_ZCULL_PROC_SYNC_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX5 0x000008E0 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT 23:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX5_PRI_ZCULL_UPDATE_SYNC_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE 24:24 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX5_PRI_ZCULL_SYNC_SINCE_LAST_TILE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX6 0x000008E8 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT 31:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX6_PRI_ZCULL_ZPASS_PIXEL_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX7 0x000008EC /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8 31:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX7_PRI_ZCULL_TOTAL_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX8 0x000008F0 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2 31:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX8_PRI_ZCULL_ZFAIL_4X2_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX9 0x000008F4 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8 31:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX9_PRI_ZCULL_ZPASS_8X8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX10 0x000008F8 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4 31:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX10_PRI_ZCULL_STNCL_4X4_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG 0x000008FC /* RWI4R */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED 0:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_FULLY_COVERED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED 1:1 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZPASS_CULL_AFTER_PARTIALLY_COVERED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES 2:2 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZFAIL_REPORT_NOT_EQUAL_TOTAL_COARSE_TILES_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZF32_AS_Z16 3:3 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_ZF32_AS_Z16_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE 4:4 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_PROC_TO_UPDATE_OCCLUDERS_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE 5:5 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_TWO_Z_1XAA_UPDATES_DISABLE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE 6:6 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_BLKACTIVITY_DISABLE_INIT 1 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0 7:7 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_0_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1 8:8 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_DISABLE 0 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_ENABLE 1 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_HEAVY_BUNDLE_ADDITIONS_EN_1_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_GFXP_DISABLE 9:9 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_GFXP_DISABLE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_12 12:12 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_12_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_13 13:13 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_13_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_14 14:14 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_14_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_15 15:15 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_SPARE_15_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD 20:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_OCCL_OVERLAP_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT 24:24 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_IGNORE_INSUFF_BANKS_RAMFORMAT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM 25:25 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_USE_Z_OUTSIDE_PRIM_INIT 0x0000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET 29:26 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_CTX_DEBUG_Z_OUTSIDE_PRIM_OFFSET_INIT 0x0000008 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR 0x00000900 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB 0:0 /* R-EVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_SAVE_RESTORE_ADDR_OOB_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_RESET_INIT 0x0 /* -WE-V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_EN_ENABLE 0x1 /* RW--V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_EN_INIT 0x1 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_0 0x00000904 /* R--4R */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_0_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_1 0x00000908 /* R--4R */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_1_ADDRESS_HIGH 7:0 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_1_LIMIT_ADDRESS_HIGH 15:8 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_2 0x0000090C /* R--4R */ #define NV_PGPC_PRI_ZCULL_HWW_ESR_INFO_2_LIMIT_ADDRESS_LOW 31:0 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_FS 0x00000910 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_FS_NUM_SMS 8:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_FS_NUM_SMS_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_FS_NUM_ACTIVE_BANKS 19:16 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_FS_NUM_ACTIVE_BANKS_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_FS_NUM_BANKS 31:28 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_RAM_ADDR 0x00000914 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC 3:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_RAM_ADDR_TILES_PER_HYPERTILE_ROW_PER_GPC_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_RAM_ADDR_ROW_OFFSET 11:8 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_RAM_ADDR_ROW_OFFSET_INIT 0x00000003 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_NUM_RCP 0x00000918 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_SM_NUM_RCP_CONSERVATIVE 23:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_NUM_RCP_CONSERVATIVE__MAX 0x800000 /* R---V */ #define NV_PGPC_PRI_ZCULL_SM_NUM_RCP_CONSERVATIVE_INIT 0x00800000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_REGION_PERMISSION 0x0000091C /* RWI4R */ #define NV_PGPC_PRI_ZCULL_REGION_PERMISSION_ALLOCATION_MASK 7:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_REGION_PERMISSION_ALLOCATION_MASK_INIT 0x000000ff /* RWI-V */ #define NV_PGPC_PRI_ZCULL_REGION_PERMISSION_MASK 23:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_REGION_PERMISSION_MASK_INIT 0x000000ff /* RWI-V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE 0x00000920 /* R--4R */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_NUM_ALIQUOTS 15:0 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS 31:16 /* R-XVF */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16X2_4X4 0x0001 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X4 0x0001 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X16_4X4 0x0002 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_4X4 0x0002 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X2 0x0004 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X2 0x0004 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_2X4 0x0008 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_2X4 0x0008 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X8_4X4 0x0010 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_4X2 0x0020 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_8X8_2X4 0x0040 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_16X16_4X8 0x0080 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_2X2 0x0100 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_4X2 0x0200 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_16X8_2X4 0x0400 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_ZS_8X8_2X2 0x0800 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_Z_4X8_1X1 0x1000 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE0 0x2000 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE1 0x4000 /* R---V */ #define NV_PGPC_PRI_ZCULL_TOTAL_RAM_SIZE_AVAILABLE_RAM_FORMATS_SPARE2 0x8000 /* R---V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_OFFSET 0x00000924 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_OFFSET_AMOUNT 15:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_OFFSET_AMOUNT_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1 0x00000928 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER 7:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MIN_ZCENTER_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER 15:8 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_ZCENTER_INIT 0xff /* RWI-V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE 23:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_1_MAX_CLIPPED_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_0 0x0000092C /* RWI4R */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE 7:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_0_MIN_SLOPE_INIT 0x00 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE 15:8 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_Z_GAMUT_THRESHOLD_0_MAX_SLOPE_INIT 0xff /* RWI-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL 0x00000930 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SAVE 0:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SAVE_RUN 0x00000001 /* -W--T */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_RESTORE 1:1 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_RESTORE_RUN 0x00000001 /* -W--T */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUB 2:2 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUB_RUN 0x00000001 /* -W--T */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED 3:3 /* R-EVF */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_CTRL_SCRUBBED_TRUE 0x00000001 /* -W--T */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_ADDR 0x00000934 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_ADDR_VALUE 31:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_ADDR_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_SIZE 0x00000938 /* R--4R */ #define NV_PGPC_PRI_ZCULL_DIRECT_CTXSW_SIZE_VALUE 31:0 /* R--VF */ #define NV_PGPC_PRI_ZCULL_HEAVY_BUNDLE_ADDITIONS 0x0000093c /* RWI4R */ #define NV_PGPC_PRI_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0 15:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_0_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1 31:16 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_HEAVY_BUNDLE_ADDITIONS_ADDRESS_1_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_LIMIT0 0x00000940 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE 9:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_LIMIT0_CRSTR2ZCULL_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE 19:10 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_DEBUG_LIMIT0_WIDREQ2ZCULL_VALUE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SYNC 0x00000944 /* RWI4R */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE 0:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_PENDING_WRITES_BUNDLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE 1:1 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_REPORT_SEMAPHORE_D_BUNDLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE 2:2 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_BACK_END_COPY_E_BUNDLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE 3:3 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_PM_TRIGGER_END_BUNDLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE 4:4 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_SYNC_ON_FLUSH_AND_INVALIDATE_ROP_MINI_CACHE_BUNDLE__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG 0x00000970 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_ZCULL_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_ZCULL_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_ZCULL_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_ZCULL_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_ZCULL_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_ZCULL_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_ZCULL_CG1 0x00000974 /* RWE4R */ #define NV_PGPC_PRI_ZCULL_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG1_SLCG 16:1 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_CG1_SLCG_DISABLED 0x0000FFFF /* RWE-V */ #define NV_PGPC_PRI_ZCULL_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP(i) (0x00000980 +(i)*4) /* RWE4A */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP__SIZE_1 32 /* */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0 2:0 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_0_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1 6:4 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_1_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2 10:8 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_2_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3 14:12 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_3_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4 18:16 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_4_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5 22:20 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_5_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6 26:24 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_6_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7 30:28 /* RWEVF */ #define NV_PGPC_PRI_ZCULL_SM_IN_GPC_NUMBER_MAP_TILE_7_INIT 0x00000007 /* RWE-V */ #define NV_PGPC_PRI_ZCULL_ZCREGION(i) (0x00000A00+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCREGION__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCREGION_FAR_Z 7:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCREGION_FAR_Z_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT 15:12 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X2 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_Z_2X4 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_2X4 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_HIGH_RES_Z 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_16X16X2_4X4 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_LOW_RES_ZS 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_ZS_16X16_4X4 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_16X8_4X4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_4X2 0x00000005 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_8X8_2X4 0x00000006 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_16X16_4X8 0x00000007 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_2X2 0x00000008 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_4X2 0x00000009 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_ZS_16X8_2X4 0x0000000a /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_ZS_8X8_2X2 0x0000000b /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_4X8_1X1 0x0000000c /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_Z_NONE 0x0000000f /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCREGION_RAMFORMAT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE(i) (0x00000A04+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCSIZE__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_HEIGHT 12:1 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_HEIGHT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_HEIGHT__MULTIPLE 0x20 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_HEIGHT_SUBREGION__MULTIPLE 0x40 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_HEIGHT__MAX 0x4000 /* */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_WIDTH 28:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_WIDTH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_WIDTH__MULTIPLE 0x10 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_WIDTH_SUBREGION__MULTIPLE 0x10 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCSIZE_WIDTH__MAX 0x4000 /* */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET(i) (0x00000A08+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_Y 11:0 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_Y__MULTIPLE 0x10 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_X 27:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCOFFSET_X__MULTIPLE 0x10 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX(i) (0x00000A0C+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX_OFFSET 10:0 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX_SIZE 27:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCRT_ARRAY_INDEX_SIZE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTART(i) (0x00000A10+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCSTART__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCSTART_ADDR 15:0 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSTART_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTART_ADDR__MULTIPLE 0x1 /* R---V */ #define NV_PGPC_PRI_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSTART_NORMALIZED_SIZE_PER_LAYER_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE(i) (0x00000A14+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE_TOTAL 15:0 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE_TOTAL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE_PER_LAYER 31:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCRAM_SIZE_PER_LAYER_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS(i) (0x00000A18+(i)*32) /* RWI4A */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS__SIZE_1 8 /* */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_VALID 0:0 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_VALID_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_VALID_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_VALID_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZDIR 1:1 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZDIR_LESS 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZDIR_GREATER 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZDIR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT 3:2 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT_MSB 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT_FP 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT_ZTRICK 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT_ZF32_1 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_ZFORMAT_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_FORCE_MATCH 4:4 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_FORCE_MATCH_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_FORCE_MATCH_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_FORCE_MATCH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SUBREGION_MODE 5:5 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SUBREGION_MODE_OFF 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SUBREGION_MODE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SUBREGION_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC 14:12 /* RWIVF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_NEVER 0x00000000 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_LESS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_EQUAL 0x00000002 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_LEQUAL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_GREATER 0x00000004 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_NOTEQUAL 0x00000005 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_GEQUAL 0x00000006 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_ALWAYS 0x00000007 /* RW--V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SFUNC_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SREF 23:16 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SREF_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SMASK 31:24 /* RWIUF */ #define NV_PGPC_PRI_ZCULL_ZCSTATUS_SMASK_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD 0x00000C7F:0x00000C00 /* RW--L */ #define NV_PGPC_PRI_GPM_PD_STATUS 0x00000C00 /* R--4R */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_ALPHA 0:0 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_ALPHA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_ALPHA_MIXED 0x1 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_BETA 4:4 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_BETA_UNPARTITIONED 0x0 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_MODE_BETA_MIXED 0x1 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM 10:8 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM_WTB 0x0 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM_SB 0x1 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM_WFP 0x2 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM_WFC 0x3 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_FSM_SWTB 0x4 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_ALPHA_PRIMID_EN 12:12 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM 18:16 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM_READY 0x0 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM_SENDING 0x1 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM_COMPLEX 0x2 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM_NUM_THREADS 0x3 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FSM_SWTB 0x4 /* R---V */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_FORWARD_BETA 20:20 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS_BETA_SPM_ID 26:24 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_STATUS2 0x00000C08 /* R--4R */ #define NV_PGPC_PRI_GPM_PD_STATUS2_BATCH_INTERLOCK_COUNT 13:0 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_PM 0x00000C04 /* RWE4R */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT 6:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP10 0x0000000A /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP11 0x0000000B /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP12 0x0000000C /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP13 0x0000000D /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP14 0x0000000E /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP15 0x0000000F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP26 0x0000001A /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP27 0x0000001B /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP28 0x0000001C /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP29 0x0000001D /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP30 0x0000001E /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP31 0x0000001F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP42 0x0000002A /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP43 0x0000002B /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP44 0x0000002C /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP45 0x0000002D /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP46 0x0000002E /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP47 0x0000002F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP48 0x00000030 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP49 0x00000031 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP50 0x00000032 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP51 0x00000033 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP52 0x00000034 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP53 0x00000035 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP54 0x00000036 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP55 0x00000037 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP56 0x00000038 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP57 0x00000039 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP58 0x0000003A /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP59 0x0000003B /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP60 0x0000003C /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP61 0x0000003D /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP62 0x0000003E /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP63 0x0000003F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP64 0x00000040 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP65 0x00000041 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP66 0x00000042 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP67 0x00000043 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP68 0x00000044 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP69 0x00000045 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP70 0x00000046 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x0000007D /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_STATIC_PATTERN_AA_8_GROUP 0x0000007E /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_STATIC_PATTERN_55_8_GROUP 0x0000007F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_SELECT_GRP_MAX 0x0000007F /* RW--V */ #define NV_PGPC_PRI_GPM_PD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_PM_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_PM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_SM_ID(i) (0x00000C10+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_GPM_PD_SM_ID__SIZE_1 8 /* */ #define NV_PGPC_PRI_GPM_PD_SM_ID_ID 7:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_SM_ID_ID_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_PES_TPC_ID_MASK(i) (0x00000C30+(i)*4) /* R--4A */ #define NV_PGPC_PRI_GPM_PD_PES_TPC_ID_MASK__SIZE_1 3 /* */ #define NV_PGPC_PRI_GPM_PD_PES_TPC_ID_MASK_MASK 8-1:0 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_LIVE_PHYSICAL_PES 0x00000C50 /* R--4R */ #define NV_PGPC_PRI_GPM_PD_LIVE_PHYSICAL_PES_MASK 3:0 /* R--VF */ #define NV_PGPC_PRI_GPM_PD_CONFIG 0x00000C6C /* RWI4R */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB 3:2 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB_AUTO 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB_ROUND_ROBIN 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB_ALPHA 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB_BETA 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_GPMPD2PEL_ARB_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE 8:4 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_FULLSIZE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_PD2GPM_SLICE_REDUCE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION 11:11 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_NO_ACTION 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_EXCLUDE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_LOAD_BALANCE_LAST_TPC_SELECTION_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM 13:12 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_LOAD_BALANCED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_ROUND_ROBIN_PES 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_TPC_SELECTION_ALGORITHM_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION 15:15 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_HONOR_PD_DISTRIBUTION_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL 17:16 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_AUTO 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_OFF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_ON 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_ROUND_ROBIN_PES_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL 20:18 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_XTRA_SPACE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_SPACE_ONLY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_ON_DRAIN_AND_SPACE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_BLOCK_UNTIL_DRAINS_ACKED 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_NO_BLOCK 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_SCG_DRAIN_SPILL_PROTOCOL_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK 22:22 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_STRICT_ALPHA_BETA_INTERLOCK_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INTERLOCK 23:23 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INTERLOCK_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INTERLOCK_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INTERLOCK_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION 24:24 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_BLOCK_ALPHA_WORK_IN_UNPARTITIONED_TO_ALPHA_TRANSITION_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH 25:25 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_RTV_PREFETCH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 26:26 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CONFIG_RESERVED 31:27 /* RWIVF */ #define NV_PGPC_PRI_GPM_PD_CONFIG_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_PD_CG 0x00000C70 /* RWE4R */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GPM_PD_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GPM_PD_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GPM_PD_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GPM_PD_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_PD_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_PD_CG1 0x00000C74 /* RWE4R */ #define NV_PGPC_PRI_GPM_PD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGPC_PRI_GPM_PD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_PD_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PGPC_PRI_GPM_PD_CG1_SLCG__PROD 0x7FFFFFC0 /* RW--V */ #define NV_PGPC_PRI_GPM_SD 0x00000CFF:0x00000C80 /* RW--L */ #define NV_PGPC_PRI_GPM_SD_CONFIG 0x00000C80 /* RWI4R */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_3D 0:0 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_3D_LOAD_BASED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_3D_ROUND_ROBIN 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_3D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_2D 1:1 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_2D_LOAD_BASED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_2D_ROUND_ROBIN 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_2D_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED0 2:2 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH 3:3 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DISABLE_INSTRUCTION_PREFETCH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DETERMINISTIC_DIST 5:5 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DETERMINISTIC_DIST_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DETERMINISTIC_DIST_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DETERMINISTIC_DIST_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED1 6:6 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_FORCE_TICKET_ZERO 7:7 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_FORCE_TICKET_ZERO_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_FORCE_TICKET_ZERO_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_FORCE_TICKET_ZERO_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC 13:13 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_PROP2X_ALLOW_SAME_TPC_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED2 15:14 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED2_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_THRESHOLD_3D 21:16 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_THRESHOLD_3D_INIT 0x00000010 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED3 23:22 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED3_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_THRESHOLD_2D 29:24 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DIST_THRESHOLD_2D_INIT 0x00000010 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE 30:30 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_ENABLED 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_DRAIN_GFX_TPC_TWO_PHASE_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED4 31:31 /* RWIVF */ #define NV_PGPC_PRI_GPM_SD_CONFIG_RESERVED4_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_SD_STATUS 0x00000C84 /* R--4R */ #define NV_PGPC_PRI_GPM_SD_STATUS_LOAD 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_PM 0x00000C88 /* RWE4R */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP10 0x0000000A /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP11 0x0000000B /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP12 0x0000000C /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP13 0x0000000D /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP14 0x0000000E /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP15 0x0000000F /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP26 0x0000001A /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP27 0x0000001B /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP28 0x0000001C /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP29 0x0000001D /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP30 0x0000001E /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP31 0x0000001F /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP42 0x0000002A /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP43 0x0000002B /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP44 0x0000002C /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP45 0x0000002D /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP46 0x0000002E /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP47 0x0000002F /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP48 0x00000030 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP49 0x00000031 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP50 0x00000032 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP51 0x00000033 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP52 0x00000034 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP53 0x00000035 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP54 0x00000036 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP55 0x00000037 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP56 0x00000038 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP57 0x00000039 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP58 0x0000003A /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP59 0x0000003B /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_GRP60 0x0000003C /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x0000003D /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_STATIC_PATTERN_2A_6_GROUP 0x0000003E /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_STATIC_PATTERN_15_6_GROUP 0x0000003F /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_SELECT_MAX 0x0000003F /* RW--V */ #define NV_PGPC_PRI_GPM_SD_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_PM_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_PM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_STATUS_COLL 0x00000C90 /* R--4R */ #define NV_PGPC_PRI_GPM_SD_STATUS_COLL_COLL 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_DIST 0x00000C94 /* R--4R */ #define NV_PGPC_PRI_GPM_SD_STATUS_DIST_DIST 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_DIST_SOF 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_IN 0x00000C98 /* R--4R */ #define NV_PGPC_PRI_GPM_SD_STATUS_IN_COLL 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_IN_DIST 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_IN_PROP2GPM_SUBTL 14:12 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_IN_GPMPD2GPMSD_COMPUTE 18:16 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT 0x00000C9C /* R--4R */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT_GPM2GCC_PIX 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT_GPM2PROP_SUBTL 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT0 10:8 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT_GPM2PROP_PIXOUT1 14:12 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_OUT_GPM2MPC_PIX 22:20 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_TPC(i) (0x00000CA0+(i)*4) /* R--4A */ #define NV_PGPC_PRI_GPM_SD_STATUS_TPC__SIZE_1 6 /* */ #define NV_PGPC_PRI_GPM_SD_STATUS_TPC_MPC2GPM_SUBTL 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_STATUS_TPC_SMM2GPM_PIXOUT 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_SD_CG 0x00000CF0 /* RWE4R */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GPM_SD_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GPM_SD_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GPM_SD_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GPM_SD_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_SD_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_SD_CG1 0x00000CF4 /* RWE4R */ #define NV_PGPC_PRI_GPM_SD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGPC_PRI_GPM_SD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_SD_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PGPC_PRI_GPM_SD_CG1_SLCG__PROD 0x7FFFFFF8 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT 0x00000D7F:0x00000D00 /* RW--L */ #define NV_PGPC_PRI_GPM_RPT_PM 0x00000D00 /* RWE4R */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT 4:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP10 0x0000000A /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP11 0x0000000B /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP12 0x0000000C /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP13 0x0000000D /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP14 0x0000000E /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP15 0x0000000F /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP26 0x0000001A /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP27 0x0000001B /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_GRP28 0x0000001C /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x0000001D /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x0000001E /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x0000001F /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_SELECT_MAX 0x0000001F /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_PM_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_PM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS 0x00000D04 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_ALPHA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS 0x00000D08 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P0 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P1 6:4 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P2 10:8 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P3 14:12 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P4 18:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P5 22:20 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P6 26:24 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_BETA_WRITE_POINTERS_P7 30:28 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_CONFIG 0x00000D0C /* RWI4R */ #define NV_PGPC_PRI_GPM_RPT_CONFIG_RESERVED 31:28 /* RWIVF */ #define NV_PGPC_PRI_GPM_RPT_CONFIG_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_0 0x00000D10 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_0_S0 15:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_0_S1 31:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_1 0x00000D14 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_1_S2 15:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_1_S3 31:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_2 0x00000D18 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_2_S4 15:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_2_S5 31:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_3 0x00000D1C /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_3_S6 15:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_SCOREBOARD_3_S7 31:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_STATUS 0x00000D20 /* R--4R */ #define NV_PGPC_PRI_GPM_RPT_STATUS_READ_POINTER 2:0 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_STATUS_FULL_FLAGS 23:16 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_STATUS_EMPTY_FLAGS 31:24 /* R--VF */ #define NV_PGPC_PRI_GPM_RPT_CG 0x00000D70 /* RWE4R */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GPM_RPT_CG1 0x00000D74 /* RWE4R */ #define NV_PGPC_PRI_GPM_RPT_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGPC_PRI_GPM_RPT_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GPM_RPT_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PGPC_PRI_GPM_RPT_CG1_SLCG__PROD 0x7FFFFFF0 /* RW--V */ #define NV_PGPC_PRI_WDXPS 0x00000FFF:0x00000F00 /* RW--L */ #define NV_PGPC_PRI_WDXPS_CONFIG 0x00000F00 /* RWI4R */ #define NV_PGPC_PRI_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16 4:0 /* RWIVF */ #define NV_PGPC_PRI_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WDXPS_CONFIG_ALPHA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16 9:5 /* RWIVF */ #define NV_PGPC_PRI_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WDXPS_CONFIG_BETA_NEXTSM_REDUCE_DIV16_FULLSIZE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE 10:10 /* RWIVF */ #define NV_PGPC_PRI_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CONFIG_TWO_PRIM_XBAR_MESSAGE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CONFIG_RESERVED 15:11 /* RWIVF */ #define NV_PGPC_PRI_WDXPS_CONFIG_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_WDXPS_PM 0x00000F08 /* RWE4R */ #define NV_PGPC_PRI_WDXPS_PM_SELECT 6:0 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP10 0x0000000a /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP11 0x0000000b /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP12 0x0000000c /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP13 0x0000000d /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP14 0x0000000e /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP15 0x0000000f /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP26 0x0000001a /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP27 0x0000001b /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP28 0x0000001c /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP29 0x0000001d /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP30 0x0000001e /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP31 0x0000001f /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP42 0x0000002a /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP43 0x0000002b /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP44 0x0000002c /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP45 0x0000002d /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP46 0x0000002e /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP47 0x0000002f /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP48 0x00000030 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP49 0x00000031 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP50 0x00000032 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP51 0x00000033 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP52 0x00000034 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP53 0x00000035 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP54 0x00000036 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP55 0x00000037 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP56 0x00000038 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP57 0x00000039 /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP58 0x0000003a /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP59 0x0000003b /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_GRP60 0x0000003c /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x0000003d /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_STATIC_PATTERN_2A_7_GROUP 0x0000003e /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_STATIC_PATTERN_55_7_GROUP 0x0000003f /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_SELECT_MAX 0x0000003f /* RW--V */ #define NV_PGPC_PRI_WDXPS_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_PM_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_PM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG 0x00000F0C /* RWE4R */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_WDXPS_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_WDXPS_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_WDXPS_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_WDXPS_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_WDXPS_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_WDXPS_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_WDXPS_CG1 0x00000F10 /* RWE4R */ #define NV_PGPC_PRI_WDXPS_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGPC_PRI_WDXPS_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_WDXPS_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PGPC_PRI_WDXPS_CG1_SLCG__PROD 0x7FFFFFF0 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG 0x00000000 /* RWI4R */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN 1:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN_ENABLED 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN_Z_ONLY 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN_C_ONLY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZBC_EN_INIT 0x00000003 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE 2:2 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_NOUPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT 3:3 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_IGNORE_PXCNT_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ 4:4 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_EARLYZ_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RUN_DS_NOW 6:6 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RUN_DS_NOW_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RUN_DS_NOW_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZONLY 7:7 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZONLY_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZONLY_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ZONLY_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_STENCIL_KEEP 9:9 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_STENCIL_KEEP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_STENCIL_KEEP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_STENCIL_KEEP_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON 11:11 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_ROP_FORCE_BC_ON_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON 12:12 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_PROP_FORCE_BC_ON_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON 13:13 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_DS_RSTR_FORCE_BC_ON_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RTL_KNOBS 17:14 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RTL_KNOBS_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_RTL_KNOBS_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_PROP 18:18 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_PROP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_PROP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_PROP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_ROP 19:19 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_ROP_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_ROP_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_ROP_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_RSTR 20:20 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_RSTR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_RSTR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_BYPASS_RSTR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR 24:24 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_COLOR_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH 25:25 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_DEPTH_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL 26:26 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ALLOW_FASTCLEAR_STENCIL_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY 29:29 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_ROP_ALWAYS_DIRTY_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_SP_SWIZZLE 31:31 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_SP_SWIZZLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_SP_SWIZZLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_DEBUG_SP_SWIZZLE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG 0x00000004 /* RWI4R */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND 23:23 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_USE_DS_CT_SEL_DL_SRC_BLND_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE 24:24 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_USE_CT_SEL_PITCH_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE 25:25 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_DS_PROPAGATE_BDL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0 26:26 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_X_CHANNEL_ONLY_MATCH_0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC 31:27 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG_EXTRA_PROPAGATION_CYC_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2 0x00000008 /* RWI4R */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR 15:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_DS_PROPAGATE_BDL_ADDR_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN 16:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_STENCIL_ZBC_EN_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_SPARE 31:17 /* RWIVF */ #define NV_PGPC_PRI_SWDX_DSS_ROP_DEBUG2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_R(i) (0x00000010+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_R__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_R_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_R_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_G(i) (0x0000004c+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_G__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_G_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_G_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_B(i) (0x00000088+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_B__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_B_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_B_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_A(i) (0x000000c4+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_A__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_A_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_COLOR_A_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT 0x00000100 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01 6:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_01_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02 13:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_02_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03 20:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_03_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04 27:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_01_TO_04_FORMAT_ENTRY_04_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT 0x00000104 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05 6:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_05_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06 13:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_06_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07 20:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_07_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08 27:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_05_TO_08_FORMAT_ENTRY_08_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT 0x00000108 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09 6:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_09_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10 13:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_10_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11 20:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_11_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12 27:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_09_TO_12_FORMAT_ENTRY_12_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT 0x0000010c /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13 6:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_13_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14 13:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_14_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15 20:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_ZERO 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_UNORM_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF32_GF32_BF32_AF32 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_R16_G16_B16_A16 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RN16_GN16_BN16_AN16 0x0000000c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RS16_GS16_BS16_AS16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RU16_GU16_BU16_AU16 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_RF16_GF16_BF16_AF16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8R8G8B8 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8RL8GL8BL8 0x0000001c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2B10G10R10 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU2BU10GU10RU10 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8B8G8R8 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A8BL8GL8RL8 0x0000002c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AN8BN8GN8RN8 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AS8BS8GS8RS8 0x00000034 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_AU8BU8GU8RU8 0x00000038 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_A2R10G10B10 0x0000003c /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_BF10GF11RF11 0x00000040 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_C_13_TO_15_FORMAT_ENTRY_15_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z(i) (0x00000110+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT 0x0000014c /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_01_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_02_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_03_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_01_TO_04_FORMAT_ENTRY_04_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT 0x00000150 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_05_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_06_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_07_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_05_TO_08_FORMAT_ENTRY_08_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT 0x00000154 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_09_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_10_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_11_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_09_TO_12_FORMAT_ENTRY_12_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT 0x00000158 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_13_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_14_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_FP32 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_Z_13_TO_15_FORMAT_ENTRY_15_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S(i) (0x0000015c+(i)*4) /* RWE4A */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S__SIZE_1 15 /* */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_VAL 7:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_VAL__INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT 0x00000198 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_01_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_02_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_03_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_01_TO_04_FORMAT_ENTRY_04_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT 0x0000019c /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_05_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_06_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_07_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_05_TO_08_FORMAT_ENTRY_08_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT 0x000001a0 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_09_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_10_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_11_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12 21:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_09_TO_12_FORMAT_ENTRY_12_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT 0x000001a4 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_13_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14 7:7 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_14_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_U8 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_DSS_ZBC_S_13_TO_15_FORMAT_ENTRY_15_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CONFIG 0x00000E00 /* RWI4R */ #define NV_PGPC_PRI_SWDX_CONFIG_TILED_CACHING 1:1 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_TILED_CACHING_ENABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_TILED_CACHING_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_TC_LAZY_VALIDATION 2:2 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_TC_LAZY_VALIDATION_ENABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_TC_LAZY_VALIDATION_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_SETUP_OUTPUT_LIMITER 7:3 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_SETUP_OUTPUT_LIMITER_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32 15:8 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_BTWT_FIFO_REDUCE_DIV32_FULLSIZE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY 17:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ZERO 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_MULTI 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_ONE 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BINNED_TCBS_PER_REPLAY_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE 19:19 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_ENABLE 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SEMAD_REPORT_NONE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR 20:20 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_PM_MODE_E_BUNDLE_ADDR_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE 21:21 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_TREAT_NON_BINNABLE_AS_IMMEDIATE_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_SPILL_POINT_PATH 22:22 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_SPILL_POINT_PATH_AUTOMATIC 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_SPILL_POINT_PATH_SPILL_BUFFER 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BUNDLE_FILTER 23:23 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_BUNDLE_FILTER_ENABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_BUNDLE_FILTER_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN 24:24 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_ENABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_MULTIPLE_INTERVALS_PER_BIN_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_INSERT_DEBUG_TOKENS 25:25 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_INSERT_DEBUG_TOKENS_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_INSERT_DEBUG_TOKENS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT 29:26 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0010 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0020 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0040 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0080 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0100 0x00000005 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0180 0x00000006 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0200 0x00000007 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0300 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0400 0x00000009 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0600 0x0000000A /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0800 0x0000000B /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0A00 0x0000000C /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0C00 0x0000000D /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x0E00 0x0000000E /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_FLUSH_SPILL_PACKING_TIMEOUT_EQ_0x1000 0x0000000F /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC 30:30 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG_BIN_SCC_FEEDBACK_DATA_SYNC_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG_RESERVED 31:31 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG_RESERVED_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_DEBUG 0x00000E04 /* R--4R */ #define NV_PGPC_PRI_SWDX_DEBUG_RECEIVED_BAD_BUNDLE_DATA 0:0 /* R--VF */ #define NV_PGPC_PRI_SWDX_DEBUG_RESOLVED_TC_ENABLE 1:1 /* R--VF */ #define NV_PGPC_PRI_SWDX_DEBUG_UNEXPECTED_L0_PACKET 2:2 /* R--VF */ #define NV_PGPC_PRI_SWDX_DEBUG_OCCUPIED_SPILL_BUFFER_ENTRIES 26:8 /* R--VF */ #define NV_PGPC_PRI_SWDX_PM 0x00000E08 /* RWE4R */ #define NV_PGPC_PRI_SWDX_PM_SELECT 5:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP0 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP1 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP2 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP3 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP4 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP5 0x00000005 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP6 0x00000006 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP7 0x00000007 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP8 0x00000008 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP9 0x00000009 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP10 0x0000000A /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP11 0x0000000B /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP12 0x0000000C /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP13 0x0000000D /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP14 0x0000000E /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP15 0x0000000F /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP16 0x00000010 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP17 0x00000011 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP18 0x00000012 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP19 0x00000013 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP20 0x00000014 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP21 0x00000015 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP22 0x00000016 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP23 0x00000017 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP24 0x00000018 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP25 0x00000019 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP26 0x0000001A /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP27 0x0000001B /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP28 0x0000001C /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP29 0x0000001D /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP30 0x0000001E /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP31 0x0000001F /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP32 0x00000020 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP33 0x00000021 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP34 0x00000022 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP35 0x00000023 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP36 0x00000024 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP37 0x00000025 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP38 0x00000026 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP39 0x00000027 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP40 0x00000028 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP41 0x00000029 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP42 0x0000002A /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP43 0x0000002B /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_GRP44 0x0000002C /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_USERDATA_BUNDLE_FLUSH_GROUP 0x0000002D /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_STATIC_PATTERN_2AA_10_GROUP 0x0000002E /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_STATIC_PATTERN_155_10_GROUP 0x0000002F /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_DEBUG_SIGNAL_INSTANCE_ID_GROUP 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_SELECT_MAX 0x00000030 /* RW--V */ #define NV_PGPC_PRI_SWDX_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PM_ENABLE_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PM_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_BASE 0x00000E24 /* RWI4R */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_BASE_ADDR_39_8_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE 0x00000E28 /* RWI4R */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B 10:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE_DIV_256B_INIT 48 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE_VALID 31:31 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE_VALID_FALSE 0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RM_BUNDLE_CB_SIZE_VALID_TRUE 1 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_TIMEOUT 0x00000E34 /* RWI4R */ #define NV_PGPC_PRI_SWDX_TC_TIMEOUT_VALUE 31:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_TIMEOUT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_COUNT 0x00000E38 /* RWI4R */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_COUNT_VALUE 31:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_COUNT_VALUE_INIT 0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO 0x00000E3C /* R--4R */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_BUNDLE_ADDR 15:0 /* R--VF */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON 30:16 /* R--VF */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_CBE_MEMORY 0x1 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_CBE_SLOT 0x2 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_PAGEPOOL 0x3 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_CBTBL 0x4 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_BIN_MEMORY 0x5 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_LEVEL0 0x6 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_LEVEL1 0x7 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_STATE_COUNT 0x8 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_TC_FLUSH_METHOD 0x9 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_RTV_LIMIT_HIT 0xA /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_STATE 0xB /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_TIMEOUT 0xC /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_INTERVAL_BOUNDARY 0xD /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_NON_BINNABLE_LINES 0xE /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_TIMESLICE_BUNDLE 0xF /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_REASON_Z_MODE_TRANSITION 0x10 /* R---V */ #define NV_PGPC_PRI_SWDX_TC_FLUSH_INFO_VALID 31:31 /* R--VF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL(i) (0x00000E40+(i)*4) /* RWI4A */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL__SIZE_1 4 /* */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0 0:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE 2:1 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE 3:3 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_0_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1 4:4 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE 6:5 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE 7:7 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_1_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2 8:8 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE 10:9 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE 11:11 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_2_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3 12:12 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE 14:13 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE 15:15 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_3_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4 16:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE 18:17 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE 19:19 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_4_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5 20:20 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE 22:21 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE 23:23 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_5_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6 24:24 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE 26:25 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE 27:27 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_6_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7 28:28 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_EMPTY 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_USED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE 30:29 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_NOT_TILED 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_FIRST 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_MODE_TILED_REPLAY_ALL 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE 31:31 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_LIGHT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_CTRL_SLOT_7_TYPE_HEAVY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL(i) (0x00000E50+(i)*4) /* RWI4A */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL__SIZE_1 2 /* */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0 1:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_0_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1 3:2 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_1_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2 5:4 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_2_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3 7:6 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_3_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4 9:8 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_4_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5 11:10 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_5_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6 13:12 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_6_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7 15:14 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_7_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8 17:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_8_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9 19:18 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_9_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10 21:20 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_10_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11 23:22 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_11_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12 25:24 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_12_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13 27:26 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_13_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14 29:28 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_14_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15 31:30 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_CACHE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_NO_FLUSH 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_LAZYVAL_CTRL_SLOT_15_NOCACHE_FLUSH 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR(i) (0x00000E58+(i)*4) /* RWI4A */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR__SIZE_1 16 /* */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR_SLOT_0 15:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR_SLOT_0_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR_SLOT_1 31:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BUNDLE_ADDR_SLOT_1_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT 0x00000E9C /* RWE4R */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ 1:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_FIRST 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_READ_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE 3:2 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_FIRST 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_CTXSW_WRITE_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE 5:4 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_NORMAL 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_WRITE_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ 7:6 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_FIRST 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_SPILL_BUFFER_READ_EVICT_LAST 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ 9:8 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_FIRST 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_NORMAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LINE_CLASS_STATE_READ_EVICT_LAST 0x00000002 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE 16:16 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_BUFFER_CACHE_MGMT_MODE_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE 17:17 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_DIRECT_CTXSW_WRITE_BURST_MODE_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE 18:18 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_A 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_ENABLE_MODE_B 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE 19:19 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_A 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_TC_TIMEOUT_DISABLE_MODE_B 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE 20:20 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_SPILL_WRITE_BURST_MODE_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION 22:21 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_HALF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_QUARTER 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_BIN_RAM_REDUCTION_EIGHTH 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION 24:23 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_HALF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_QUARTER 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL0_RAM_REDUCTION_EIGHTH 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION 26:25 /* RWEVF */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_NONE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_HALF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_QUARTER 0x00000002 /* RW--V */ #define NV_PGPC_PRI_SWDX_SPILL_UNIT_LEVEL1_RAM_REDUCTION_EIGHTH 0x00000003 /* RW--V */ #define NV_PGPC_PRI_SWDX_TC_BETA_CB_SIZE(i) (0x00000EA0+(i)*4) /* RWI4A */ #define NV_PGPC_PRI_SWDX_TC_BETA_CB_SIZE__SIZE_1 21 /* */ #define NV_PGPC_PRI_SWDX_TC_BETA_CB_SIZE_V 21:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_TC_BETA_CB_SIZE_V_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_TC_BETA_CB_SIZE_V_DEFAULT 1152 /* RW--V */ #define NV_PGPC_PRI_SWDX_CONFIG2 0x000001CC /* RWI4R */ #define NV_PGPC_PRI_SWDX_CONFIG2_ASYNC_TC_OVERRIDE 00:00 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_NONE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONFIG2_ASYNC_TC_OVERRIDE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_PES_MASK 0x000001D0 /* RWE4R */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_0 3:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_0_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_1 7:4 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_1_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_2 11:8 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_3 15:12 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_3_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_4 19:16 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_4_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_5 23:20 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_5_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_6 27:24 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_6_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_7 31:28 /* RWEVF */ #define NV_PGPC_PRI_SWDX_PES_MASK_GPC_7_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_ADDR 0x000001D8 /* RWI4R */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* ----V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_ADDR_39_8_ALIGN_BITS 0x00000008 /* ----V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_SIZE 0x000001DC /* RWI4R */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_SIZE_256B 15:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_SIZE_256B_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_SIZE_256B_DEFAULT 1400 /* ----V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_SIZE_256B_BYTE_GRANULARITY 0x00000100 /* ----V */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_LWM 0x000001E0 /* RWI4R */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B 15:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RM_SPILL_BUFFER_LWM_SIZE_256B_INIT 0x0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_BETA_CB_CTRL 0x000001E4 /* RWI4R */ #define NV_PGPC_PRI_SWDX_BETA_CB_CTRL_CBES_RESERVE 11:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_BETA_CB_CTRL_CBES_RESERVE_NON_GFXP 0 /* RWI-V */ #define NV_PGPC_PRI_SWDX_BETA_CB_CTRL_CBES_RESERVE_GFXP 256 /* RW--V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL 0x000001E8 /* RWE4R */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_SAVE 1:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_SAVE_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_WFI 0x00000001 /* -W--T */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_SAVE_RUN_GFXP 0x00000002 /* -W--T */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_RESTORE 3:2 /* RWEVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_RESTORE_IDLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_WFI 0x00000001 /* -W--T */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_GFXP 0x00000002 /* -W--T */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_RESTORE_RUN_SCRUB 0x00000003 /* -W--T */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED 9:8 /* R-EVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_FALSE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_WFI 0x00000001 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_SAVED_GFXP 0x00000002 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED 11:10 /* R-EVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_FALSE 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_WFI 0x00000001 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_GFXP 0x00000002 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_STATUS_RESTORED_SCRUB 0x00000003 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS 16:16 /* R-EVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_EMPTY 0x00000000 /* R-E-V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_CTRL_BINNER_RAM_STATUS_NONEMPTY 0x00000001 /* R---V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_ADDR 0x000001EC /* RW-4R */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_ADDR_39_8 31:0 /* RWXVF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_ADDR_39_8_BYTE_GRANULARITY 0x00000100 /* ----V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_ADDR_39_8_ALIGN_BITS 0x00000008 /* ----V */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_SIZE_WFI 0x000001F0 /* R--4R */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_SIZE_WFI_VALUE 31:0 /* R--VF */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_SIZE_GFXP 0x000001F4 /* R--4R */ #define NV_PGPC_PRI_SWDX_DIRECT_CTXSW_SIZE_GFXP_VALUE 31:0 /* R--VF */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_ON 0x000001F8 /* RWI4R */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_ON_PPOOL 9:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_ON_PPOOL_INIT 450 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_ON_CBTBL 25:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_ON_CBTBL_INIT 450 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_OFF 0x000001FC /* RWI4R */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_OFF_PPOOL 9:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_OFF_PPOOL_INIT 498 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_OFF_CBTBL 25:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_CONST_LIMITS_TS_OFF_CBTBL_INIT 498 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RTV_LIMITS 0x000001C8 /* RWI4R */ #define NV_PGPC_PRI_SWDX_RTV_LIMITS_TS_OFF 13:0 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RTV_LIMITS_TS_OFF_INIT 13 /* RWI-V */ #define NV_PGPC_PRI_SWDX_RTV_LIMITS_TS_ON 29:16 /* RWIVF */ #define NV_PGPC_PRI_SWDX_RTV_LIMITS_TS_ON_INIT 12 /* RWI-V */ #define NV_PGPC_PRI_SWDX_CG 0x00000E0C /* RWE4R */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_SWDX_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_SWDX_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_SWDX_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_SWDX_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_SWDX_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_SWDX_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_SWDX_CG1 0x00000E10 /* RWE4R */ #define NV_PGPC_PRI_SWDX_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG1_SLCG 31:1 /* RWEVF */ #define NV_PGPC_PRI_SWDX_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_SWDX_CG1_SLCG_DISABLED 0x7FFFFFFF /* RWE-V */ #define NV_PGPC_PRI_SWDX_CG1_SLCG__PROD 0x7FFFFFFF /* RW--V */ #define NV_PGPC_PRI_GCC 0x000013FF:0x00001000 /* RW--L */ #define NV_PGPC_PRI_GCC_DBG 0x00001000 /* RWI4R */ #define NV_PGPC_PRI_GCC_DBG_L15 0:0 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_L15_ENABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_L15_DISABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_INVALIDATE 1:1 /* -WIVF */ #define NV_PGPC_PRI_GCC_DBG_INVALIDATE_TASK 0x00000001 /* -W--T */ #define NV_PGPC_PRI_GCC_DBG_INVALIDATE_TASK_INIT 0x00000000 /* -WI-V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_INSTR 2:2 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_INSTR_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_NUM_WAYS_DISABLED 5:3 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_NUM_WAYS_DISABLED_0 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL 6:6 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_PAGEPOOL_CHANNEL_BLOCKING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL 7:7 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_NONBLOCKING 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_NOT_IN_PAGEPOOL_CHANNEL_BLOCKING 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_VA_CONSTANTS_CHANNEL 8:8 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_VA_CONSTANTS_CHANNEL_NONBLOCKING 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_VA_CONSTANTS_CHANNEL_BLOCKING 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_INSTRUCTIONS_CHANNEL 9:9 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_INSTRUCTIONS_CHANNEL_NONBLOCKING 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_INSTRUCTIONS_CHANNEL_BLOCKING 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_TSL2_CHANNEL 10:10 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_TSL2_CHANNEL_NONBLOCKING 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_TSL2_CHANNEL_BLOCKING 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT0 11:11 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT0_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT0_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT1 12:12 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT1_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_HIT1_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_MISS 13:13 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_MISS_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_ARB_DISABLE_MISS_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_API 14:14 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_GFX_API_DX 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_GFX_API_OGL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL 15:15 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_NONBLOCKING 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CONSTANTS_IN_RTV_CHANNEL_BLOCKING 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR 17:17 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_INSTR_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_RTV 18:18 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_RTV_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_RTV_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_WORLD_RTV_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET 22:19 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_PREFETCH_MAX_COUNT_PER_SET_INIT 0x00000004 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_PREFETCH_MAX_TOTAL 28:23 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_PREFETCH_MAX_TOTAL_INIT 0x00000020 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CYA_CONST_CL_FETCH 29:29 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_CYA_CONST_CL_FETCH_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CYA_CONST_CL_FETCH_FULL 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_CYA_CONST_CL_FETCH_PARTIAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_CYA_INVALIDATE_ALL 30:30 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_CYA_INVALIDATE_ALL_DISABLE 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_CYA_INVALIDATE_ALL_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_RTV 31:31 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_GFX_PREFETCH_SCREEN_RTV_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_3 0x00001014 /* RWI4R */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_ENABLE 0:0 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_ENABLE_INIT 0x00000001 /* RWI-V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET 3:1 /* RWIVF */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_256B 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_768B 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_1792B 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_2816B 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_3840B 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_3_PREFETCH_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL_BASE 0x00001004 /* RWI4R */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_RM_RTV_CB_BASE 0x00001034 /* RWI4R */ #define NV_PGPC_PRI_GCC_RM_RTV_CB_BASE_ADDR_39_8 31:0 /* RWIVF */ #define NV_PGPC_PRI_GCC_RM_RTV_CB_BASE_ADDR_39_8_INIT 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL 0x00001008 /* RWI4R */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL_TOTAL_PAGES 9:0 /* RWIVF */ #define NV_PGPC_PRI_GCC_RM_PAGEPOOL_TOTAL_PAGES_HWMAX 0x00000000 /* RWI-V */ #define NV_PGPC_PRI_GCC_PERFMON 0x0000100C /* RWE4R */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OUTPUT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_HITMISS2 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_HITMISS3 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_HITMISS4 0x00000003 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_HITMISS5 0x00000004 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_HITMISS6 0x00000005 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_STATIC_PATTERN_25_6_GROUP 0x00000006 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_STATIC_PATTERN_1A_6_GROUP 0x00000007 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_LATENCY 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_MISC1 0x00000009 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_MISC2 0x0000000a /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_SM2GCC_INP_REQ 0x0000000b /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OUTSTANDING_MISS_TO_RETURN 0x0000000c /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OUTSTANDING_INSTR_REQ 0x0000000d /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OUTSTANDING_CONST_REQ 0x0000000e /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OUTSTANDING_TEX_REQ 0x0000000f /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GPM2GCC_PIX 0x00000010 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_PIPE_STALL1 0x00000011 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_PIPE_STALL2 0x00000012 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_OCCUPANCY_MISS_BUFFER 0x00000013 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_INSTR_PREFETCH 0x00000014 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_TEX_INVAL_BUNDLES 0x00000015 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_QMD_PREFETCH 0x00000016 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_L15_HITMISS1 0x00000017 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_L15_HITMISS2 0x00000018 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_L15_HITMISS3 0x00000019 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_L15_HITMISS4 0x0000001a /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_L15_GNIC_REQ 0x0000001b /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GCC_PREFETCH 0x0000001c /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_PPCAM_HITMISS 0x0000001d /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_IN_OUT_REQS 0x0000001e /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_INVAL_REQS 0x0000001f /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_QMD_CONST_PREFETCH 0x00000020 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GFX_INST_PREFETCH 0x00000021 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_0 0x00000022 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_1 0x00000023 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_2 0x00000024 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_SELECT_GFX_CONST_PREFETCH_3 0x00000025 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_GCC_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_HWW_ESR 0x00001028 /* RWE4R */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_CORRECTED 0:0 /* R--VF */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_CORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_CORRECTED_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_UNCORRECTED 1:1 /* R--VF */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_UNCORRECTED_NOT_PENDING 0x0 /* R---V */ #define NV_PGPC_PRI_GCC_HWW_ESR_ECC_UNCORRECTED_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_GCC_HWW_ESR_RESET 30:30 /* -WEVF */ #define NV_PGPC_PRI_GCC_HWW_ESR_RESET_INACTIVE 0x0 /* -WE-V */ #define NV_PGPC_PRI_GCC_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */ #define NV_PGPC_PRI_GCC_HWW_ESR_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_GCC_HWW_ESR_EN_DISABLE 0x0 /* RW--V */ #define NV_PGPC_PRI_GCC_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG 0x00001020 /* RWE4R */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_GCC_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_GCC_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_GCC_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_GCC_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_GCC_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_GCC_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_GCC_CG1 0x00001024 /* RWE4R */ #define NV_PGPC_PRI_GCC_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_GCC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_GCC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGPC_PRI_GCC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_GCC_CG1_SLCG__PROD 0x000000FF /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK 0x00001040 /* RWE4R */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_GCC_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL 0x00001044 /* RWE4R */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL__PRIV_LEVEL_MASK 0x00001040 /* */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR 0:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR 1:1 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* -W--T */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS 0x00001048 /* RWE4R */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0 0:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1 1:1 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0 4:4 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK0_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1 5:5 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_BANK1_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 8:8 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 9:9 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 10:10 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 11:11 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_RESET_TASK 0x1 /* RW--T */ #define NV_PGPC_PRI_GCC_L15_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_CORRECTED_ERR_COUNT 0x0000104C /* RWE4R */ #define NV_PGPC_PRI_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_UNCORRECTED_ERR_COUNT 0x00001054 /* RWE4R */ #define NV_PGPC_PRI_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_GCC_L15_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_GCC_L15_ECC_ADDRESS 0x00001058 /* R--4R */ #define NV_PGPC_PRI_GCC_L15_ECC_ADDRESS_INDEX 16:0 /* R-XVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK 0x00001060 /* RWE4R */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "gcc_dbg" /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_GCC_DBG_2 0x0000105c /* RWE4R */ #define NV_PGPC_PRI_GCC_DBG_2__PRIV_LEVEL_MASK 0x00001060 /* */ #define NV_PGPC_PRI_GCC_DBG_2_SPARE 31:0 /* RWEVF */ #define NV_PGPC_PRI_GCC_DBG_2_SPARE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL 0x00000880 /* RWE4R */ #define NV_PGPC_PRI_MMU_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_VM_PG_SIZE_128KB 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_VM_PG_SIZE_64KB 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_COMP_FAULT_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_COMP_FAULT_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_MISS_GRAN_FULL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_MISS_GRAN_HALF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_MISS_GRAN_QUARTER 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_MISS_GRAN_NO_PTE_COMP 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_PDE_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_PDE_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_L2_SEND_MODE_ONE_PTE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_L2_SEND_MODE_WHOLE_CL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_WORK_CREATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_WORK_CREATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL 0x00001480 /* RWE4R */ #define NV_PGPC_PRI_MMU0_CTRL_VM_PG_SIZE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_VM_PG_SIZE_128KB 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_VM_PG_SIZE_64KB 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_COMP_FAULT 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_COMP_FAULT_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_COMP_FAULT_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_MISS_GRAN 4:3 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_MISS_GRAN_FULL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_MISS_GRAN_HALF 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_MISS_GRAN_QUARTER 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_MISS_GRAN_NO_PTE_COMP 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_CACHE_MODE 6:5 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_PDE_CACHE_MODE 8:7 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_PDE_CACHE_MODE_ON 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_PDE_CACHE_MODE_EVICT_SMPG_PARTIALS 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_PDE_CACHE_MODE_EVICT_ALL_PARTIALS 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_PDE_CACHE_MODE_OFF 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_L2_SEND_MODE 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_L2_SEND_MODE_ONE_PTE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_L2_SEND_MODE_WHOLE_CL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_WORK_CREATION_DISABLE 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_WORK_CREATION_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_WORK_CREATION_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_USE_PDB_BIG_PAGE_SIZE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_MODE 25:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_L2 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_ATOMIC 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_RMW 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_MODE_POWER 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_OFF 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_STRONG_BIT_ATOMIC_CYA_ON 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_L2 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_ATOMIC_CAPABILITY_SYS_NCOH_MODE_FOLLOW_SYS_COH 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM 0x00000884 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_SELECT 8:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_00 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_01 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_02 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_03 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_04 0x00000004 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_05 0x00000005 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_06 0x00000006 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_07 0x00000007 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_08 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_09 0x00000009 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0A 0x0000000A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0B 0x0000000B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0C 0x0000000C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0D 0x0000000D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0E 0x0000000E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_0F 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10 0x00000010 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11 0x00000011 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12 0x00000012 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13 0x00000013 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14 0x00000014 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15 0x00000015 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17 0x00000017 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18 0x00000018 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19 0x00000019 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A 0x0000001A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B 0x0000001B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C 0x0000001C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D 0x0000001D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E 0x0000001E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F 0x0000001F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_20 0x00000020 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_21 0x00000021 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_22 0x00000022 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_23 0x00000023 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_24 0x00000024 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_25 0x00000025 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_26 0x00000026 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_27 0x00000027 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_28 0x00000028 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_29 0x00000029 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2A 0x0000002A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2B 0x0000002B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2C 0x0000002C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2D 0x0000002D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2E 0x0000002E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_2F 0x0000002F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_30 0x00000030 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_31 0x00000031 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_32 0x00000032 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_33 0x00000033 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_34 0x00000034 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_35 0x00000035 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_36 0x00000036 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_37 0x00000037 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_38 0x00000038 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_39 0x00000039 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3A 0x0000003A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3B 0x0000003B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3C 0x0000003C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3D 0x0000003D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3E 0x0000003E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_3F 0x0000003F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_40 0x00000040 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_41 0x00000041 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_42 0x00000042 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_43 0x00000043 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_44 0x00000044 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_45 0x00000045 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_46 0x00000046 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_47 0x00000047 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_48 0x00000048 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_49 0x00000049 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4A 0x0000004A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4B 0x0000004B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4C 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4D 0x0000004D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4E 0x0000004E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_4F 0x0000004F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_50 0x00000050 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_51 0x00000051 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_52 0x00000052 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_53 0x00000053 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_54 0x00000054 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_55 0x00000055 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_56 0x00000056 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_57 0x00000057 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_58 0x00000058 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_59 0x00000059 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5A 0x0000005A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5B 0x0000005B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5C 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5D 0x0000005D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5E 0x0000005E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_5F 0x0000005F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_60 0x00000060 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_61 0x00000061 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_62 0x00000062 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_63 0x00000063 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_64 0x00000064 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_65 0x00000065 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_66 0x00000066 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_67 0x00000067 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_68 0x00000068 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_69 0x00000069 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6A 0x0000006A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6B 0x0000006B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6C 0x0000006C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6D 0x0000006D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6E 0x0000006E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_6F 0x0000006F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_70 0x00000070 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_71 0x00000071 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_72 0x00000072 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_73 0x00000073 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_74 0x00000074 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_75 0x00000075 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_76 0x00000076 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_77 0x00000077 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_78 0x00000078 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_79 0x00000079 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7A 0x0000007A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7B 0x0000007B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7C 0x0000007C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7D 0x0000007D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7E 0x0000007E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_7F 0x0000007F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_80 0x00000080 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_81 0x00000081 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_82 0x00000082 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_83 0x00000083 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_84 0x00000084 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_85 0x00000085 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_86 0x00000086 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_87 0x00000087 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_88 0x00000088 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_89 0x00000089 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8A 0x0000008A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8B 0x0000008B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8C 0x0000008C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8D 0x0000008D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8E 0x0000008E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_8F 0x0000008F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_90 0x00000090 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_91 0x00000091 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_92 0x00000092 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_93 0x00000093 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_94 0x00000094 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_95 0x00000095 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_96 0x00000096 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_97 0x00000097 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_98 0x00000098 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_99 0x00000099 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9A 0x0000009A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9B 0x0000009B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9C 0x0000009C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9D 0x0000009D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9E 0x0000009E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_9F 0x0000009F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A0 0x000000A0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A1 0x000000A1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A2 0x000000A2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A3 0x000000A3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A4 0x000000A4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A5 0x000000A5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A6 0x000000A6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A7 0x000000A7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A8 0x000000A8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_A9 0x000000A9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AA 0x000000AA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AB 0x000000AB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AC 0x000000AC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AD 0x000000AD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AE 0x000000AE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_AF 0x000000AF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B0 0x000000B0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B1 0x000000B1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B2 0x000000B2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B3 0x000000B3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B4 0x000000B4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B5 0x000000B5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B6 0x000000B6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B7 0x000000B7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B8 0x000000B8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_B9 0x000000B9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BA 0x000000BA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BB 0x000000BB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BC 0x000000BC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BD 0x000000BD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BE 0x000000BE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_BF 0x000000BF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C0 0x000000C0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C1 0x000000C1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C2 0x000000C2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C3 0x000000C3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C4 0x000000C4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C5 0x000000C5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C6 0x000000C6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C7 0x000000C7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C8 0x000000C8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_C9 0x000000C9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CA 0x000000CA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CB 0x000000CB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CC 0x000000CC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CD 0x000000CD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CE 0x000000CE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_CF 0x000000CF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D0 0x000000D0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D1 0x000000D1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D2 0x000000D2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D3 0x000000D3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D4 0x000000D4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D5 0x000000D5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D6 0x000000D6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D7 0x000000D7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D8 0x000000D8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_D9 0x000000D9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DA 0x000000DA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DB 0x000000DB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DC 0x000000DC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DD 0x000000DD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DE 0x000000DE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_DF 0x000000DF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E0 0x000000E0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E1 0x000000E1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E2 0x000000E2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E3 0x000000E3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E4 0x000000E4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E5 0x000000E5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E6 0x000000E6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E7 0x000000E7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E8 0x000000E8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_E9 0x000000E9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_EA 0x000000EA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_EB 0x000000EB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_EC 0x000000EC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_ED 0x000000ED /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_EE 0x000000EE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_EF 0x000000EF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F0 0x000000F0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F1 0x000000F1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F2 0x000000F2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F3 0x000000F3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F4 0x000000F4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F5 0x000000F5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F6 0x000000F6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F7 0x000000F7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F8 0x000000F8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_F9 0x000000F9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_FA 0x000000FA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_FB 0x000000FB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_FC 0x000000FC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_FD 0x000000FD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_100 0x00000100 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_101 0x00000101 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_102 0x00000102 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_103 0x00000103 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_104 0x00000104 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_105 0x00000105 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_106 0x00000106 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_107 0x00000107 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_108 0x00000108 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_109 0x00000109 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10A 0x0000010A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10B 0x0000010B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10C 0x0000010C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10D 0x0000010D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10E 0x0000010E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_10F 0x0000010F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_110 0x00000110 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_111 0x00000111 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_112 0x00000112 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_113 0x00000113 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_114 0x00000114 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_115 0x00000115 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_116 0x00000116 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_117 0x00000117 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_118 0x00000118 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_119 0x00000119 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11A 0x0000011A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11B 0x0000011B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11C 0x0000011C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11D 0x0000011D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11E 0x0000011E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_11F 0x0000011F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_120 0x00000120 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_121 0x00000121 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_122 0x00000122 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_123 0x00000123 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_124 0x00000124 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_125 0x00000125 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_126 0x00000126 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_127 0x00000127 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_128 0x00000128 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_129 0x00000129 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12A 0x0000012A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12B 0x0000012B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12C 0x0000012C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12D 0x0000012D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12E 0x0000012E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_12F 0x0000012F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_130 0x00000130 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_131 0x00000131 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_132 0x00000132 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_133 0x00000133 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_134 0x00000134 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_135 0x00000135 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_136 0x00000136 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_137 0x00000137 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_138 0x00000138 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_139 0x00000139 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13A 0x0000013A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13B 0x0000013B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13C 0x0000013C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13D 0x0000013D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13E 0x0000013E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_13F 0x0000013F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_140 0x00000140 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_141 0x00000141 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_142 0x00000142 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_143 0x00000143 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_144 0x00000144 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_145 0x00000145 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_146 0x00000146 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_147 0x00000147 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_148 0x00000148 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_149 0x00000149 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14A 0x0000014A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14B 0x0000014B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14C 0x0000014C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14D 0x0000014D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14E 0x0000014E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_14F 0x0000014F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_150 0x00000150 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_151 0x00000151 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_152 0x00000152 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_153 0x00000153 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_154 0x00000154 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_155 0x00000155 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_156 0x00000156 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_157 0x00000157 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_158 0x00000158 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_159 0x00000159 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15A 0x0000015A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15B 0x0000015B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15C 0x0000015C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15D 0x0000015D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15E 0x0000015E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_15F 0x0000015F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_160 0x00000160 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_161 0x00000161 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_162 0x00000162 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_163 0x00000163 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_164 0x00000164 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_165 0x00000165 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_166 0x00000166 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_167 0x00000167 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_168 0x00000168 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_169 0x00000169 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16A 0x0000016A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16B 0x0000016B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16C 0x0000016C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16D 0x0000016D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16E 0x0000016E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_16F 0x0000016F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_170 0x00000170 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_171 0x00000171 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_172 0x00000172 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_173 0x00000173 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_174 0x00000174 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_175 0x00000175 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_176 0x00000176 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_177 0x00000177 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_178 0x00000178 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_179 0x00000179 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17A 0x0000017A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17B 0x0000017B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17C 0x0000017C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17D 0x0000017D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17E 0x0000017E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_17F 0x0000017F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_180 0x00000180 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_181 0x00000181 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_182 0x00000182 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_183 0x00000183 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_184 0x00000184 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_185 0x00000185 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_186 0x00000186 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_187 0x00000187 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_188 0x00000188 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_189 0x00000189 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18A 0x0000018A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18B 0x0000018B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18C 0x0000018C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18D 0x0000018D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18E 0x0000018E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_18F 0x0000018F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_190 0x00000190 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_191 0x00000191 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_192 0x00000192 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_193 0x00000193 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_194 0x00000194 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_195 0x00000195 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_196 0x00000196 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_197 0x00000197 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_198 0x00000198 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_199 0x00000199 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19A 0x0000019A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19B 0x0000019B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19C 0x0000019C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19D 0x0000019D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19E 0x0000019E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_19F 0x0000019F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AA 0x000001AA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AB 0x000001AB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AC 0x000001AC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AD 0x000001AD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AE 0x000001AE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1AF 0x000001AF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BA 0x000001BA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BB 0x000001BB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BC 0x000001BC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BD 0x000001BD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BE 0x000001BE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1BF 0x000001BF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CA 0x000001CA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CB 0x000001CB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CC 0x000001CC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CD 0x000001CD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CE 0x000001CE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1CF 0x000001CF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DA 0x000001DA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DB 0x000001DB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DC 0x000001DC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DD 0x000001DD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DE 0x000001DE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1DF 0x000001DF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1EA 0x000001EA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1EB 0x000001EB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1EC 0x000001EC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1ED 0x000001ED /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1EE 0x000001EE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1EF 0x000001EF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FA 0x000001FA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FB 0x000001FB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FC 0x000001FC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FD 0x000001FD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FE 0x000001FE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_GRP_1FF 0x000001FF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_00 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_01 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_02 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_03 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_04 0x00000004 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_05 0x00000005 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_06 0x00000006 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_07 0x00000007 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_08 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_09 0x00000009 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0A 0x0000000A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0B 0x0000000B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0C 0x0000000C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0D 0x0000000D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0E 0x0000000E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_0F 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10 0x00000010 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11 0x00000011 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12 0x00000012 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13 0x00000013 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14 0x00000014 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15 0x00000015 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17 0x00000017 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18 0x00000018 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19 0x00000019 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A 0x0000001A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B 0x0000001B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C 0x0000001C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D 0x0000001D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E 0x0000001E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F 0x0000001F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_20 0x00000020 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_21 0x00000021 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_22 0x00000022 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_23 0x00000023 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_24 0x00000024 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_25 0x00000025 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_26 0x00000026 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_27 0x00000027 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_28 0x00000028 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_29 0x00000029 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2A 0x0000002A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2B 0x0000002B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2C 0x0000002C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2D 0x0000002D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2E 0x0000002E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_2F 0x0000002F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_30 0x00000030 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_31 0x00000031 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_32 0x00000032 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_33 0x00000033 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_34 0x00000034 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_35 0x00000035 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_36 0x00000036 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_37 0x00000037 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_38 0x00000038 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_39 0x00000039 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3A 0x0000003A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3B 0x0000003B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3C 0x0000003C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3D 0x0000003D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3E 0x0000003E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_3F 0x0000003F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_40 0x00000040 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_41 0x00000041 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_42 0x00000042 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_43 0x00000043 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_44 0x00000044 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_45 0x00000045 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_46 0x00000046 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_47 0x00000047 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_48 0x00000048 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_49 0x00000049 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4A 0x0000004A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4B 0x0000004B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4C 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4D 0x0000004D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4E 0x0000004E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_4F 0x0000004F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_50 0x00000050 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_51 0x00000051 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_52 0x00000052 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_53 0x00000053 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_54 0x00000054 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_55 0x00000055 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_56 0x00000056 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_57 0x00000057 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_58 0x00000058 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_59 0x00000059 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5A 0x0000005A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5B 0x0000005B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5C 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5D 0x0000005D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5E 0x0000005E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_5F 0x0000005F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_60 0x00000060 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_61 0x00000061 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_62 0x00000062 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_63 0x00000063 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_64 0x00000064 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_65 0x00000065 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_66 0x00000066 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_67 0x00000067 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_68 0x00000068 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_69 0x00000069 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6A 0x0000006A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6B 0x0000006B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6C 0x0000006C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6D 0x0000006D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6E 0x0000006E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_6F 0x0000006F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_70 0x00000070 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_71 0x00000071 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_72 0x00000072 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_73 0x00000073 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_74 0x00000074 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_75 0x00000075 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_76 0x00000076 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_77 0x00000077 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_78 0x00000078 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_79 0x00000079 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7A 0x0000007A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7B 0x0000007B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7C 0x0000007C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7D 0x0000007D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7E 0x0000007E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_7F 0x0000007F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_80 0x00000080 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_81 0x00000081 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_82 0x00000082 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_83 0x00000083 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_84 0x00000084 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_85 0x00000085 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_86 0x00000086 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_87 0x00000087 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_88 0x00000088 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_89 0x00000089 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8A 0x0000008A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8B 0x0000008B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8C 0x0000008C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8D 0x0000008D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8E 0x0000008E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_8F 0x0000008F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_90 0x00000090 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_91 0x00000091 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_92 0x00000092 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_93 0x00000093 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_94 0x00000094 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_95 0x00000095 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_96 0x00000096 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_97 0x00000097 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_98 0x00000098 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_99 0x00000099 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9A 0x0000009A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9B 0x0000009B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9C 0x0000009C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9D 0x0000009D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9E 0x0000009E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_9F 0x0000009F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A0 0x000000A0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A1 0x000000A1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A2 0x000000A2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A3 0x000000A3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A4 0x000000A4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A5 0x000000A5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A6 0x000000A6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A7 0x000000A7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A8 0x000000A8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_A9 0x000000A9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AA 0x000000AA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AB 0x000000AB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AC 0x000000AC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AD 0x000000AD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AE 0x000000AE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_AF 0x000000AF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B0 0x000000B0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B1 0x000000B1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B2 0x000000B2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B3 0x000000B3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B4 0x000000B4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B5 0x000000B5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B6 0x000000B6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B7 0x000000B7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B8 0x000000B8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_B9 0x000000B9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BA 0x000000BA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BB 0x000000BB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BC 0x000000BC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BD 0x000000BD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BE 0x000000BE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_BF 0x000000BF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C0 0x000000C0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C1 0x000000C1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C2 0x000000C2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C3 0x000000C3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C4 0x000000C4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C5 0x000000C5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C6 0x000000C6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C7 0x000000C7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C8 0x000000C8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_C9 0x000000C9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CA 0x000000CA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CB 0x000000CB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CC 0x000000CC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CD 0x000000CD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CE 0x000000CE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_CF 0x000000CF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D0 0x000000D0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D1 0x000000D1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D2 0x000000D2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D3 0x000000D3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D4 0x000000D4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D5 0x000000D5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D6 0x000000D6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D7 0x000000D7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D8 0x000000D8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_D9 0x000000D9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DA 0x000000DA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DB 0x000000DB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DC 0x000000DC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DD 0x000000DD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DE 0x000000DE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_DF 0x000000DF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E0 0x000000E0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E1 0x000000E1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E2 0x000000E2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E3 0x000000E3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E4 0x000000E4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E5 0x000000E5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E6 0x000000E6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E7 0x000000E7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E8 0x000000E8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_E9 0x000000E9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_EA 0x000000EA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_EB 0x000000EB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_EC 0x000000EC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_ED 0x000000ED /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_EE 0x000000EE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_EF 0x000000EF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F0 0x000000F0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F1 0x000000F1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F2 0x000000F2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F3 0x000000F3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F4 0x000000F4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F5 0x000000F5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F6 0x000000F6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F7 0x000000F7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F8 0x000000F8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_F9 0x000000F9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_FA 0x000000FA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_FB 0x000000FB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_FC 0x000000FC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_FD 0x000000FD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_100 0x00000100 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_101 0x00000101 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_102 0x00000102 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_103 0x00000103 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_104 0x00000104 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_105 0x00000105 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_106 0x00000106 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_107 0x00000107 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_108 0x00000108 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_109 0x00000109 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10A 0x0000010A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10B 0x0000010B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10C 0x0000010C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10D 0x0000010D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10E 0x0000010E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_10F 0x0000010F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_110 0x00000110 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_111 0x00000111 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_112 0x00000112 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_113 0x00000113 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_114 0x00000114 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_115 0x00000115 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_116 0x00000116 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_117 0x00000117 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_118 0x00000118 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_119 0x00000119 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11A 0x0000011A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11B 0x0000011B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11C 0x0000011C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11D 0x0000011D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11E 0x0000011E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_11F 0x0000011F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_120 0x00000120 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_121 0x00000121 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_122 0x00000122 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_123 0x00000123 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_124 0x00000124 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_125 0x00000125 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_126 0x00000126 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_127 0x00000127 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_128 0x00000128 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_129 0x00000129 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12A 0x0000012A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12B 0x0000012B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12C 0x0000012C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12D 0x0000012D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12E 0x0000012E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_12F 0x0000012F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_130 0x00000130 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_131 0x00000131 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_132 0x00000132 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_133 0x00000133 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_134 0x00000134 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_135 0x00000135 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_136 0x00000136 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_137 0x00000137 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_138 0x00000138 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_139 0x00000139 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13A 0x0000013A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13B 0x0000013B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13C 0x0000013C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13D 0x0000013D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13E 0x0000013E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_13F 0x0000013F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_140 0x00000140 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_141 0x00000141 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_142 0x00000142 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_143 0x00000143 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_144 0x00000144 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_145 0x00000145 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_146 0x00000146 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_147 0x00000147 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_148 0x00000148 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_149 0x00000149 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14A 0x0000014A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14B 0x0000014B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14C 0x0000014C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14D 0x0000014D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14E 0x0000014E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_14F 0x0000014F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_150 0x00000150 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_151 0x00000151 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_152 0x00000152 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_153 0x00000153 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_154 0x00000154 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_155 0x00000155 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_156 0x00000156 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_157 0x00000157 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_158 0x00000158 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_159 0x00000159 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15A 0x0000015A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15B 0x0000015B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15C 0x0000015C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15D 0x0000015D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15E 0x0000015E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_15F 0x0000015F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_160 0x00000160 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_161 0x00000161 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_162 0x00000162 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_163 0x00000163 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_164 0x00000164 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_165 0x00000165 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_166 0x00000166 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_167 0x00000167 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_168 0x00000168 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_169 0x00000169 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16A 0x0000016A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16B 0x0000016B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16C 0x0000016C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16D 0x0000016D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16E 0x0000016E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_16F 0x0000016F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_170 0x00000170 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_171 0x00000171 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_172 0x00000172 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_173 0x00000173 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_174 0x00000174 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_175 0x00000175 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_176 0x00000176 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_177 0x00000177 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_178 0x00000178 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_179 0x00000179 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17A 0x0000017A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17B 0x0000017B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17C 0x0000017C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17D 0x0000017D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17E 0x0000017E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_17F 0x0000017F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_180 0x00000180 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_181 0x00000181 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_182 0x00000182 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_183 0x00000183 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_184 0x00000184 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_185 0x00000185 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_186 0x00000186 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_187 0x00000187 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_188 0x00000188 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_189 0x00000189 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18A 0x0000018A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18B 0x0000018B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18C 0x0000018C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18D 0x0000018D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18E 0x0000018E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_18F 0x0000018F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_190 0x00000190 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_191 0x00000191 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_192 0x00000192 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_193 0x00000193 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_194 0x00000194 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_195 0x00000195 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_196 0x00000196 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_197 0x00000197 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_198 0x00000198 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_199 0x00000199 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19A 0x0000019A /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19B 0x0000019B /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19C 0x0000019C /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19D 0x0000019D /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19E 0x0000019E /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_19F 0x0000019F /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AA 0x000001AA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AB 0x000001AB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AC 0x000001AC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AD 0x000001AD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AE 0x000001AE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1AF 0x000001AF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BA 0x000001BA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BB 0x000001BB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BC 0x000001BC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BD 0x000001BD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BE 0x000001BE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1BF 0x000001BF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CA 0x000001CA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CB 0x000001CB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CC 0x000001CC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CD 0x000001CD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CE 0x000001CE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1CF 0x000001CF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DA 0x000001DA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DB 0x000001DB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DC 0x000001DC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DD 0x000001DD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DE 0x000001DE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1DF 0x000001DF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1EA 0x000001EA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1EB 0x000001EB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1EC 0x000001EC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1ED 0x000001ED /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1EE 0x000001EE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1EF 0x000001EF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FA 0x000001FA /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FB 0x000001FB /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FC 0x000001FC /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FD 0x000001FD /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FE 0x000001FE /* RW--V */ #define NV_PGPC_PRI_MMU_PM_SELECT_MUX1_GRP_1FF 0x000001FF /* RW--V */ #define NV_PGPC_PRI_MMU_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_ALT_INPUT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_ALT_INPUT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_ALT_INPUT_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_BLK_ACT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_BLK_ACT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_BLK_ACT_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM 0x00001484 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_SELECT 8:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_00 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_01 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_02 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_03 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_04 0x00000004 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_05 0x00000005 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_06 0x00000006 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_07 0x00000007 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_08 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_09 0x00000009 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0A 0x0000000A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0B 0x0000000B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0C 0x0000000C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0D 0x0000000D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0E 0x0000000E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_0F 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10 0x00000010 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11 0x00000011 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12 0x00000012 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13 0x00000013 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14 0x00000014 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15 0x00000015 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17 0x00000017 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18 0x00000018 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19 0x00000019 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A 0x0000001A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B 0x0000001B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C 0x0000001C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D 0x0000001D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E 0x0000001E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F 0x0000001F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_20 0x00000020 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_21 0x00000021 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_22 0x00000022 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_23 0x00000023 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_24 0x00000024 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_25 0x00000025 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_26 0x00000026 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_27 0x00000027 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_28 0x00000028 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_29 0x00000029 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2A 0x0000002A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2B 0x0000002B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2C 0x0000002C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2D 0x0000002D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2E 0x0000002E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_2F 0x0000002F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_30 0x00000030 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_31 0x00000031 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_32 0x00000032 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_33 0x00000033 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_34 0x00000034 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_35 0x00000035 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_36 0x00000036 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_37 0x00000037 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_38 0x00000038 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_39 0x00000039 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3A 0x0000003A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3B 0x0000003B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3C 0x0000003C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3D 0x0000003D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3E 0x0000003E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_3F 0x0000003F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_40 0x00000040 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_41 0x00000041 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_42 0x00000042 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_43 0x00000043 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_44 0x00000044 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_45 0x00000045 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_46 0x00000046 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_47 0x00000047 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_48 0x00000048 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_49 0x00000049 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4A 0x0000004A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4B 0x0000004B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4C 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4D 0x0000004D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4E 0x0000004E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_4F 0x0000004F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_50 0x00000050 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_51 0x00000051 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_52 0x00000052 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_53 0x00000053 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_54 0x00000054 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_55 0x00000055 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_56 0x00000056 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_57 0x00000057 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_58 0x00000058 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_59 0x00000059 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5A 0x0000005A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5B 0x0000005B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5C 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5D 0x0000005D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5E 0x0000005E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_5F 0x0000005F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_60 0x00000060 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_61 0x00000061 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_62 0x00000062 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_63 0x00000063 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_64 0x00000064 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_65 0x00000065 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_66 0x00000066 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_67 0x00000067 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_68 0x00000068 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_69 0x00000069 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6A 0x0000006A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6B 0x0000006B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6C 0x0000006C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6D 0x0000006D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6E 0x0000006E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_6F 0x0000006F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_70 0x00000070 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_71 0x00000071 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_72 0x00000072 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_73 0x00000073 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_74 0x00000074 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_75 0x00000075 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_76 0x00000076 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_77 0x00000077 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_78 0x00000078 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_79 0x00000079 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7A 0x0000007A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7B 0x0000007B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7C 0x0000007C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7D 0x0000007D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7E 0x0000007E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_7F 0x0000007F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_80 0x00000080 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_81 0x00000081 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_82 0x00000082 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_83 0x00000083 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_84 0x00000084 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_85 0x00000085 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_86 0x00000086 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_87 0x00000087 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_88 0x00000088 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_89 0x00000089 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8A 0x0000008A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8B 0x0000008B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8C 0x0000008C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8D 0x0000008D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8E 0x0000008E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_8F 0x0000008F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_90 0x00000090 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_91 0x00000091 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_92 0x00000092 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_93 0x00000093 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_94 0x00000094 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_95 0x00000095 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_96 0x00000096 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_97 0x00000097 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_98 0x00000098 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_99 0x00000099 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9A 0x0000009A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9B 0x0000009B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9C 0x0000009C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9D 0x0000009D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9E 0x0000009E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_9F 0x0000009F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A0 0x000000A0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A1 0x000000A1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A2 0x000000A2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A3 0x000000A3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A4 0x000000A4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A5 0x000000A5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A6 0x000000A6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A7 0x000000A7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A8 0x000000A8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_A9 0x000000A9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AA 0x000000AA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AB 0x000000AB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AC 0x000000AC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AD 0x000000AD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AE 0x000000AE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_AF 0x000000AF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B0 0x000000B0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B1 0x000000B1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B2 0x000000B2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B3 0x000000B3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B4 0x000000B4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B5 0x000000B5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B6 0x000000B6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B7 0x000000B7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B8 0x000000B8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_B9 0x000000B9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BA 0x000000BA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BB 0x000000BB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BC 0x000000BC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BD 0x000000BD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BE 0x000000BE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_BF 0x000000BF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C0 0x000000C0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C1 0x000000C1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C2 0x000000C2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C3 0x000000C3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C4 0x000000C4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C5 0x000000C5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C6 0x000000C6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C7 0x000000C7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C8 0x000000C8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_C9 0x000000C9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CA 0x000000CA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CB 0x000000CB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CC 0x000000CC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CD 0x000000CD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CE 0x000000CE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_CF 0x000000CF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D0 0x000000D0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D1 0x000000D1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D2 0x000000D2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D3 0x000000D3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D4 0x000000D4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D5 0x000000D5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D6 0x000000D6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D7 0x000000D7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D8 0x000000D8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_D9 0x000000D9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DA 0x000000DA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DB 0x000000DB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DC 0x000000DC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DD 0x000000DD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DE 0x000000DE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_DF 0x000000DF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E0 0x000000E0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E1 0x000000E1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E2 0x000000E2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E3 0x000000E3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E4 0x000000E4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E5 0x000000E5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E6 0x000000E6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E7 0x000000E7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E8 0x000000E8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_E9 0x000000E9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_EA 0x000000EA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_EB 0x000000EB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_EC 0x000000EC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_ED 0x000000ED /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_EE 0x000000EE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_EF 0x000000EF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F0 0x000000F0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F1 0x000000F1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F2 0x000000F2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F3 0x000000F3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F4 0x000000F4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F5 0x000000F5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F6 0x000000F6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F7 0x000000F7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F8 0x000000F8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_F9 0x000000F9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_FA 0x000000FA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_FB 0x000000FB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_FC 0x000000FC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_FD 0x000000FD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_100 0x00000100 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_101 0x00000101 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_102 0x00000102 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_103 0x00000103 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_104 0x00000104 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_105 0x00000105 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_106 0x00000106 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_107 0x00000107 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_108 0x00000108 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_109 0x00000109 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10A 0x0000010A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10B 0x0000010B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10C 0x0000010C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10D 0x0000010D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10E 0x0000010E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_10F 0x0000010F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_110 0x00000110 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_111 0x00000111 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_112 0x00000112 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_113 0x00000113 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_114 0x00000114 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_115 0x00000115 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_116 0x00000116 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_117 0x00000117 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_118 0x00000118 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_119 0x00000119 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11A 0x0000011A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11B 0x0000011B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11C 0x0000011C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11D 0x0000011D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11E 0x0000011E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_11F 0x0000011F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_120 0x00000120 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_121 0x00000121 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_122 0x00000122 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_123 0x00000123 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_124 0x00000124 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_125 0x00000125 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_126 0x00000126 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_127 0x00000127 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_128 0x00000128 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_129 0x00000129 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12A 0x0000012A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12B 0x0000012B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12C 0x0000012C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12D 0x0000012D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12E 0x0000012E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_12F 0x0000012F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_130 0x00000130 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_131 0x00000131 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_132 0x00000132 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_133 0x00000133 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_134 0x00000134 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_135 0x00000135 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_136 0x00000136 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_137 0x00000137 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_138 0x00000138 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_139 0x00000139 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13A 0x0000013A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13B 0x0000013B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13C 0x0000013C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13D 0x0000013D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13E 0x0000013E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_13F 0x0000013F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_140 0x00000140 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_141 0x00000141 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_142 0x00000142 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_143 0x00000143 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_144 0x00000144 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_145 0x00000145 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_146 0x00000146 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_147 0x00000147 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_148 0x00000148 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_149 0x00000149 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14A 0x0000014A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14B 0x0000014B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14C 0x0000014C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14D 0x0000014D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14E 0x0000014E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_14F 0x0000014F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_150 0x00000150 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_151 0x00000151 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_152 0x00000152 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_153 0x00000153 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_154 0x00000154 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_155 0x00000155 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_156 0x00000156 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_157 0x00000157 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_158 0x00000158 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_159 0x00000159 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15A 0x0000015A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15B 0x0000015B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15C 0x0000015C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15D 0x0000015D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15E 0x0000015E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_15F 0x0000015F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_160 0x00000160 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_161 0x00000161 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_162 0x00000162 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_163 0x00000163 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_164 0x00000164 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_165 0x00000165 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_166 0x00000166 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_167 0x00000167 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_168 0x00000168 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_169 0x00000169 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16A 0x0000016A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16B 0x0000016B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16C 0x0000016C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16D 0x0000016D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16E 0x0000016E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_16F 0x0000016F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_170 0x00000170 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_171 0x00000171 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_172 0x00000172 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_173 0x00000173 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_174 0x00000174 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_175 0x00000175 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_176 0x00000176 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_177 0x00000177 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_178 0x00000178 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_179 0x00000179 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17A 0x0000017A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17B 0x0000017B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17C 0x0000017C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17D 0x0000017D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17E 0x0000017E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_17F 0x0000017F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_180 0x00000180 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_181 0x00000181 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_182 0x00000182 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_183 0x00000183 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_184 0x00000184 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_185 0x00000185 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_186 0x00000186 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_187 0x00000187 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_188 0x00000188 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_189 0x00000189 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18A 0x0000018A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18B 0x0000018B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18C 0x0000018C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18D 0x0000018D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18E 0x0000018E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_18F 0x0000018F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_190 0x00000190 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_191 0x00000191 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_192 0x00000192 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_193 0x00000193 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_194 0x00000194 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_195 0x00000195 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_196 0x00000196 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_197 0x00000197 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_198 0x00000198 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_199 0x00000199 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19A 0x0000019A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19B 0x0000019B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19C 0x0000019C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19D 0x0000019D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19E 0x0000019E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_19F 0x0000019F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AA 0x000001AA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AB 0x000001AB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AC 0x000001AC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AD 0x000001AD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AE 0x000001AE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1AF 0x000001AF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BA 0x000001BA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BB 0x000001BB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BC 0x000001BC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BD 0x000001BD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BE 0x000001BE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1BF 0x000001BF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CA 0x000001CA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CB 0x000001CB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CC 0x000001CC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CD 0x000001CD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CE 0x000001CE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1CF 0x000001CF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DA 0x000001DA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DB 0x000001DB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DC 0x000001DC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DD 0x000001DD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DE 0x000001DE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1DF 0x000001DF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1EA 0x000001EA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1EB 0x000001EB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1EC 0x000001EC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1ED 0x000001ED /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1EE 0x000001EE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1EF 0x000001EF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FA 0x000001FA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FB 0x000001FB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FC 0x000001FC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FD 0x000001FD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FE 0x000001FE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_GRP_1FF 0x000001FF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1 24:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_00 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_01 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_02 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_03 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_04 0x00000004 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_05 0x00000005 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_06 0x00000006 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_07 0x00000007 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_08 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_09 0x00000009 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0A 0x0000000A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0B 0x0000000B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0C 0x0000000C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0D 0x0000000D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0E 0x0000000E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_0F 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10 0x00000010 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11 0x00000011 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12 0x00000012 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13 0x00000013 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14 0x00000014 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15 0x00000015 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16 0x00000016 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17 0x00000017 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18 0x00000018 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19 0x00000019 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A 0x0000001A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B 0x0000001B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C 0x0000001C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D 0x0000001D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E 0x0000001E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F 0x0000001F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_20 0x00000020 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_21 0x00000021 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_22 0x00000022 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_23 0x00000023 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_24 0x00000024 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_25 0x00000025 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_26 0x00000026 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_27 0x00000027 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_28 0x00000028 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_29 0x00000029 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2A 0x0000002A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2B 0x0000002B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2C 0x0000002C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2D 0x0000002D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2E 0x0000002E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_2F 0x0000002F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_30 0x00000030 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_31 0x00000031 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_32 0x00000032 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_33 0x00000033 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_34 0x00000034 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_35 0x00000035 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_36 0x00000036 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_37 0x00000037 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_38 0x00000038 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_39 0x00000039 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3A 0x0000003A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3B 0x0000003B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3C 0x0000003C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3D 0x0000003D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3E 0x0000003E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_3F 0x0000003F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_40 0x00000040 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_41 0x00000041 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_42 0x00000042 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_43 0x00000043 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_44 0x00000044 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_45 0x00000045 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_46 0x00000046 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_47 0x00000047 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_48 0x00000048 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_49 0x00000049 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4A 0x0000004A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4B 0x0000004B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4C 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4D 0x0000004D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4E 0x0000004E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_4F 0x0000004F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_50 0x00000050 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_51 0x00000051 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_52 0x00000052 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_53 0x00000053 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_54 0x00000054 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_55 0x00000055 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_56 0x00000056 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_57 0x00000057 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_58 0x00000058 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_59 0x00000059 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5A 0x0000005A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5B 0x0000005B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5C 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5D 0x0000005D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5E 0x0000005E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_5F 0x0000005F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_60 0x00000060 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_61 0x00000061 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_62 0x00000062 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_63 0x00000063 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_64 0x00000064 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_65 0x00000065 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_66 0x00000066 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_67 0x00000067 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_68 0x00000068 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_69 0x00000069 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6A 0x0000006A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6B 0x0000006B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6C 0x0000006C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6D 0x0000006D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6E 0x0000006E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_6F 0x0000006F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_70 0x00000070 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_71 0x00000071 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_72 0x00000072 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_73 0x00000073 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_74 0x00000074 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_75 0x00000075 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_76 0x00000076 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_77 0x00000077 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_78 0x00000078 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_79 0x00000079 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7A 0x0000007A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7B 0x0000007B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7C 0x0000007C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7D 0x0000007D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7E 0x0000007E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_7F 0x0000007F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_80 0x00000080 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_81 0x00000081 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_82 0x00000082 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_83 0x00000083 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_84 0x00000084 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_85 0x00000085 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_86 0x00000086 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_87 0x00000087 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_88 0x00000088 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_89 0x00000089 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8A 0x0000008A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8B 0x0000008B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8C 0x0000008C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8D 0x0000008D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8E 0x0000008E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_8F 0x0000008F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_90 0x00000090 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_91 0x00000091 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_92 0x00000092 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_93 0x00000093 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_94 0x00000094 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_95 0x00000095 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_96 0x00000096 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_97 0x00000097 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_98 0x00000098 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_99 0x00000099 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9A 0x0000009A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9B 0x0000009B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9C 0x0000009C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9D 0x0000009D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9E 0x0000009E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_9F 0x0000009F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A0 0x000000A0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A1 0x000000A1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A2 0x000000A2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A3 0x000000A3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A4 0x000000A4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A5 0x000000A5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A6 0x000000A6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A7 0x000000A7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A8 0x000000A8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_A9 0x000000A9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AA 0x000000AA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AB 0x000000AB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AC 0x000000AC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AD 0x000000AD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AE 0x000000AE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_AF 0x000000AF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B0 0x000000B0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B1 0x000000B1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B2 0x000000B2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B3 0x000000B3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B4 0x000000B4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B5 0x000000B5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B6 0x000000B6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B7 0x000000B7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B8 0x000000B8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_B9 0x000000B9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BA 0x000000BA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BB 0x000000BB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BC 0x000000BC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BD 0x000000BD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BE 0x000000BE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_BF 0x000000BF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C0 0x000000C0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C1 0x000000C1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C2 0x000000C2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C3 0x000000C3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C4 0x000000C4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C5 0x000000C5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C6 0x000000C6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C7 0x000000C7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C8 0x000000C8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_C9 0x000000C9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CA 0x000000CA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CB 0x000000CB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CC 0x000000CC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CD 0x000000CD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CE 0x000000CE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_CF 0x000000CF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D0 0x000000D0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D1 0x000000D1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D2 0x000000D2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D3 0x000000D3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D4 0x000000D4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D5 0x000000D5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D6 0x000000D6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D7 0x000000D7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D8 0x000000D8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_D9 0x000000D9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DA 0x000000DA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DB 0x000000DB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DC 0x000000DC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DD 0x000000DD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DE 0x000000DE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_DF 0x000000DF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E0 0x000000E0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E1 0x000000E1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E2 0x000000E2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E3 0x000000E3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E4 0x000000E4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E5 0x000000E5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E6 0x000000E6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E7 0x000000E7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E8 0x000000E8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_E9 0x000000E9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_EA 0x000000EA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_EB 0x000000EB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_EC 0x000000EC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_ED 0x000000ED /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_EE 0x000000EE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_EF 0x000000EF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F0 0x000000F0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F1 0x000000F1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F2 0x000000F2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F3 0x000000F3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F4 0x000000F4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F5 0x000000F5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F6 0x000000F6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F7 0x000000F7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F8 0x000000F8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_F9 0x000000F9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_FA 0x000000FA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_FB 0x000000FB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_FC 0x000000FC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_FD 0x000000FD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_5_4_GROUP 0x000000FE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_STATIC_PATTERN_A_4_GROUP 0x000000FF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_100 0x00000100 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_101 0x00000101 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_102 0x00000102 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_103 0x00000103 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_104 0x00000104 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_105 0x00000105 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_106 0x00000106 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_107 0x00000107 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_108 0x00000108 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_109 0x00000109 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10A 0x0000010A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10B 0x0000010B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10C 0x0000010C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10D 0x0000010D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10E 0x0000010E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_10F 0x0000010F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_110 0x00000110 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_111 0x00000111 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_112 0x00000112 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_113 0x00000113 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_114 0x00000114 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_115 0x00000115 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_116 0x00000116 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_117 0x00000117 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_118 0x00000118 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_119 0x00000119 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11A 0x0000011A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11B 0x0000011B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11C 0x0000011C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11D 0x0000011D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11E 0x0000011E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_11F 0x0000011F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_120 0x00000120 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_121 0x00000121 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_122 0x00000122 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_123 0x00000123 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_124 0x00000124 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_125 0x00000125 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_126 0x00000126 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_127 0x00000127 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_128 0x00000128 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_129 0x00000129 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12A 0x0000012A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12B 0x0000012B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12C 0x0000012C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12D 0x0000012D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12E 0x0000012E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_12F 0x0000012F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_130 0x00000130 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_131 0x00000131 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_132 0x00000132 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_133 0x00000133 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_134 0x00000134 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_135 0x00000135 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_136 0x00000136 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_137 0x00000137 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_138 0x00000138 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_139 0x00000139 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13A 0x0000013A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13B 0x0000013B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13C 0x0000013C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13D 0x0000013D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13E 0x0000013E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_13F 0x0000013F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_140 0x00000140 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_141 0x00000141 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_142 0x00000142 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_143 0x00000143 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_144 0x00000144 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_145 0x00000145 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_146 0x00000146 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_147 0x00000147 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_148 0x00000148 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_149 0x00000149 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14A 0x0000014A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14B 0x0000014B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14C 0x0000014C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14D 0x0000014D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14E 0x0000014E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_14F 0x0000014F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_150 0x00000150 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_151 0x00000151 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_152 0x00000152 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_153 0x00000153 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_154 0x00000154 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_155 0x00000155 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_156 0x00000156 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_157 0x00000157 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_158 0x00000158 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_159 0x00000159 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15A 0x0000015A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15B 0x0000015B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15C 0x0000015C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15D 0x0000015D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15E 0x0000015E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_15F 0x0000015F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_160 0x00000160 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_161 0x00000161 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_162 0x00000162 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_163 0x00000163 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_164 0x00000164 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_165 0x00000165 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_166 0x00000166 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_167 0x00000167 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_168 0x00000168 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_169 0x00000169 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16A 0x0000016A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16B 0x0000016B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16C 0x0000016C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16D 0x0000016D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16E 0x0000016E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_16F 0x0000016F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_170 0x00000170 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_171 0x00000171 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_172 0x00000172 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_173 0x00000173 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_174 0x00000174 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_175 0x00000175 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_176 0x00000176 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_177 0x00000177 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_178 0x00000178 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_179 0x00000179 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17A 0x0000017A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17B 0x0000017B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17C 0x0000017C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17D 0x0000017D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17E 0x0000017E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_17F 0x0000017F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_180 0x00000180 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_181 0x00000181 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_182 0x00000182 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_183 0x00000183 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_184 0x00000184 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_185 0x00000185 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_186 0x00000186 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_187 0x00000187 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_188 0x00000188 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_189 0x00000189 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18A 0x0000018A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18B 0x0000018B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18C 0x0000018C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18D 0x0000018D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18E 0x0000018E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_18F 0x0000018F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_190 0x00000190 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_191 0x00000191 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_192 0x00000192 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_193 0x00000193 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_194 0x00000194 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_195 0x00000195 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_196 0x00000196 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_197 0x00000197 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_198 0x00000198 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_199 0x00000199 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19A 0x0000019A /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19B 0x0000019B /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19C 0x0000019C /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19D 0x0000019D /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19E 0x0000019E /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_19F 0x0000019F /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A0 0x000001A0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A1 0x000001A1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A2 0x000001A2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A3 0x000001A3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A4 0x000001A4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A5 0x000001A5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A6 0x000001A6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A7 0x000001A7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A8 0x000001A8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1A9 0x000001A9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AA 0x000001AA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AB 0x000001AB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AC 0x000001AC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AD 0x000001AD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AE 0x000001AE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1AF 0x000001AF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B0 0x000001B0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B1 0x000001B1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B2 0x000001B2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B3 0x000001B3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B4 0x000001B4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B5 0x000001B5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B6 0x000001B6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B7 0x000001B7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B8 0x000001B8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1B9 0x000001B9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BA 0x000001BA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BB 0x000001BB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BC 0x000001BC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BD 0x000001BD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BE 0x000001BE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1BF 0x000001BF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C0 0x000001C0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C1 0x000001C1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C2 0x000001C2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C3 0x000001C3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C4 0x000001C4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C5 0x000001C5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C6 0x000001C6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C7 0x000001C7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C8 0x000001C8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1C9 0x000001C9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CA 0x000001CA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CB 0x000001CB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CC 0x000001CC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CD 0x000001CD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CE 0x000001CE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1CF 0x000001CF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D0 0x000001D0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D1 0x000001D1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D2 0x000001D2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D3 0x000001D3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D4 0x000001D4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D5 0x000001D5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D6 0x000001D6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D7 0x000001D7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D8 0x000001D8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1D9 0x000001D9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DA 0x000001DA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DB 0x000001DB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DC 0x000001DC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DD 0x000001DD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DE 0x000001DE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1DF 0x000001DF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E0 0x000001E0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E1 0x000001E1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E2 0x000001E2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E3 0x000001E3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E4 0x000001E4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E5 0x000001E5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E6 0x000001E6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E7 0x000001E7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E8 0x000001E8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1E9 0x000001E9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1EA 0x000001EA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1EB 0x000001EB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1EC 0x000001EC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1ED 0x000001ED /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1EE 0x000001EE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1EF 0x000001EF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F0 0x000001F0 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F1 0x000001F1 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F2 0x000001F2 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F3 0x000001F3 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F4 0x000001F4 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F5 0x000001F5 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F6 0x000001F6 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F7 0x000001F7 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F8 0x000001F8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1F9 0x000001F9 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FA 0x000001FA /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FB 0x000001FB /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FC 0x000001FC /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FD 0x000001FD /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FE 0x000001FE /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_SELECT_MUX1_GRP_1FF 0x000001FF /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_ALT_INPUT 29:29 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_ALT_INPUT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_ALT_INPUT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_ALT_INPUT_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_BLK_ACT 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_BLK_ACT_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_BLK_ACT_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_BLK_ACT_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_ADDR_LOW 0x00000888 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGPC_PRI_MMU0_PM_ADDR_LOW 0x00001488 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_ADDR_LOW_BITS 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_ADDR_LOW_ALIGNMENT 0x00000008 /* */ #define NV_PGPC_PRI_MMU_PM_ADDR_HIGH 0x0000088C /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGPC_PRI_MMU0_PM_ADDR_HIGH 0x0000148C /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_ADDR_HIGH_BITS 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_ADDR_HIGH_ALIGNMENT 0x00000008 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK 0x00000300 /* RWE4R */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK 0x00001400 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU0_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK 0x00000358 /* RWE4R */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK 0x00001458 /* RWE4R */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "mmu_plm" /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 8 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 12 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_mmu_plm_wr_secure" /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_FECS_ENABLED_FUSE1 0x0000005C /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK 0x0000032C /* RWE4R */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK 0x0000142C /* RWE4R */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00000308 /* RWE4R */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK 0x00001408 /* RWE4R */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK 0x00000328 /* RWE4R */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK 0x00001428 /* RWE4R */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 15 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 12 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_sram_ecc_wr_secure" /* */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWE-V */ #define NV_PGPC_PRI_MMU0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_SEC2_GSP_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL 0x00000310 /* RWE4R */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000328 /* */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL 0x00001410 /* RWE4R */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL__PRIV_LEVEL_MASK 0x00000328 /* */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_CORRECTED_ERR__NOP 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_TASK 0x1 /* RW--T */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CONTROL_INJECT_UNCORRECTED_ERR__NOP 0x0 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS 0x00000314 /* RWE4R */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS 0x00001414 /* RWE4R */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_SA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA 3:3 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_L1TLB_FA_DATA_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_CORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_TOTAL_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_UNCORRECTED_ERR_UNIQUE_COUNTER_OVERFLOW_PENDING 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_RESET 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_RESET_CLEAR 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_RESET_TASK 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_STATUS_RESET_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00000318 /* R-E4R */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* R-E-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* R-E-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT 0x00001418 /* R-E4R */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL 15:0 /* R-EVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_TOTAL_INIT 0 /* R-E-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE 31:16 /* R-EVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_CORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* R-E-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0000031C /* RWE4R */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT 0x0000141C /* RWE4R */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL 15:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_TOTAL_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE 31:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_UNCORRECTED_ERR_COUNT_UNIQUE_INIT 0 /* RWE-V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS 0x00000320 /* R--4R */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS 0x00001420 /* R--4R */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_INDEX 31:0 /* R-XVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_CACHELINE 11:0 /* R-XVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_ERROR_MASK 27:12 /* R-XVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_RAM_ID 31:28 /* R-XVF */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_SA_DATA 0x1 /* RW--V */ #define NV_PGPC_PRI_MMU0_L1TLB_ECC_ADDRESS_RAM_ID_L1TLB_FA_DATA 0x2 /* RW--V */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR 0x00000324 /* R-E4R */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_MMU_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR 0x00001424 /* R-E4R */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR 0:0 /* R-EVF */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_CORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR 1:1 /* R-EVF */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_NOT_PENDING 0x0 /* R-E-V */ #define NV_PGPC_PRI_MMU0_GPCMMU_GLOBAL_ESR_ECC_UNCORRECTED_ERR_PENDING 0x1 /* R---V */ #define NV_PGPC_PRI_MMU_TLB_CTRL 0x000008A4 /* RWE4R */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_FA_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_RGG_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_CTRL_LTP_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL 0x000014A4 /* RWE4R */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_SIZE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_SIZE 5:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_RB_SIZE 7:6 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_SIZE 9:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_RB_SIZE 11:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SIZE 13:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_FA_SIZE 15:14 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_FA_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_RB_SIZE 17:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG 19:18 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SET_INDEX_BIG_PG_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG 21:20 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_SET_INDEX_SMALL_PG_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_PRF_FAULT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_PRF_FAULT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_PROP_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_L1_FAST_PATH_DISABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_DB_SIZE 29:28 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_RGG_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_DB_SIZE 31:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_CTRL_LTP_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_MISC 0x0000037C /* RWE4R */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_MISC 0x0000147C /* RWE4R */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_SIZE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_RB_SIZE 3:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_RB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_DB_SIZE 5:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_DB_SIZE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_TLB_MISC_ROP_WR_DATA_HAS_BUBBLES_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD 0x000008A8 /* RWE4R */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_RSRVD_MEMBAR_RQ_TRACKING_RW 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_RSRVD 0x000014A8 /* RWE4R */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_CL_VC_B 2:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_CL_VC_NB 5:3 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_RB_VC_B 8:6 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_RB_VC_NB 11:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_RGG_UTLB_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_CL_VC_B 14:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_CL_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_CL_VC_NB 17:15 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_CL_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_RB_VC_B 20:18 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_RB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_RB_VC_NB 23:21 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_RB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_DB_VC_B 26:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_DB_VC_B_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_DB_VC_NB 29:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_LTP_UTLB_DB_VC_NB_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_MEMBAR_RQ_TRACKING 31:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_RSRVD_MEMBAR_RQ_TRACKING_RW 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_RSRVD_MEMBAR_RQ_TRACKING_WRT 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_RSRVD_MEMBAR_RQ_TRACKING_SYSMEM 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_RSRVD_MEMBAR_RQ_TRACKING_NONE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS 0x000008AC /* RWE4R */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_V_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_COUNT_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGPC_PRI_MMU_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 4 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS 0x000014AC /* RWE4R */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_V 4:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_V_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_COUNT 4:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_COUNT_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_HALF_LTC 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_HALF_LTC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK 23:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER(i) ((i)+16):((i)+16) /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER__SIZE_1 8 /* */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_USE_NVLINK_PEER_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_NVLINK_PEER_THROUGH_L2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC 30:28 /* RWEVF */ #define NV_PGPC_PRI_MMU0_NUM_ACTIVE_LTCS_SLICES_PER_LTC_INIT 4 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL 0x000008B0 /* RWE4R */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_WR_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_RD_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_DEBUG_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_DEBUG_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_4KB 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_64KB 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_128KB 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_CTRL_PAGE_SIZE_1MB 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL 0x000014B0 /* RWE4R */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_WR_KIND 7:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_WR_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_RD_KIND 15:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_RD_KIND_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_DEBUG 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_DEBUG_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_DEBUG_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_PAGE_SIZE 18:17 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_PAGE_SIZE_4KB 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_PAGE_SIZE_64KB 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_PAGE_SIZE_128KB 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_CTRL_PAGE_SIZE_1MB 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_WR 0x000008B4 /* RWE4R */ #define NV_PGPC_PRI_MMU_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_WR_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_WR_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_WR_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_WR_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PGPC_PRI_MMU0_DEBUG_WR 0x000014B4 /* RWE4R */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_APERTURE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_VOL 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_ADDR 31:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_WR_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PGPC_PRI_MMU_DEBUG_RD 0x000008B8 /* RWE4R */ #define NV_PGPC_PRI_MMU_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_RD_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_RD_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_DEBUG_RD_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_DEBUG_RD_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PGPC_PRI_MMU0_DEBUG_RD 0x000014B8 /* RWE4R */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_APERTURE 1:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_APERTURE_VID_MEM 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_APERTURE_PEER_MEM 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_APERTURE_SYS_MEM_C 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_APERTURE_SYS_MEM_NC 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_VOL 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_VOL_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_VOL_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_ADDR 31:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_ADDR_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_DEBUG_RD_ADDR_ALIGNMENT 0x0000000c /* */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_LOW 0x00000334 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_LOW 0x00001434 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_LOW_BITS 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_LOW_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_HIGH 0x00000338 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UPPER_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_HIGH 0x00001438 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_HIGH_BITS 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UPPER_ADDR_HIGH_BITS_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE 0x00000304 /* RWE4R */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE 0x00001404 /* RWE4R */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE__PRIV_LEVEL_MASK 0x00000300 /* */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_PROTECTED_MODE_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_UPDATE_MODE 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_UPDATE_MODE_FALSE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_UPDATE_MODE_TRUE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_UPDATE_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_SECURE_LOCK 29:29 /* R-XVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_SECURE_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_SECURE_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC 28:28 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_MISC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_HWPM_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_WPR_WRITE_VPR_LOCK_SMPC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE 0x0000035C /* RWE4R */ #define NV_PGPC_PRI_MMU_VPR_STATE__PRIV_LEVEL_MASK 0x00000358 /* */ #define NV_PGPC_PRI_MMU_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_VPR_STATE_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VPR_STATE_PROTECTED_MODE_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VPR_STATE 0x0000145C /* RWE4R */ #define NV_PGPC_PRI_MMU0_VPR_STATE__PRIV_LEVEL_MASK 0x00000358 /* */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PROTECTED_MODE 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PROTECTED_MODE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PROTECTED_MODE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VPR_STATE_PROTECTED_MODE_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI 0x00000330 /* RWE4R */ #define NV_PGPC_PRI_MMU_CTRL_DBI__PRIV_LEVEL_MASK 0x0000032C /* */ #define NV_PGPC_PRI_MMU_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_BYPASS_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_BYPASS_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_BYPASS_EN_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_DC_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_DC_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_DC_EN_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_CTRL_DBI_AC_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_AC_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CTRL_DBI_AC_EN_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI 0x00001430 /* RWE4R */ #define NV_PGPC_PRI_MMU0_CTRL_DBI__PRIV_LEVEL_MASK 0x0000032C /* */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_BYPASS_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_BYPASS_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_BYPASS_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_BYPASS_EN_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_DC_EN 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_DC_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_DC_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_DC_EN_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_AC_EN 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_AC_EN_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_AC_EN_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CTRL_DBI_AC_EN_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOTTOM 0x00000340 /* RW-4R */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOTTOM 0x00001440 /* RW-4R */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE 19:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOTTOM_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_MIDDLE 0x00000344 /* RW-4R */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 4096 /* RW--V */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0xC /* RW--V */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_MIDDLE 0x00001444 /* RW-4R */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE 19:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_INIT 0x0 /* RWE-V */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE 4096 /* RW--V */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_MIDDLE_PER_SLICE_ATOM_SIZE_LG2 0xC /* RW--V */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_ATOM_SIZE 4096 #define NV_PGPC_PRI_MMU_MEM_PARTITION_ATOM_SIZE_LG2 0xC #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0 0x00000348 /* RW-4R */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x00000603 /* RWE-V */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOUNDARY_CFG0 0x00001448 /* RW-4R */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL 10:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_MEM_PARTITION_BOUNDARY_CFG0_VAL_INIT 0x00000603 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG 0x0000034C /* RWE4R */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER(i) (((i)*4)+1):((i)*4) /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x00000000 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x00000001 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x00000002 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x00000003 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 1 /* */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGPC_PRI_MMU_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG 0x0000144C /* RWE4R */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER(i) (((i)*4)+1):((i)*4) /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER__SIZE_1 8 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_INVALID 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB0 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_ONLY_HSHUB1 0x00000002 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_BOTH_HSHUBS 0x00000003 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER_PCIE 1 /* */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0 1:0 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER0_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1 5:4 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER1_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2 9:8 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER2_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3 13:12 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER3_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4 17:16 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER4_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5 21:20 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER5_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6 25:24 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER6_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7 29:28 /* RWEUF */ #define NV_PGPC_PRI_MMU0_PEER_HSHUB_CONNECTION_CFG_PEER7_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG 0x00000350 /* RWE4R */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG 0x00001450 /* RWE4R */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS 1:0 /* RWEUF */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INVALID 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB0 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_ONLY_HSHUB1 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_BOTH_HSHUBS 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_PCIE 0x00000003 /* RW--V */ #define NV_PGPC_PRI_MMU0_SYSMEM_HSHUB_CONNECTION_CFG_SYS_INIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_GPCMMU_HYPERVISOR_CTL0 0x00000354 /* RWE4R */ #define NV_PGPC_PRI_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_GPCMMU_HYPERVISOR_CTL0 0x00001454 /* RWE4R */ #define NV_PGPC_PRI_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_GPCMMU_HYPERVISOR_CTL0_CONVERT_ACK_TYPE_VC_TO_GL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT 0x0000033C /* RW-4R */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_SIZE_INIT 1 /* R-E-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x00000005 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT 0x0000143C /* RW-4R */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_SIZE 3:0 /* R-EVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_SIZE_INIT 1 /* R-E-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY 7:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_GRANULARITY_INIT 0x00000005 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE 29:29 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_CLEAR 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_DISABLE_MODE_SET 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_MODE 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_MODE_ACCESS 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_MODE_DIRTY 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_MODE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_ENABLE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_ENABLE_FALSE 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_ENABLE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_ENABLE_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00000360 /* RW-4R */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO 0x00001460 /* RW-4R */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL 31:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_LO_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00000364 /* RW-4R */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI 0x00001464 /* RW-4R */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL 31:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_VIDMEM_ACCESS_BIT_START_ADDR_HI_VAL_INIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK 0x00000890 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TX_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PE_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PE_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPCCS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPCCS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_RAST_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_RAST_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GCC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GCC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GPCCS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_GPCCS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PROP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_PROP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_ROP_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_2_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_2_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_3_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_3_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_4_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_4_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_5_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_5_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_6_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_6_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_7_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_UNIT_MASK_TPC_7_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK 0x00001490 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_0 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_1 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TX_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PE 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PE_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PE_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPCCS 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPCCS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPCCS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_RAST 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_RAST_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_RAST_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GCC 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GCC_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GCC_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GPCCS 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GPCCS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_GPCCS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PROP 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PROP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_PROP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_0 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_1 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_ROP_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_0 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_0_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_0_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_1 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_1_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_1_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_2 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_2_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_2_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_3 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_3_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_3_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_4 20:20 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_4_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_4_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_5 21:21 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_5_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_5_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_6 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_6_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_6_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_7 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_7_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_UNIT_MASK_TPC_7_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK 0x00000894 /* RWE4R */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_MEMBAR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_MEMBAR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PACK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PACK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_VIDMEM_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_VIDMEM_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PEER_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_PEER_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_C_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_C_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_TYPE_VIRTUAL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_TYPE_PHYSICAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PM_REQ_MASK_EXCLUSIVE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK 0x00001494 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_RD 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_WR 1:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GATOM 2:2 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GRED 3:3 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CACHE_MGMT 4:4 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CACHE_MGMT_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CACHE_MGMT_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PREFETCH 5:5 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PF1_PREFETCH 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PF1_PREFETCH_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PF1_PREFETCH_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_MEMBAR 7:7 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_MEMBAR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_MEMBAR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_RD 8:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_WR 9:9 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GRED 10:10 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GATOM 11:11 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PHYS_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PACK_RD 12:12 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PACK_RD_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PACK_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_WR 13:13 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_WR_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GRED 14:14 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GRED_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GRED_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GATOM 15:15 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GATOM_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_CONCAT_GATOM_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_CLIENTS 22:22 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_CLIENTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_CLIENTS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_REQUESTS 23:23 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_REQUESTS_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_ALL_REQUESTS_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_VIDMEM 24:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_VIDMEM_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_VIDMEM_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PEER 25:25 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PEER_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_PEER_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_C 26:26 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_C_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_C_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_NC 27:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_NC_ENABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_SYSMEM_NC_DISABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_TYPE 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_TYPE_VIRTUAL 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_TYPE_PHYSICAL 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_EXCLUSIVE 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_EXCLUSIVE_FALSE 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PM_REQ_MASK_EXCLUSIVE_TRUE 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG 0x00000898 /* RWE4R */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_MMU_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_MMU_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_MMU_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_MMU_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_MMU_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG 0x00001498 /* RWE4R */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_STATE_CG_EN 7:7 /* */ #define NV_PGPC_PRI_MMU0_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PGPC_PRI_MMU0_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PGPC_PRI_MMU0_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_EN 28:28 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PGPC_PRI_MMU0_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_HALT_CG_EN 31:31 /* */ #define NV_PGPC_PRI_MMU0_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PGPC_PRI_MMU0_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PGPC_PRI_MMU0_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PGPC_PRI_MMU_CG1 0x0000089C /* RWE4R */ #define NV_PGPC_PRI_MMU_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGPC_PRI_MMU_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_MMU_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG1 0x0000149C /* RWE4R */ #define NV_PGPC_PRI_MMU0_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG1_SLCG 8:1 /* RWEVF */ #define NV_PGPC_PRI_MMU0_CG1_SLCG_ENABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_MMU0_CG1_SLCG__PROD 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PG 0x000008A0 /* RWE4R */ #define NV_PGPC_PRI_MMU_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_IDLE_BLPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PG_IDLE_BLPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_DIS_EARLY_WUP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PG_DIS_EARLY_WUP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_DEEP_ELPG_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_DEEP_ELPG_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_IDLE_ELPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PG_IDLE_ELPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_DIDT_DELAY_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_RESET_DURATION_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_CLAMP_DELAY_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_ZONE_OFF_MASK_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG_SOFT_GATING_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU_PG_SOFT_GATING_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG 0x000014A0 /* RWE4R */ #define NV_PGPC_PRI_MMU0_PG_IDLE_BLPG_DLY_CNT 7:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_IDLE_BLPG_DLY_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_ELPG_EN_OFFSET_CNT 15:8 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_ELPG_EN_OFFSET_CNT_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_IDLE_BLPG_EN 16:16 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_IDLE_BLPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PG_IDLE_BLPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_DIS_EARLY_WUP 17:17 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_DIS_EARLY_WUP_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PG_DIS_EARLY_WUP_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_DEEP_ELPG_EN 18:18 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_DEEP_ELPG_EN_ENABLED 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_DEEP_ELPG_EN_DISABLED 0x00000000 /* RW--V */ #define NV_PGPC_PRI_MMU0_PG_IDLE_ELPG_EN 19:19 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_IDLE_ELPG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PG_IDLE_ELPG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_DIDT_DELAY 23:20 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_DIDT_DELAY_HWINIT 0x0000000A /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_RESET_DURATION 26:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_RESET_DURATION_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_CLAMP_DELAY 29:27 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_CLAMP_DELAY_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_ZONE_OFF_MASK 30:30 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_ZONE_OFF_MASK_HWINIT 0x00000001 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG_SOFT_GATING_EN 31:31 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG_SOFT_GATING_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PGPC_PRI_MMU0_PG_SOFT_GATING_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG1 0x000008BC /* RWE4R */ #define NV_PGPC_PRI_MMU_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG1_ZONE_SEQ_HWINIT 0x00053977 /* RWE-V */ #define NV_PGPC_PRI_MMU_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGPC_PRI_MMU_PG1_ZONE_MASK_HWINIT 0x000000FF /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG1 0x000014BC /* RWE4R */ #define NV_PGPC_PRI_MMU0_PG1_ZONE_SEQ 23:0 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG1_ZONE_SEQ_HWINIT 0x00053977 /* RWE-V */ #define NV_PGPC_PRI_MMU0_PG1_ZONE_MASK 31:24 /* RWEVF */ #define NV_PGPC_PRI_MMU0_PG1_ZONE_MASK_HWINIT 0x000000FF /* RWE-V */ #endif // __ga102_dev_gpc_no_tpc_h__