/* _NVRM_COPYRIGHT_BEGIN_ * * Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All * information contained herein is proprietary and confidential to NVIDIA * Corporation. Any use, reproduction, or disclosure without the written * permission of NVIDIA Corporation is prohibited. * * _NVRM_COPYRIGHT_END_ */ #ifndef __ga102_dev_fbpa_h__ #define __ga102_dev_fbpa_h__ /* This file is autogenerated. Do not edit */ #define NV_PFB_FBPA_0 0x00903FFF:0x00900000 /* RW--D */ #define NV_PFB_FBPA_1 0x00907FFF:0x00904000 /* RW--D */ #define NV_PFB_FBPA_2 0x0090BFFF:0x00908000 /* RW--D */ #define NV_PFB_FBPA_3 0x0090FFFF:0x0090C000 /* RW--D */ #define NV_PFB_FBPA_4 0x00913FFF:0x00910000 /* RW--D */ #define NV_PFB_FBPA_5 0x00917FFF:0x00914000 /* RW--D */ #define NV_PFB_FBPA_6 0x0091BFFF:0x00918000 /* RW--D */ #define NV_PFB_FBPA_7 0x0091FFFF:0x0091C000 /* RW--D */ #define NV_PFB_FBPA_8 0x00923FFF:0x00920000 /* RW--D */ #define NV_PFB_FBPA_9 0x00927FFF:0x00924000 /* RW--D */ #define NV_PFB_FBPA_A 0x0092BFFF:0x00928000 /* RW--D */ #define NV_PFB_FBPA_B 0x0092FFFF:0x0092C000 /* RW--D */ #define NV_PFB_FBPA_C 0x00933FFF:0x00930000 /* RW--D */ #define NV_PFB_FBPA_D 0x00937FFF:0x00934000 /* RW--D */ #define NV_PFB_FBPA_E 0x0093BFFF:0x00938000 /* RW--D */ #define NV_PFB_FBPA_F 0x0093FFFF:0x0093C000 /* RW--D */ #define NV_PFB_FBPA_10 0x00943FFF:0x00940000 /* RW--D */ #define NV_PFB_FBPA_11 0x00947FFF:0x00944000 /* RW--D */ #define NV_PFB_FBPA_12 0x0094BFFF:0x00948000 /* RW--D */ #define NV_PFB_FBPA_13 0x0094FFFF:0x0094C000 /* RW--D */ #define NV_PFB_FBPA_14 0x00953FFF:0x00950000 /* RW--D */ #define NV_PFB_FBPA_15 0x00957FFF:0x00954000 /* RW--D */ #define NV_PFB_FBPA_16 0x0095BFFF:0x00958000 /* RW--D */ #define NV_PFB_FBPA_17 0x0095FFFF:0x0095C000 /* RW--D */ #define NV_PFB_FBPA_MC0 0x00983FFF:0x00980000 /* RW--D */ #define NV_PFB_FBPA_MC1 0x00987FFF:0x00984000 /* RW--D */ #define NV_PFB_FBPA_MC2 0x0098BFFF:0x00988000 /* RW--D */ #define NV_PFB_FBPA_MC_0 0x00983FFF:0x00980000 /* RW--D */ #define NV_PFB_FBPA_MC_1 0x00987FFF:0x00984000 /* RW--D */ #define NV_PFB_FBPA_MC_2 0x0098BFFF:0x00988000 /* RW--D */ #define NV_PFB_FBPA 0x009A3FFF:0x009A0000 /* RW--D */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK 0x009A0168 /* RW-4R */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK 0x009A0148 /* RW-4R */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK 0x009A014C /* RW-4R */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK 0x009A0170 /* RW-4R */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_ecc" /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK 0x009A01B0 /* RW-4R */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK 0x009A01B4 /* RW-4R */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK 0x009A2578 /* RW-4R */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK 0x009A000C /* RW-4R */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK 0x009A2250 /* RW-4R */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK 0x009A086C /* RW-4R */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_SPARE 0x009A0050 /* RW-4R */ #define NV_PFB_FBPA_SPARE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SPARE_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_SPARE_BITS_INIT 0xFF001040 /* RWI-V */ #define NV_PFB_FBPA_SPARE_BITS_OFIFO_OFFSET 5:0 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_OFIFO_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_CMDFF_DEPTH 12:8 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_CMDFF_DEPTH_INIT 0x00000010 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_CMDFF_DEPTH_MAX 0x00000010 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_CMDFF_DEPTH_SAFE 0x00000004 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_SYNC_PULSE_POLARITY 13:13 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_SYNC_PULSE_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_OFIFO_OFFSET_POLARITY 14:14 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_OFIFO_OFFSET_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_PDEN_OFFSET 19:16 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_PDEN_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_L2_CRC_MODE 20:20 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_L2_CRC_MODE_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_VS_DELAY 23:21 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_VS_DELAY_INIT 0x00000002 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_BIT30 30:30 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_BIT30_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_BUG765178_TEST_MODE 31:31 /* ----F */ #define NV_PFB_FBPA_SPARE_BITS_BUG765178_TEST_MODE_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_BUG765178_TEST_MODE_SKIP 0x00000001 /* ----V */ #define NV_PFB_FBPA_SPARE_BITS_BUG765178_TEST_MODE_RUN 0x00000000 /* ----V */ #define NV_PFB_FBPA_SPARE2 0x009A00CC /* RW-4R */ #define NV_PFB_FBPA_SPARE2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SPARE2_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_SPARE2_BITS_INIT 0xFFFF0000 /* RWI-V */ #define NV_PFB_FBPA_FALCON_MONITOR 0x009A0054 /* RW-4R */ #define NV_PFB_FBPA_FALCON_MONITOR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FALCON_MONITOR_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_FALCON_MONITOR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FALCON_CTRL_VER 0x009A0064 /* R--4R */ #define NV_PFB_FBPA_FALCON_CTRL_VER__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FALCON_CTRL_VER_DEV 7:0 /* R-IVF */ #define NV_PFB_FBPA_FALCON_CTRL_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FALCON_CTRL_VER_ECO 15:8 /* R-IVF */ #define NV_PFB_FBPA_FALCON_CTRL_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FALCON_CTRL_VER_MINOR 23:16 /* R-IVF */ #define NV_PFB_FBPA_FALCON_CTRL_VER_MINOR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FALCON_CTRL_VER_MAJOR 31:24 /* R-IVF */ #define NV_PFB_FBPA_FALCON_CTRL_VER_MAJOR_INIT 0x00000004 /* R-I-V */ #define NV_PFB_FBPA_CFG_PWRD 0x009A0060 /* RW-4R */ #define NV_PFB_FBPA_CFG_PWRD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_80 0x00000014 /* RW--V */ #define NV_PFB_FBPA_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_120 0x0000001F /* RW--V */ #define NV_PFB_FBPA_CFG_PWRD_RCVR_PWRD_DLY 8:5 /* RWIVF */ #define NV_PFB_FBPA_CFG_PWRD_RCVR_PWRD_DLY_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_CFG_PWRD_BLCG_USE_TRAINING_IDLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_CFG_PWRD_BLCG_USE_TRAINING_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG_PWRD_BLCG_USE_TRAINING_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0 0x009A0080 /* RW-4R */ #define NV_PFB_FBPA_DEBUG_0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_0_MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_MRS_256 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_MRS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_PERIODIC_QRST 5:5 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_PERIODIC_QRST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_PERIODIC_QRST_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_SPARE0 8:8 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_ODT_PIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_ODT_PIN_CMD 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_ODT_PIN_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_ODT_PIN_DEBUG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_ODT_MODE 14:14 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_ODT_MODE_WRITE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_ODT_MODE_NOTREAD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_USE_CFG0_BL8_HBM 15:15 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_USE_CFG0_BL8_HBM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_USE_CFG0_BL8_HBM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_BL16EDC_SET 16:16 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_BL16EDC_SET_EVEN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_BL16EDC_SET_ODD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_WFT_IDLE 17:17 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_WFT_IDLE_NEW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_WFT_IDLE_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_FB_IDLE_NOPBR 18:18 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_FB_IDLE_NOPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_FB_IDLE_NOPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HANDSHAKE 19:19 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HANDSHAKE_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HANDSHAKE_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_FORCE_FULL_MEMREF 20:20 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_FORCE_FULL_MEMREF_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_FORCE_FULL_MEMREF_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_R2P_BL_ADJUST 21:21 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_R2P_BL_ADJUST_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_R2P_BL_ADJUST_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_POST_SP_TR 22:22 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_POST_SP_TR_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_POST_SP_TR_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_TOGGLE_FIX 23:23 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_TOGGLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_TOGGLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HWACPDIDLE_FIX 24:24 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HWACPDIDLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DISABLE_HWACPDIDLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_MODE 25:25 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_MODE_SDR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_MODE_DDR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR 26:26 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_PRI_REG_UPDATE_EXT 27:27 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_PRI_REG_UPDATE_EXT_15 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_PRI_REG_UPDATE_EXT_31 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_REFCFG_REQ_PENDING 28:28 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_REFCFG_REQ_PENDING_FIXED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_REFCFG_REQ_PENDING_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_BECS_ACK 29:29 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_BECS_ACK_LEVEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_BECS_ACK_PULSE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_DRAM_ACK 30:30 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_DRAM_ACK_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_DRAM_ACK_IDLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_0_TREFI_UPDATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_0_TREFI_UPDATE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_0_TREFI_UPDATE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_1 0x009A0084 /* RW-4R */ #define NV_PFB_FBPA_DEBUG_1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_1_L2_ECC 0:0 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_1_L2_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_1_L2_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DEBUG_2 0x009A2340 /* R--4R */ #define NV_PFB_FBPA_DEBUG_2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_2_XBAR_ASR_OK 0:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_2_XBAR_ASR_OK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_2_XBAR_ASR_WAKEUP 1:1 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_2_XBAR_ASR_WAKEUP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_2_STOP_FB_REQ 2:2 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_2_STOP_FB_REQ_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_2_STOP_FB_ACK 3:3 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_2_STOP_FB_ACK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_SUBPIDLE(i) (0x009A2344+(i)*4) /* R--4A */ #define NV_PFB_FBPA_DEBUG_SUBPIDLE__SIZE_1 2 /* */ #define NV_PFB_FBPA_DEBUG_SUBPIDLE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_SUBPIDLE_IDLES 27:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_SUBPIDLE_IDLES_INIT 0x0FFFFFFF /* R-I-V */ #define NV_PFB_FBPA_DEBUG_PAIDLE 0x009A234C /* R--4R */ #define NV_PFB_FBPA_DEBUG_PAIDLE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_PAIDLE_IDLES 21:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_PAIDLE_IDLES_INIT 0x003FFFFF /* R-I-V */ #define NV_PFB_FBPA_DEBUG_CTRL_0 0x009A2350 /* RW-4R */ #define NV_PFB_FBPA_DEBUG_CTRL_0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_CTRL_0_EN_COUNT 0:0 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_0_EN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_CTRL_0_CLR_COUNT 8:8 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_0_CLR_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_CTRL_1 0x009A2354 /* RW-4R */ #define NV_PFB_FBPA_DEBUG_CTRL_1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_0 1:0 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_1 9:8 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_2 17:16 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_3 25:24 /* RWIVF */ #define NV_PFB_FBPA_DEBUG_CTRL_1_SEL_3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_BASE 0x009A2358 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_BASE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_BASE 0x009A235C /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_BASE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_0 0x009A2360 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_0 0x009A2364 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_1 0x009A2368 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_1 0x009A236C /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_2 0x009A2370 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_2 0x009A2374 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_3 0x009A2378 /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_LO_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_3 0x009A237C /* R--4R */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DEBUG_COUNT_HI_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_ROW_REMAP 0x009A01DC /* R--4R */ #define NV_PFB_FBPA_ROW_REMAP__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ROW_REMAP_ENABLE 0:0 /* R-IVF */ #define NV_PFB_FBPA_ROW_REMAP_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_ROW_REMAP_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_ROW_REMAP_RD(i) (0x009A01F0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ROW_REMAP_RD__SIZE_1 2 /* */ #define NV_PFB_FBPA_ROW_REMAP_RD_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_ENTRY_VLD 8:8 /* R-IVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_ENTRY_VLD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_ROW 25:9 /* R-IVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_ROW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_RD_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_RD_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR(i) (0x009A01F8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ROW_REMAP_WR__SIZE_1 2 /* */ #define NV_PFB_FBPA_ROW_REMAP_WR__PRIV_LEVEL_MASK 0x009A000C /* */ #define NV_PFB_FBPA_ROW_REMAP_WR_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR_ROW 25:9 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ROW_REMAP_WR_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_ROW_REMAP_WR_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD 0x009A0090 /* RW-4R */ #define NV_PFB_FBPA_TESTCMD__PRIV_LEVEL_MASK 0x009A014C /* */ #define NV_PFB_FBPA_TESTCMD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LPDDR4_SELF_REF_ENTRY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LPDDR4_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CKE_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0 1:1 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_CS0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1 2:2 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_CS1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_CS1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CS1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS 3:3 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_RAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS 4:4 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_CAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_CAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE 5:5 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_WE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_HBM_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_WE_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES 6:6 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_RES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_RES_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4 7:7 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_BANK_4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_4_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK 11:8 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR6_SELF_REF_ENTRY1 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR6_SELF_REF_ENTRY2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TESTCMD_BANK_DDR6_SELF_REF_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR 25:12 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER 28:26 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_ADR_UPPER_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO 30:30 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_GO_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD 31:31 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_HOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_HOLD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT 0x009A0094 /* RW-4R */ #define NV_PFB_FBPA_TESTCMD_EXT__PRIV_LEVEL_MASK 0x009A014C /* */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT 0:0 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0 1:1 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1 2:2 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ADR_DRAM1 10:3 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_ADR_DRAM1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DEBUG 14:14 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_DEBUG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ODT 15:15 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_ODT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ODT_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_RW_CMD 16:16 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_RW_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_MRS_CMD 17:17 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_MRS_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DR_CMD 18:18 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_DR_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_4CK_CMD 19:19 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_4CK_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_LAM_CMD 20:20 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_LAM_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_CMD 21:21 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_SID 25:24 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_SID_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1 0x009A0154 /* RW-4R */ #define NV_PFB_FBPA_TESTCMD_EXT_1__PRIV_LEVEL_MASK 0x009A014C /* */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR 23:0 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_ENTRY 0x00018018 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_EXIT 0x00014014 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0 27:27 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1 28:28 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR 29:29 /* RWIVF */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0 0x009A00A0 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1 0x009A00A4 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2 0x009A00A8 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3 0x009A00AC /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0 0x009A00B0 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1 0x009A00B4 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2 0x009A00B8 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3 0x009A00BC /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI 0x009A00C0 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_DBI__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_DBI_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC 0x009A00C8 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_ECC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_ECC_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_SWIZZLE_BYTE 0x009A00C4 /* RW-4R */ #define NV_PFB_FBPA_SWIZZLE_BYTE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE1 3:2 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE2 5:4 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE3 7:6 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE0 9:8 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE1 11:10 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE2 13:12 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE3 15:14 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCK01 17:16 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCKB01 19:18 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCK23 21:20 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCKB23 23:22 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP0_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCK01 25:24 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCKB01 27:26 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCK23 29:28 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCKB23 31:30 /* RWIVF */ #define NV_PFB_FBPA_SWIZZLE_BYTE_SUBP1_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_PM 0x009A0100 /* RW-4R */ #define NV_PFB_FBPA_PM__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_PM_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_PM_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC0 0x00000003 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT0 0x00000005 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT1 0x00000006 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ0 0x00000007 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ2 0x00000009 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC2 0x0000000B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ3 0x00000010 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ4 0x00000011 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ5 0x00000012 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC4 0x00000013 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT4 0x00000015 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT5 0x00000016 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ4 0x00000017 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ6 0x00000019 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRTYREQ7 0x0000001A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC6 0x0000001B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SLC7 0x0000001C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT6 0x0000001D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDAT7 0x0000001E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ6 0x0000001F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READREQ7 0x00000020 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_SUBP0 0x00000021 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_SUBP1 0x00000022 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_CH0_SUBP0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_CH0_SUBP1 0x00000024 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_CH1_SUBP0 0x00000025 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_ACT_CH1_SUBP1 0x00000026 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_BANK_ACT_SUBP0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_BANK_ACT_SUBP1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_NO_ACT_SUBP0 0x00000029 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_NO_ACT_SUBP1 0x0000002A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP0 0x0000002B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP1 0x0000002C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BANKQ_EMPTY_SUBP0 0x0000002D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BANKQ_EMPTY_SUBP1 0x0000002E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BA_OUTPUT 0x0000002F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BA_SIGS 0x00000030 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_CKG0 0x00000031 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_CKG1 0x00000032 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRARB_SUBP0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DIRARB_SUBP1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_BANKS_SUBP0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_BANKS_SUBP1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_EXTRA_SUBP0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_EXTRA_SUBP1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RWALL 0x00000039 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_SUBP0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_SUBP1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_CH0_SUBP0 0x0000003C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_CH0_SUBP1 0x0000003D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_CH1_SUBP0 0x0000003E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RW_CH1_SUBP1 0x0000003F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_SUBP0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_SUBP1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_CH0_SUBP0 0x00000042 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_CH0_SUBP1 0x00000043 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_CH1_SUBP0 0x00000044 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_CH1_SUBP1 0x00000045 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_CH0_SUBP0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_CH0_SUBP1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_CH1_SUBP0 0x00000048 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_CH1_SUBP1 0x00000049 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_PART2_SUBP0 0x0000004A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_PART2_SUBP1 0x0000004B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_PP_SUBP0 0x0000004C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_WAIT_PP_SUBP1 0x0000004D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ECC_CH0_SUBP0 0x0000004E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ECC_CH0_SUBP1 0x0000004F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ECC_CH1_SUBP0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ECC_CH1_SUBP1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_FT_IDLE_SUBP0 0x00000052 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_FT_IDLE_SUBP1 0x00000053 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE 0x00000054 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_CH0_SUBP0 0x00000055 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_CH0_SUBP1 0x00000056 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_CH1_SUBP0 0x00000057 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_CH1_SUBP1 0x00000058 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SUBP0 0x00000059 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_IDLE_SUBP1 0x0000005A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_INFLIGHT_READ_COUNT 0x0000005B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_INFLIGHT_READ_COUNT_VC0 0x0000005C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_INFLIGHT_READ_COUNT_VC1 0x0000005D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_INFLIGHT_READ_COUNT_VC2 0x0000005E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_INFLIGHT_WRITE_COUNT 0x0000005F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_OUT_READS 0x00000060 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_OUT_WRITES 0x00000061 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_PENDING_REFRESH_SUBP0 0x00000062 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_PENDING_REFRESH_SUBP1 0x00000063 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_PART2_SUBP0 0x00000064 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_PART2_SUBP1 0x00000065 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_SUBP0 0x00000066 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_SUBP1 0x00000067 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP0 0x00000068 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP1 0x00000069 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP0 0x0000006A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP1 0x0000006B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP0 0x0000006C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP1 0x0000006D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READARB_SUBP0 0x0000006E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READARB_SUBP1 0x0000006F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_READARB_VC 0x00000070 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_REFSB_SUBP0 0x00000071 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_REFSB_SUBP1 0x00000072 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT0_PART2_SUBP0 0x00000073 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT0_PART2_SUBP1 0x00000074 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT0_SUBP0 0x00000075 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT0_SUBP1 0x00000076 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT1_PART2_SUBP0 0x00000077 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT1_PART2_SUBP1 0x00000078 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT1_SUBP0 0x00000079 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RFT1_SUBP1 0x0000007A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_STAT_CH0_SUBP0 0x0000007B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_STAT_CH0_SUBP1 0x0000007C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_STAT_CH1_SUBP0 0x0000007D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_STAT_CH1_SUBP1 0x0000007E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_SINGLE_PASS_SUBP0 0x0000007F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_SINGLE_PASS_SUBP1 0x00000080 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000081 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000082 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_SUBP01_TRAFFIC 0x00000083 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_SUBP01_TRAFFIC_CH0 0x00000084 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_SUBP01_TRAFFIC_CH1 0x00000085 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WFT0_SUBP0 0x00000086 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WFT0_SUBP1 0x00000087 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WFT1_SUBP0 0x00000088 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WFT1_SUBP1 0x00000089 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP0 0x0000008A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP1 0x0000008B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRBANKQ_SUBP0 0x0000008C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRBANKQ_SUBP1 0x0000008D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEARB_SUBP0 0x0000008E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEARB_SUBP1 0x0000008F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_UTIL_SUBP0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_UTIL_SUBP1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RCMD_CH0_SUBP0 0x00000092 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RCMD_CH0_SUBP1 0x00000093 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RCMD_CH1_SUBP0 0x00000094 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_DRAMC_RCMD_CH1_SUBP1 0x00000095 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_SUBP0 0x00000096 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_SUBP1 0x00000097 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_CH0_SUBP0 0x00000098 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_CH0_SUBP1 0x00000099 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_CH1_SUBP0 0x0000009A /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BUCKET_CH1_SUBP1 0x0000009B /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ISO_TRACKING0_SUBP0 0x0000009C /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ISO_TRACKING0_SUBP1 0x0000009D /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ISO_TRACKING1_SUBP0 0x0000009E /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ISO_TRACKING1_SUBP1 0x0000009F /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC0_SUBP0 0x000000A0 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC0_SUBP1 0x000000A1 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC1_SUBP0 0x000000A2 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC1_SUBP1 0x000000A3 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC2_SUBP0 0x000000A4 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_BW_TRACKING_VC2_SUBP1 0x000000A5 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_REQ_FIFO_SG0 0x000000A6 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_REQ_FIFO_SG1 0x000000A7 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_REQ_FIFO_SG2 0x000000A8 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_WRITEPULL_REQ_FIFO_SG3 0x000000A9 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_RETURN_FIFO_SG0 0x000000AA /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_RETURN_FIFO_SG1 0x000000AB /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_RETURN_FIFO_SG2 0x000000AC /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_RR_RETURN_FIFO_SG3 0x000000AD /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR0_SUBP0 0x000000AE /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR0_SUBP1 0x000000AF /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR1_SUBP0 0x000000B0 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR1_SUBP1 0x000000B1 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR2_SUBP0 0x000000B2 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR2_SUBP1 0x000000B3 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR3_SUBP0 0x000000B4 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR3_SUBP1 0x000000B5 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR4_SUBP0 0x000000B6 /* RW--V */ #define NV_PFB_FBPA_PM_SELECT_ACPD_ASR4_SUBP1 0x000000B7 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP(i) (0x009A01E0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_SUBP__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_SUBP__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_SUBP_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_PM_SUBP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_SUBP_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_PM_SUBP_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_ACT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_ACT_CH0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_ACT_CH1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_BANK_ACT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_NO_ACT 0x00000005 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACTARB_NUM_RW_BANKS 0x00000006 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BANKQ_EMPTY 0x00000007 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DIRARB 0x00000008 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_CH0 0x0000000A /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_CH1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_BANKS 0x0000000C /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_EXTRA 0x0000000D /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_RW 0x0000000E /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_RW_CH0 0x0000000F /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_RW_CH1 0x00000010 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_WAIT_CH0 0x00000011 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_WAIT_CH1 0x00000012 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_WAIT_PART2 0x00000013 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_WAIT_PP 0x00000014 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ECC_CH0 0x00000015 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ECC_CH1 0x00000016 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_FT_IDLE 0x00000017 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_IDLE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_IDLE_CH0 0x00000019 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_IDLE_CH1 0x0000001A /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_PENDING_REFRESH 0x0000001B /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RDBANKQ 0x0000001C /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RDBANKQ_PART2 0x0000001D /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RDBANKQ_VC0_REQ_FIFO 0x0000001E /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RDBANKQ_VC1_REQ_FIFO 0x0000001F /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RDBANKQ_VC2_REQ_FIFO 0x00000020 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_READARB 0x00000021 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_REFSB 0x00000022 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RFT0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RFT0_PART2 0x00000024 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RFT1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RFT1_PART2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RR_STAT_CH0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_RR_STAT_CH1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_SINGLE_PASS 0x00000029 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WFT0 0x0000002A /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WFT1 0x0000002B /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WRBANKQ 0x0000002C /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WRBANKQ_REQ_FIFO 0x0000002D /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WRITEARB 0x0000002E /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_WRITEPULL_UTIL 0x0000002F /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_RCMD_CH0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_DRAMC_RCMD_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BUCKET 0x00000032 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BUCKET_CH0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BUCKET_CH1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ISO_TRACKING0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ISO_TRACKING1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BW_TRACKING_VC0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BW_TRACKING_VC1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_BW_TRACKING_VC2 0x00000039 /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACPD_ASR0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACPD_ASR1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACPD_ASR2 0x0000003C /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACPD_ASR3 0x0000003D /* RW--V */ #define NV_PFB_FBPA_PM_SUBP_SELECT_ACPD_ASR4 0x0000003E /* RW--V */ #define NV_PFB_FBPA_PM_CAPTURE(i) (0x009A0180+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_CAPTURE__SIZE_1 12 /* */ #define NV_PFB_FBPA_PM_CAPTURE__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_CAPTURE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_CAPTURE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_CAPTURE_HI(i) (0x009A2500+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_CAPTURE_HI__SIZE_1 12 /* */ #define NV_PFB_FBPA_PM_CAPTURE_HI__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_CAPTURE_HI_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_CAPTURE_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_CAPTURE_WINDOW(i) (0x009A01D0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_CAPTURE_WINDOW__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_CAPTURE_WINDOW__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_CAPTURE_WINDOW_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_CAPTURE_WINDOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_CAPTURE_CTL 0x009A01D8 /* RW-4R */ #define NV_PFB_FBPA_PM_CAPTURE_CTL__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_CAPTURE_CTL_INVERT 0:0 /* RWIVF */ #define NV_PFB_FBPA_PM_CAPTURE_CTL_INVERT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_BUCKET(i) (0x009A2530+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_BUCKET__SIZE_1 11 /* */ #define NV_PFB_FBPA_PM_BUCKET__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_BUCKET_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_BUCKET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_BUCKET_CTL 0x009A255C /* RW-4R */ #define NV_PFB_FBPA_PM_BUCKET_CTL__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE 2:0 /* RWIVF */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE_RD_CMD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE_WR_CMD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE_COL_CMD 0x00000002 /* RW--V */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE_ANY_CMD 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_PM_BUCKET_CTL_TYPE_ISO_TRACKING 0x00000004 /* RW--V */ #define NV_PFB_FBPA_PM_CTL 0x009A2560 /* RW-4R */ #define NV_PFB_FBPA_PM_CTL__PRIV_LEVEL_MASK 0x009A01B0 /* */ #define NV_PFB_FBPA_PM_CTL_ISO_SUBID_MSB_INDEX 3:0 /* RWIVF */ #define NV_PFB_FBPA_PM_CTL_ISO_SUBID_MSB_INDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PM_CTL_ISO_SUBID_MSB_INDEX_MAX 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_REG_CTL 0x009A2564 /* RW-4R */ #define NV_PFB_FBPA_REG_CTL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REG_CTL_FBIO_NOACK 0:0 /* RWIVF */ #define NV_PFB_FBPA_REG_CTL_FBIO_NOACK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REG_CTL_FBIO_NOACK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_ASR_NUM(i) (0x009A0110+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_ASR_NUM__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASR_NUM__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASR_NUM_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_ASR_NUM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_ASR_CYCCNT(i) (0x009A0118+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_ASR_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASR_CYCCNT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASR_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_ASR_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_ASR_MAXCYC(i) (0x009A0120+(i)*4) /* R--4A */ #define NV_PFB_FBPA_PM_ASR_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASR_MAXCYC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASR_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_PM_ASR_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_PM_ASR_MINCYC(i) (0x009A0128+(i)*4) /* R--4A */ #define NV_PFB_FBPA_PM_ASR_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASR_MINCYC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASR_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_PM_ASR_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_PM_ASRSTALL_CYCCNT(i) (0x009A0130+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_CYCCNT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_PM_ASRSTALL_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PM_ASRSTALL_MAXCYC(i) (0x009A0138+(i)*4) /* R--4A */ #define NV_PFB_FBPA_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_MAXCYC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_PM_ASRSTALL_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_PM_ASRSTALL_MINCYC(i) (0x009A0140+(i)*4) /* R--4A */ #define NV_PFB_FBPA_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_MINCYC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PM_ASRSTALL_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_PM_ASRSTALL_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_ASRCTRL_NONISO 0x009A0150 /* RW-4R */ #define NV_PFB_FBPA_ASRCTRL_NONISO__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASRCTRL_NONISO_THRESHOLD 31:0 /* RWIVF */ #define NV_PFB_FBPA_ASRCTRL_NONISO_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MISC_CTRL 0x009A0160 /* RW-4R */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD 2:0 /* RWIVF */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_10 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_11 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_12 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_13 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_14 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_15 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_PERIOD_16 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_EN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_CTRL_INTERVAL_TIMER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_NUM_ACTIVE_FBPS 0x009A0164 /* RW-4R */ #define NV_PFB_FBPA_NUM_ACTIVE_FBPS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_NUM_ACTIVE_FBPS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_NUM_ACTIVE_LTCS 0x009A016C /* RW-4R */ #define NV_PFB_FBPA_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_NUM_ACTIVE_LTCS_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WPRE0 0x009A0174 /* RW-4R */ #define NV_PFB_FBPA_WPRE0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPRE0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPRE0_DQ0_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_WPRE0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_WPRE0_DQ1_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_WPRE0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_WPRE0_DQ2_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_WPRE0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_WPRE0_DQ3_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_WPRE1 0x009A0178 /* RW-4R */ #define NV_PFB_FBPA_WPRE1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPRE1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPRE1_DQ4_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_WPRE1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_WPRE1_DQ5_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_WPRE1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_WPRE1_DQ6_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_WPRE1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_WPRE1_DQ7_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_WPRE2 0x009A017C /* RW-4R */ #define NV_PFB_FBPA_WPRE2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPRE2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPRE2_DBI_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_WPRE2_TR_PATTERN 15:8 /* RWIVF */ #define NV_PFB_FBPA_WPRE2_TR_PATTERN_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST0 0x009A01B8 /* RW-4R */ #define NV_PFB_FBPA_WPOST0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPOST0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPOST0_DQ0_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_WPOST0_DQ1_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_WPOST0_DQ2_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_WPOST0_DQ3_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST1 0x009A01BC /* RW-4R */ #define NV_PFB_FBPA_WPOST1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPOST1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPOST1_DQ4_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_WPOST1_DQ5_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_WPOST1_DQ6_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_WPOST1_DQ7_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_WPOST2 0x009A01C0 /* RW-4R */ #define NV_PFB_FBPA_WPOST2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WPOST2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_WPOST2_DBI_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_CFG0 0x009A0200 /* RW-4R */ #define NV_PFB_FBPA_CFG0__PRIV_LEVEL_MASK 0x009A2250 /* */ #define NV_PFB_FBPA_CFG0_BL 1:0 /* RWIVF */ #define NV_PFB_FBPA_CFG0_BL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_BL_BL4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_BL_BL8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG0_BL_BL16 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CFG0_EXTBANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_CFG0_EXTBANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_EXTBANK_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_EXTBANK__PROD_C_SINGLE_SIDED_MEM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_EXTBANK__PROD_C_DUAL_SIDED_MEM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_X8 4:4 /* RWIVF */ #define NV_PFB_FBPA_CFG0_X8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_X8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_CA_RETURN_TO_ZERO 5:5 /* RWIVF */ #define NV_PFB_FBPA_CFG0_CA_RETURN_TO_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_CA_RETURN_TO_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_HBM_CMD_PARITY_OVERRIDE 6:6 /* RWIVF */ #define NV_PFB_FBPA_CFG0_HBM_CMD_PARITY_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_HBM_CMD_PARITY_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_EDC_RATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_CFG0_EDC_RATE_HALF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_EDC_RATE_FULL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_GAPLESS_WTR 8:8 /* RWIVF */ #define NV_PFB_FBPA_CFG0_GAPLESS_WTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_GAPLESS_WTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_DRAM_ACPD 11:11 /* RWIVF */ #define NV_PFB_FBPA_CFG0_DRAM_ACPD_NO_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_DRAM_ACPD_ACTIVE_POWERDOWN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ATR 12:12 /* RWIVF */ #define NV_PFB_FBPA_CFG0_AUTO_ATR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_AUTO_ATR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ATR__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ATR__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ATR__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_DATA_SCRAMBLE 13:13 /* RWIVF */ #define NV_PFB_FBPA_CFG0_DATA_SCRAMBLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_DATA_SCRAMBLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_SYNC 14:14 /* RWIVF */ #define NV_PFB_FBPA_CFG0_AUTO_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_AUTO_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_LOW_POWER 15:15 /* RWIVF */ #define NV_PFB_FBPA_CFG0_LOW_POWER_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_LOW_POWER_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_ABI 16:16 /* RWIVF */ #define NV_PFB_FBPA_CFG0_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_BURST_LENGTH 17:17 /* RWIVF */ #define NV_PFB_FBPA_CFG0_BURST_LENGTH_4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_BURST_LENGTH_8 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG0_DM_ON_ADR 18:18 /* RWIVF */ #define NV_PFB_FBPA_CFG0_DM_ON_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_DM_ON_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_TIMING_UNIT 19:19 /* RWIVF */ #define NV_PFB_FBPA_CFG0_TIMING_UNIT_DRAMCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_TIMING_UNIT_DRAMDIV2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_CMD_PARITY 20:20 /* RWIVF */ #define NV_PFB_FBPA_CFG0_CMD_PARITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_CMD_PARITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG0_AUTO_ODT 21:21 /* RWIVF */ #define NV_PFB_FBPA_CFG0_AUTO_ODT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_AUTO_ODT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ODT__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ODT__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_ODT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_CLAMSHELL 22:22 /* RWIVF */ #define NV_PFB_FBPA_CFG0_CLAMSHELL_X32 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_CLAMSHELL_X16 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_EDC_EARLY_VALUE 23:23 /* RWIVF */ #define NV_PFB_FBPA_CFG0_EDC_EARLY_VALUE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG0_EDC_EARLY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_BG_8 24:24 /* RWIVF */ #define NV_PFB_FBPA_CFG0_BG_8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_BG_8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_PRE 25:25 /* RWIVF */ #define NV_PFB_FBPA_CFG0_AUTO_PRE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_AUTO_PRE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG0_SAME_QUSE_TWO_RANKS 26:26 /* RWIVF */ #define NV_PFB_FBPA_CFG0_SAME_QUSE_TWO_RANKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG0_SAME_QUSE_TWO_RANKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG0_RDEDC 27:27 /* RWIVF */ #define NV_PFB_FBPA_CFG0_RDEDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_RDEDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_WREDC 28:28 /* RWIVF */ #define NV_PFB_FBPA_CFG0_WREDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_WREDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_REPLAY 29:29 /* RWIVF */ #define NV_PFB_FBPA_CFG0_REPLAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_REPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_MS01_ECC 30:30 /* RWIVF */ #define NV_PFB_FBPA_CFG0_MS01_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_MS01_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG0_DRAM_ACK 31:31 /* RWIVF */ #define NV_PFB_FBPA_CFG0_DRAM_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG0_DRAM_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1 0x009A0204 /* RW-4R */ #define NV_PFB_FBPA_CFG1__PRIV_LEVEL_MASK 0x009A0148 /* */ #define NV_PFB_FBPA_CFG1_SUBP 1:0 /* RWIVF */ #define NV_PFB_FBPA_CFG1_SUBP_256B 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_SUBP_512B 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_SUBP_1KB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_SUBP_2KB 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CFG1_AP 6:4 /* RWIVF */ #define NV_PFB_FBPA_CFG1_AP_A8 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_AP_A9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_AP_A10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_AP_A11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CFG1_AP_A12 0x00000004 /* RW--V */ #define NV_PFB_FBPA_CFG1_AP_A13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CFG1_STACK 9:7 /* RWIVF */ #define NV_PFB_FBPA_CFG1_STACK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_STACK_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_STACK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_COL 15:12 /* RWIVF */ #define NV_PFB_FBPA_CFG1_COL_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_CFG1_COL_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_CFG1_COL_15 0x0000000F /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA 19:16 /* RWIVF */ #define NV_PFB_FBPA_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB 23:20 /* RWIVF */ #define NV_PFB_FBPA_CFG1_ROWB_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_CFG1_ROWB_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CFG1_ROWB_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_CFG1_BANK 25:24 /* RWIVF */ #define NV_PFB_FBPA_CFG1_BANK_2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CFG1_BANK_3 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CFG1_BANK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_BG_8_OVR 26:26 /* RWIVF */ #define NV_PFB_FBPA_CFG1_BG_8_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_BG_8_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_BG 28:27 /* RWIVF */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_ROW_BG 30:29 /* RWIVF */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_ROW_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_ROW_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CFG1_NUM_BANKS_PER_ROW_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CSTATUS 0x009A020C /* R--4R */ #define NV_PFB_FBPA_CSTATUS__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CSTATUS_RAMAMOUNT 16:0 /* R-IVF */ #define NV_PFB_FBPA_CSTATUS_RAMAMOUNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CSTATUS_OVERRIDE 0x009A257C /* RW-4R */ #define NV_PFB_FBPA_CSTATUS_OVERRIDE__PRIV_LEVEL_MASK 0x009A2578 /* */ #define NV_PFB_FBPA_CSTATUS_OVERRIDE_RAMAMOUNT 16:0 /* RWIVF */ #define NV_PFB_FBPA_CSTATUS_OVERRIDE_RAMAMOUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL 0x009A0210 /* RW-4R */ #define NV_PFB_FBPA_REFCTRL__PRIV_LEVEL_MASK 0x009A2250 /* */ #define NV_PFB_FBPA_REFCTRL_PUT 6:0 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL_PUT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL_GET 14:8 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL_GET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL_RESET 16:16 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL_RESET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL_RESET_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFCTRL_VALID 31:31 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL_VALID_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL_VALID_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ 0x009A0214 /* RW-4R */ #define NV_PFB_FBPA_ZQ__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ZQ_CL_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_ZQ_CL_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_CS_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_ZQ_CS_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_CL_PERIODIC 2:2 /* RWIVF */ #define NV_PFB_FBPA_ZQ_CL_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_CL_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_CS_PERIODIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_ZQ_CS_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_CS_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_PERIODIC_CH 4:4 /* RWIVF */ #define NV_PFB_FBPA_ZQ_PERIODIC_CH_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_PERIODIC_CH_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_PERIODIC_RANK 5:5 /* RWIVF */ #define NV_PFB_FBPA_ZQ_PERIODIC_RANK_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_PERIODIC_RANK_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_ZQ_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ZQ_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_ZQ_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_ZQ_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ZQ_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_ZQ_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_ZQ_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ZQ_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ZQ_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ZQ_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_PIN 0x009A0218 /* RW-4R */ #define NV_PFB_FBPA_PIN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PIN_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PIN_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PIN_DQM 4:4 /* RWIVF */ #define NV_PFB_FBPA_PIN_DQM_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PIN_DQM_INACTIVE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PIN_RESET 8:8 /* RWIVF */ #define NV_PFB_FBPA_PIN_RESET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PIN_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PIN_CKE_POLARITY 12:12 /* RWIVF */ #define NV_PFB_FBPA_PIN_CKE_POLARITY_ACTIVE_HI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PIN_CKE_POLARITY_ACTIVE_LO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PIN_A0 21:20 /* RWIVF */ #define NV_PFB_FBPA_PIN_A0_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PIN_A0_LOW 0x00000002 /* RW--V */ #define NV_PFB_FBPA_PIN_A0_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_PIN_WDQS_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_PIN_WDQS_MODE_RETURN_TO_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PIN_WDQS_MODE_RETURN_TO_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_PIN_WDQS_MODE_FREERUNNING 0x00000002 /* RW--V */ #define NV_PFB_FBPA_PIN_DBI 31:28 /* RWIVF */ #define NV_PFB_FBPA_PIN_DBI_X8 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_PAD 0x009A021C /* RW-4R */ #define NV_PFB_FBPA_PAD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PAD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_CKE__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_CMD27 1:1 /* RWIVF */ #define NV_PFB_FBPA_PAD_CMD27_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_CMD27_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_CMD28 2:2 /* RWIVF */ #define NV_PFB_FBPA_PAD_CMD28_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_CMD28_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_CHANNEL_PULLDN 8:8 /* RWIVF */ #define NV_PFB_FBPA_PAD_CHANNEL_PULLDN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_CHANNEL_PULLDN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_INPUT_DRIVER_CTRL 16:16 /* RWIVF */ #define NV_PFB_FBPA_PAD_INPUT_DRIVER_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_INPUT_DRIVER_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PAD_DBI 20:20 /* RWIVF */ #define NV_PFB_FBPA_PAD_DBI_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PAD_DBI_OVERRIDE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING 0x009A03F4 /* RW-4R */ #define NV_PFB_FBPA_TIMING__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING_ACT2PDEN 0:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING_ACT2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING_ACT2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING_PCHG2PDEN 1:1 /* RWIVF */ #define NV_PFB_FBPA_TIMING_PCHG2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING_PCHG2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING_AR2PDEN 2:2 /* RWIVF */ #define NV_PFB_FBPA_TIMING_AR2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING_AR2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING_DQRQPOP 3:3 /* RWIVF */ #define NV_PFB_FBPA_TIMING_DQRQPOP_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING_DQRQPOP_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING_NOP2MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_TIMING_NOP2MRS_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING_NOP2MRS_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING0 0x009A0220 /* RW-4R */ #define NV_PFB_FBPA_TIMING0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING0_RC 8:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_TIMING0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING0_RC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_TIMING0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_TIMING0_RFC 22:12 /* RWIVF */ #define NV_PFB_FBPA_TIMING0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_TIMING0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING0_RFC_MAX 0x000003FF /* RW--V */ #define NV_PFB_FBPA_TIMING0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_TIMING0_RAS 31:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_TIMING0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING0_RAS_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_TIMING1 0x009A0224 /* RW-4R */ #define NV_PFB_FBPA_TIMING1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING1_R2W 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING1_R2W_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2W_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_TIMING1_R2W_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2W_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2W__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2R 14:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING1_W2R_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_TIMING1_W2R_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2R_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2R__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2P 20:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING1_R2P_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING1_R2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2P_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TIMING1_R2P__PROD_C_SAMSUNG_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2P 30:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING1_W2P_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_TIMING1_W2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2P_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TIMING1_W2P__PROD_C_SAMSUNG_DDR3 0x00000012 /* RW--V */ #define NV_PFB_FBPA_TIMING2 0x009A0228 /* RW-4R */ #define NV_PFB_FBPA_TIMING2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING2_RD_RCD 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING2_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_TIMING2_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_RD_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING2_RD_RCD__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_TIMING2_WR_RCD 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING2_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING2_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WR_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING2_WR_RCD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TIMING2_RRD 22:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING2_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING2_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_RRD_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TIMING2_RRD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV 28:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING2_WDV_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TIMING2_WDV_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV__PROD_C_WL1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV__PROD_C_WL6 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TIMING2_WDV__PROD_C_SAMSUNG_DDR3 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TIMING3 0x009A022C /* RW-4R */ #define NV_PFB_FBPA_TIMING3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING3_QUSE 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING3_QUSE_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_TIMING3_QUSE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING3_QUSE_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING3_QUSE__PROD_C_CL11 0x0000000B /* RW--V */ #define NV_PFB_FBPA_TIMING3_QUSE__PROD_C_SAMSUNG_DDR3 0x0000000B /* RW--V */ #define NV_PFB_FBPA_TIMING3_QRST 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING3_QRST_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING3_QRST_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING3_QRST_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING3_QRST__PROD_C_CL11 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TIMING3_QRST__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TIMING3_QSAFE 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING3_QSAFE_17 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_TIMING3_QSAFE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING3_QSAFE_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TIMING3_RDV 31:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING3_RDV_60 0x0000003C /* RWI-V */ #define NV_PFB_FBPA_TIMING3_RDV_27 0x0000001C /* RW--V */ #define NV_PFB_FBPA_TIMING3_RDV_MIN 0x00000011 /* RW--V */ #define NV_PFB_FBPA_TIMING3_RDV_MAX 0x00000028 /* RW--V */ #define NV_PFB_FBPA_TIMING3_RDV__PROD_C_CL11 0x0000001B /* RW--V */ #define NV_PFB_FBPA_TIMING3_RDV__PROD_C_SAMSUNG_DDR3 0x0000001B /* RW--V */ #define NV_PFB_FBPA_TIMING4 0x009A0230 /* RW-4R */ #define NV_PFB_FBPA_TIMING4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING4_PDEX2WR 5:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING4_PDEX2WR_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TIMING4_PDEX2WR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEX2WR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEX2WR__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEX2RD 13:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING4_PDEX2RD_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TIMING4_PDEX2RD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEX2RD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEX2RD__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX 19:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_FAW 28:20 /* RWIVF */ #define NV_PFB_FBPA_TIMING4_FAW_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_FAW_40 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_TIMING4_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_FAW_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_TIMING4_FAW__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_MSB 30:29 /* RWIVF */ #define NV_PFB_FBPA_TIMING4_PDEN2PDEX_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING5 0x009A0234 /* RW-4R */ #define NV_PFB_FBPA_TIMING5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING5_PCHG2PDEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING5_PCHG2PDEN_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING5_PCHG2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING5_PCHG2PDEN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING5_PCHG2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TIMING5_RW2PDEN 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING5_RW2PDEN_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_TIMING5_RW2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING5_RW2PDEN_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING5_RW2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_TIMING5_ACT2PDEN 22:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING5_ACT2PDEN_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_TIMING5_ACT2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING5_ACT2PDEN_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TIMING5_ACT2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_TIMING5_AR2PDEN 31:23 /* RWIVF */ #define NV_PFB_FBPA_TIMING5_AR2PDEN_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_TIMING5_AR2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING5_AR2PDEN_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_TIMING5_AR2PDEN__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_TIMING6 0x009A0238 /* RW-4R */ #define NV_PFB_FBPA_TIMING6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING6_PPD 4:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING6_PPD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING6_BUS_W2R 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING6_BUS_W2R_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING6_BUS_W2R_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_DRAMC 21:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_DRAMC_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_DRAMC_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO 31:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO_70 0x00000046 /* RWI-V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO_20 0x00000014 /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_TIMING6_CMD2MCIDLE_FBIO_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING7 0x009A023C /* RW-4R */ #define NV_PFB_FBPA_TIMING7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING7_REXT 3:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING7_REXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING7_WEXT 11:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING7_WEXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING7_ATR 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING7_ATR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING7_ATR_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING7_ATR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING7_ATRLEN 28:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING7_ATRLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING7_ATRLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TIMING7_ATRLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING8 0x009A0240 /* RW-4R */ #define NV_PFB_FBPA_TIMING8__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING8_ODT 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING8_ODT_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING8_ODT_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING8_ODT_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING8_ODTLEN 11:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING8_ODTLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING8_ODTLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TIMING8_ODTLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING8_QPOP_OFFSET 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING8_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING8_QPOP_OFFSET_ELEVEN 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_TIMING8_QPOP_OFFSET_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING8_RPRE 27:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING8_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING8_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING8_RPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING8_WPRE 31:28 /* RWIVF */ #define NV_PFB_FBPA_TIMING8_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING8_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING8_WPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING9 0x009A0244 /* RW-4R */ #define NV_PFB_FBPA_TIMING9__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING9_CCDL 3:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING9_CCDL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING9_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TIMING9_CCDL_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING9_CCDS 7:4 /* RWIVF */ #define NV_PFB_FBPA_TIMING9_CCDS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING9_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING9_CCDS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_ADR 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_ADR_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_WCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_WCK_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_WREDC 31:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING9_QPOP_OFFSET_WREDC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING10 0x009A0248 /* RW-4R */ #define NV_PFB_FBPA_TIMING10__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING10_WCK2MRS 3:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_WCK2MRS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_WCK2TR 7:4 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_WCK2TR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_LTLTR 11:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_LTLTR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_LTL7TR 16:12 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_LTL7TR_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_MRD 22:17 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_MRD_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING10_WCK2MRS_MSB2 23:23 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_WCK2MRS_MSB2_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_REFTR 29:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_REFTR_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING10_REFTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING10_REFTR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING10_WCK2TR_MSB 30:30 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_WCK2TR_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING10_WCK2MRS_MSB 31:31 /* RWIVF */ #define NV_PFB_FBPA_TIMING10_WCK2MRS_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING11 0x009A024C /* RW-4R */ #define NV_PFB_FBPA_TIMING11__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING11_ADZ 4:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING11_ADZ_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING11_WTR_RCD 9:5 /* RWIVF */ #define NV_PFB_FBPA_TIMING11_WTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING11_WTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING11_WTR_RCD_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TIMING11_LTR_RCD 14:10 /* RWIVF */ #define NV_PFB_FBPA_TIMING11_LTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING11_LTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING11_LTR_RCD_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING11_LTRTR 20:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING11_LTRTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING11_LTRTR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING11_LTRTR_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TIMING11_KO 30:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING11_KO_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING11_KO_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING11_KO_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING12 0x009A0250 /* RW-4R */ #define NV_PFB_FBPA_TIMING12__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING12_RDCRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING12_RDCRC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TIMING12_CKE 9:4 /* RWIVF */ #define NV_PFB_FBPA_TIMING12_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING12_CKE_5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TIMING12_CKSRE 13:10 /* RWIVF */ #define NV_PFB_FBPA_TIMING12_CKSRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING12_CKSRE_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TIMING12_LOCKPLL 29:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING12_LOCKPLL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING12_LOCKPLL_3000 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_TIMING12_LOCKPLL_MAX 0x00003FFF /* RW--V */ #define NV_PFB_FBPA_TIMING13 0x009A0254 /* RW-4R */ #define NV_PFB_FBPA_TIMING13__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK 4:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK_5 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK_MSB 5:5 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASREX2CLK_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASR2NRD_MSB 6:6 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASR2NRD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX_MSB 7:7 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASR2NRD 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASR2NRD_120 0x00000078 /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASR2NRD_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASR2NRD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASR2NRD__PROD_C_SAMSUNG_DDR3 0x00000078 /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX 31:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX_5K 0x00001388 /* RWI-V */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX_MAX 0x0000FFFF /* RW--V */ #define NV_PFB_FBPA_TIMING13_ASR2ASREX__PROD_C_SAMSUNG_DDR3 0x00004E20 /* RW--V */ #define NV_PFB_FBPA_TIMING14 0x009A0258 /* RW-4R */ #define NV_PFB_FBPA_TIMING14__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING14_ZQCS 6:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING14_ZQCS_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_TIMING14_ZQCL 17:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING14_ZQCL_100 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_TIMING15 0x009A025C /* RW-4R */ #define NV_PFB_FBPA_TIMING15__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING15_RDRET 6:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING15_RDRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TIMING15_WRRET 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING15_WRRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TIMING15_RDINTRP 22:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING15_RDINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING15_WRINTRP 30:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING15_WRINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING16 0x009A0260 /* RW-4R */ #define NV_PFB_FBPA_TIMING16__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING16_RDFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING16_RDFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING16_WRFLUSH 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING16_WRFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING16_RP 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING16_RP_10 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING16_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING16_RP_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TIMING16_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TIMING16_WCK_QRST 27:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING16_WCK_QRST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING17 0x009A0264 /* RW-4R */ #define NV_PFB_FBPA_TIMING17__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING17_RDRET_PRE 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING17_RDRET_PRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING17_WCK2RDWCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING17_WCK2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING17_MRS2RDWCK 31:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING17_MRS2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING18 0x009A0268 /* RW-4R */ #define NV_PFB_FBPA_TIMING18__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING18_WRCRCFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING18_WRCRCFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING18_REXT 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING18_REXT_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING18_QUSE_SETTLE 20:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING18_QUSE_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING18_DLCELL_SETTLE 29:21 /* RWIVF */ #define NV_PFB_FBPA_TIMING18_DLCELL_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING19 0x009A026C /* RW-4R */ #define NV_PFB_FBPA_TIMING19__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING19_QRST_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING19_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING19_QRST_FLUSH 9:5 /* RWIVF */ #define NV_PFB_FBPA_TIMING19_QRST_FLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING19_MPRR 16:10 /* RWIVF */ #define NV_PFB_FBPA_TIMING19_MPRR_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING20 0x009A028C /* RW-4R */ #define NV_PFB_FBPA_TIMING20__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING20_RD_REFRESH 7:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING20_RD_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING20_WR_REFRESH 15:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING20_WR_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TIMING21 0x009A0390 /* RW-4R */ #define NV_PFB_FBPA_TIMING21__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING21_REFSB 0:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING21_REFSB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING21_REFSB_FORCE_FULL 1:1 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_FORCE_FULL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING21_REFSB_FORCE_FULL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING21_REFSB_DUAL_REQUEST 2:2 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_DUAL_REQUEST_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING21_REFSB_DUAL_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING21_REFSB_DELAYED_THRESHOLD 5:3 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_DELAYED_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING21_REFSB_FULL_REF_PERIOD 19:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_FULL_REF_PERIOD_INIT 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_TIMING21_REFSB_DISPATCH_PERIOD 31:22 /* RWIVF */ #define NV_PFB_FBPA_TIMING21_REFSB_DISPATCH_PERIOD_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_TIMING22 0x009A0394 /* RW-4R */ #define NV_PFB_FBPA_TIMING22__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING22_RFCSBA 9:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING22_RFCSBA_INIT 0x00000032 /* RWI-V */ #define NV_PFB_FBPA_TIMING22_RFCSBR 17:10 /* RWIVF */ #define NV_PFB_FBPA_TIMING22_RFCSBR_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TIMING22_RFCSBA_MSB 21:20 /* RWIVF */ #define NV_PFB_FBPA_TIMING22_RFCSBA_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING23 0x009A039C /* RW-4R */ #define NV_PFB_FBPA_TIMING23__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING23_CCDR 3:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING23_CCDR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING23_CCDR_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TIMING23_RD_RANK_SEL_DELAY 10:4 /* RWIVF */ #define NV_PFB_FBPA_TIMING23_RD_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING23_WR_RANK_SEL_DELAY 17:11 /* RWIVF */ #define NV_PFB_FBPA_TIMING23_WR_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING23_WR_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING23_WR_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING23_WR_CCDL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING23_WR_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TIMING23_WR_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_TIMING23_WR_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING23_WR_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TIMING23_WR_CCDS_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TIMING24 0x009A03E0 /* RW-4R */ #define NV_PFB_FBPA_TIMING24__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING24_RRDL 6:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING24_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TIMING24_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING24_RRDL_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TIMING24_CCDMW 14:8 /* RWIVF */ #define NV_PFB_FBPA_TIMING24_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING24_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_TIMING24_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING24_CCDMW_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TIMING24_LPDDR4_RDV_OFFSET 18:15 /* RWIVF */ #define NV_PFB_FBPA_TIMING24_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING24_ABPA 25:20 /* RWIVF */ #define NV_PFB_FBPA_TIMING24_ABPA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING24_XS_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_TIMING24_XS_OFFSET_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TIMING25 0x009A03EC /* RW-4R */ #define NV_PFB_FBPA_TIMING25__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING25_ZQCAL 11:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING25_ZQCAL_1_US 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_TIMING25_MRRW 21:13 /* RWIVF */ #define NV_PFB_FBPA_TIMING25_MRRW_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_TIMING25_MRRWL 30:22 /* RWIVF */ #define NV_PFB_FBPA_TIMING25_MRRWL_256 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_TIMING26 0x009A24E0 /* RW-4R */ #define NV_PFB_FBPA_TIMING26__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING26_RFC_DLR 8:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING26_RFC_DLR_58 0x0000003A /* RWI-V */ #define NV_PFB_FBPA_TIMING26_RFC_DLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TIMING26_RFC_DLR_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_TIMING27 0x009A24E4 /* RW-4R */ #define NV_PFB_FBPA_TIMING27__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING27_REFSR 0:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING27_REFSR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TIMING27_REFSR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING28 0x009A24E8 /* RW-4R */ #define NV_PFB_FBPA_TIMING28__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING28_WRIDON 5:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING28_WRIDON_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING28_WRIDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_TIMING28_WRIDOFF_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING28_NOP2QPOP 16:12 /* RWIVF */ #define NV_PFB_FBPA_TIMING28_NOP2QPOP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TIMING28_NOP2MRS 22:18 /* RWIVF */ #define NV_PFB_FBPA_TIMING28_NOP2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING28_TKO2MRS 30:24 /* RWIVF */ #define NV_PFB_FBPA_TIMING28_TKO2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TIMING29 0x009A24EC /* RW-4R */ #define NV_PFB_FBPA_TIMING29__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING29_TDCC1 13:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING29_TDCC1_INIT 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_TIMING29_TDCC2 29:16 /* RWIVF */ #define NV_PFB_FBPA_TIMING29_TDCC2_INIT 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_TIMING30 0x009A24FC /* RW-4R */ #define NV_PFB_FBPA_TIMING30__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING30_FB_FBIO_DRAM_IDLE_DELAY 9:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_INIT 0x0000013C /* RWI-V */ #define NV_PFB_FBPA_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_GDDR6 0x0000013C /* RW--V */ #define NV_PFB_FBPA_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_SDDR4 0x00000278 /* RW--V */ #define NV_PFB_FBPA_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_HBM2 0x0000009E /* RW--V */ #define NV_PFB_FBPA_TIMING30_FBIO_CKE_CKOFF_SKEW 17:12 /* RWIVF */ #define NV_PFB_FBPA_TIMING30_FBIO_CKE_CKOFF_SKEW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TIMING31 0x009A24F8 /* RW-4R */ #define NV_PFB_FBPA_TIMING31__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING31_XSMRS 10:0 /* RWIVF */ #define NV_PFB_FBPA_TIMING31_XSMRS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_0 0x009A24F0 /* RW-4R */ #define NV_PFB_FBPA_POWER_0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRUP_RD_INTERP 6:0 /* RWIVF */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRUP_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRDN_RD_INTERP 14:8 /* RWIVF */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRDN_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRUP_WR_INTERP 22:16 /* RWIVF */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRUP_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRDN_WR_INTERP 30:24 /* RWIVF */ #define NV_PFB_FBPA_POWER_0_OFFSET_PWRDN_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_1 0x009A24F4 /* RW-4R */ #define NV_PFB_FBPA_POWER_1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRUP_RCVR 6:0 /* RWIVF */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRUP_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRDN_RCVR 14:8 /* RWIVF */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRDN_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRUP_RX_CLK 22:16 /* RWIVF */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRUP_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRDN_RX_CLK 30:24 /* RWIVF */ #define NV_PFB_FBPA_POWER_1_OFFSET_PWRDN_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL0 0x009A2300 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL0_DELAY_REF 30:30 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL0_DELAY_REF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL0_BLCG_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL0_BLCG_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL1 0x009A2304 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL2 0x009A2308 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL3 0x009A230C /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL4 0x009A2310 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL5 0x009A2314 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL6 0x009A2318 /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL7 0x009A231C /* RW-4R */ #define NV_PFB_FBPA_ASR_CTRL7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_ASR_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0 0x009A2320 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0_STALL_DELAY 11:8 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL0_STALL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0_INV_BW_EVAL 29:29 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL0_INV_BW_EVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0_EN_WCKTR 30:30 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL0_EN_WCKTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0_CHECK_DISPLAY_OK 31:31 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL0_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL0_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACPD_CTRL1 0x009A2324 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL2 0x009A2328 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL3 0x009A232C /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL4 0x009A2330 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL5 0x009A2334 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL6 0x009A2338 /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL7 0x009A233C /* RW-4R */ #define NV_PFB_FBPA_ACPD_CTRL7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_ACPD_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL 0x009A2444 /* RW-4R */ #define NV_PFB_FBPA_DQR_CTRL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_CTRL_PERIOD 15:0 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_SET 21:20 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_SET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_CLR 23:22 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_CLR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC0_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC0_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC1_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_DQR_CTRL_EN_IC1_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0 0x009A24C0 /* R--4R */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP1 0x009A24C4 /* R--4R */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP0 0x009A24C8 /* R--4R */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP1 0x009A24CC /* R--4R */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_DQR_STATUS_DQ_IC1_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_VLD 0x009A24D0 /* RW-4R */ #define NV_PFB_FBPA_DQR_STATUS_VLD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC0_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_DQR_STATUS_VLD_IC1_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CONFIG0 0x009A0290 /* RW-4R */ #define NV_PFB_FBPA_CONFIG0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG0_RC 7:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_CONFIG0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RC_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RFC 16:8 /* RWIVF */ #define NV_PFB_FBPA_CONFIG0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_CONFIG0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RFC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RAS 23:17 /* RWIVF */ #define NV_PFB_FBPA_CONFIG0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_CONFIG0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RAS_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RP 30:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG0_RP_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_CONFIG0_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RP_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_CONFIG0_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_CONFIG0_USE_TIMING_REGS 31:31 /* RWIVF */ #define NV_PFB_FBPA_CONFIG0_USE_TIMING_REGS_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_USE_TIMING_REGS_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG0_USE_TIMING_REGS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG0_USE_TIMING_REGS_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG1 0x009A0294 /* RW-4R */ #define NV_PFB_FBPA_CONFIG1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG1_CL 6:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG1_CL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_CONFIG1_CL_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_CL_MAX 0x00000024 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_WL 13:7 /* RWIVF */ #define NV_PFB_FBPA_CONFIG1_WL_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_CONFIG1_WL_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_WL_MAX 0x00000012 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_RD_RCD 19:14 /* RWIVF */ #define NV_PFB_FBPA_CONFIG1_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_CONFIG1_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_RD_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG1_WR_RCD 25:20 /* RWIVF */ #define NV_PFB_FBPA_CONFIG1_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_CONFIG1_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_WR_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_HBM_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_G6_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_G6_HS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_G6X_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_CONFIG1_QPOP_OFFSET_G6X_HS 0x00000011 /* RW--V */ #define NV_PFB_FBPA_CONFIG2 0x009A0298 /* RW-4R */ #define NV_PFB_FBPA_CONFIG2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG2_RPRE 3:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_RPRE_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_WPRE 7:4 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_WPRE_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_CDLR 14:8 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_CDLR_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_CDLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_CDLR_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_CONFIG2_WR 22:16 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_WR_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_WR_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_WR_MAX 0x00000023 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_W2R_BUS 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_W2R_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_W2R_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_W2R_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_CONFIG2_R2W_BUS 31:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG2_R2W_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG2_R2W_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG2_R2W_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_CONFIG3 0x009A029C /* RW-4R */ #define NV_PFB_FBPA_CONFIG3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG3_PDEX 4:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_PDEX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_PDEX_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_CONFIG3_PDEN2PDEX 8:5 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_CONFIG3_FAW 16:9 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_FAW_40 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_FAW_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_CONFIG3_AOND 23:17 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_AOND_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_AOND_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_CONFIG3_AOND_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_AOND_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_CONFIG3_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_CCDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_CCDL_MAX 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG3_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG3_CCDS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG3_CCDS_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CONFIG4 0x009A02A0 /* RW-4R */ #define NV_PFB_FBPA_CONFIG4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO 2:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO_1F 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO_MIN 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO_3_9_US 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_LO_7_8_US 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH 14:3 /* RWIVF */ #define NV_PFB_FBPA_CONFIG4_REFRESH_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_11 0x0000002F /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_MAX 0x00000FFF /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_3_9_US 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_CONFIG4_REFRESH_7_8_US 0x0000001A /* RW--V */ #define NV_PFB_FBPA_CONFIG4_REFRESH__PROD_C_SAMSUNG_DDR3 0x0000002F /* RW--V */ #define NV_PFB_FBPA_CONFIG4_RRD 20:15 /* RWIVF */ #define NV_PFB_FBPA_CONFIG4_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_CONFIG4_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_RRD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY 26:21 /* RWIVF */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_DDR5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_DDR5X 0x00000014 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_DDR6 0x00000014 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_HBM 0x0000000A /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_SDDR4 0x00000028 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY__PROD_C_LEGACY 0x00000014 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_IDLE_DELAY_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC 31:27 /* RWIVF */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_18 0x00000012 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_26 0x0000001A /* RWI-V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5X 0x00000018 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6X 0x00000010 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_HBM 0x00000018 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_SDDR4 0x00000010 /* RW--V */ #define NV_PFB_FBPA_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_LEGACY 0x00000018 /* RW--V */ #define NV_PFB_FBPA_CONFIG5 0x009A02A4 /* RW-4R */ #define NV_PFB_FBPA_CONFIG5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG5_ADR_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_ADR_MIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_WRCRC 10:4 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_WRCRC_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_WRCRC_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_CONFIG5_WRCRC_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_CONFIG5_QSAFE_OFFSET 17:12 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_QSAFE_OFFSET_39 0x00000027 /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_INTRP_MSB 19:18 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_INTRP_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_RDRET_OFFSET 23:20 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_RDRET_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_WRRET_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_WRRET_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_CONFIG5_INTRP 31:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG5_INTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6 0x009A02A8 /* RW-4R */ #define NV_PFB_FBPA_CONFIG6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG6_RDFLUSH_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_RDFLUSH_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_WRFLUSH_OFFSET 14:8 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_WRFLUSH_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT 15:15 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG6_WDAT_LATENCY 20:16 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_WDAT_LATENCY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_PPD 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_PPD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_SDDR4_RDV_OFFSET 29:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_SDDR4_RDV_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_CMD_ADJUST 31:30 /* RWIVF */ #define NV_PFB_FBPA_CONFIG6_CMD_ADJUST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG6_CMD_ADJUST_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG7 0x009A02AC /* RW-4R */ #define NV_PFB_FBPA_CONFIG7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG7_ZQCS_INTERVAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG7_ZQCS_INTERVAL_64 0x0061A800 /* RW--V */ #define NV_PFB_FBPA_CONFIG7_ZQCS_INTERVAL_128 0x00C35000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG8 0x009A02CC /* RW-4R */ #define NV_PFB_FBPA_CONFIG8__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG8_ATR_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG8_ATR_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_CONFIG8_ATR_PADDING 11:8 /* RWIVF */ #define NV_PFB_FBPA_CONFIG8_ATR_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_CONFIG8_ODT_PADDING 15:12 /* RWIVF */ #define NV_PFB_FBPA_CONFIG8_ODT_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_CONFIG8_WCK2PH 23:16 /* RWIVF */ #define NV_PFB_FBPA_CONFIG8_WCK2PH_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_CONFIG8_MRSTWCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG8_MRSTWCK_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9 0x009A02E8 /* RW-4R */ #define NV_PFB_FBPA_CONFIG9__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG9_QUSE_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_QUSE_OFFSET_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9_QUSE_DDLL_SETTLE 11:7 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_QUSE_DDLL_SETTLE_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9_REXT_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_REXT_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9_DLCELL_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_DLCELL_SETTLE_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9_QRST_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG9_MPRR 31:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG9_MPRR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10 0x009A02F4 /* RW-4R */ #define NV_PFB_FBPA_CONFIG10__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG10_RFC_MSB 1:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_RFC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_PDEN2PDEX_MSB 6:5 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_PDEN2PDEX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_RD_RCD_MSB 8:8 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_RD_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_WR_RCD_MSB 11:11 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_WR_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI 17:14 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_SDDR4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_IDLE_DELAY_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI 18:18 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG10_RDRET_OFFSET_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_CONFIG10_RDRET_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11 0x009A03E4 /* RW-4R */ #define NV_PFB_FBPA_CONFIG11__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG11_RRDL 5:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_RRDL_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_CONFIG11_CCDMW 12:7 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_CCDMW_MAX 0x00000010 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_MTA 14:14 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_MTA_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_MTA_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_WPOST 15:15 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_LPDDR4_RDV_OFFSET 18:16 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_WEXT_OFFSET 22:19 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_WEXT_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_RPRE_TOGGLE 23:23 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_RPRE_TOGGLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG11_RPRE_TOGGLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_RD_RANK_SEL_DELAY 27:24 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_RD_RANK_SEL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_CONFIG11_WR_RANK_SEL_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_CONFIG11_WR_RANK_SEL_DELAY_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_CONFIG12 0x009A015C /* RW-4R */ #define NV_PFB_FBPA_CONFIG12__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFIG12_BLDIV 3:0 /* RWIVF */ #define NV_PFB_FBPA_CONFIG12_BLDIV_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG12_ADR_TERM 4:4 /* RWIVF */ #define NV_PFB_FBPA_CONFIG12_ADR_TERM_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG12_ADR_TERM_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFIG12_ADRTR_FIFO_MARGIN 7:5 /* RWIVF */ #define NV_PFB_FBPA_CONFIG12_ADRTR_FIFO_MARGIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG12_CABI_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_CONFIG12_CABI_MODE_DC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFIG12_CABI_MODE_AC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TIMING0_GEN 0x009A02B0 /* R-I4R */ #define NV_PFB_FBPA_TIMING0_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING0_GEN_RC 8:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING0_GEN_RC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING0_GEN_RFC 22:12 /* R-IVF */ #define NV_PFB_FBPA_TIMING0_GEN_RFC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING0_GEN_RAS 31:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING0_GEN_RAS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING1_GEN 0x009A02B4 /* R-I4R */ #define NV_PFB_FBPA_TIMING1_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING1_GEN_R2W 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING1_GEN_R2W_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING1_GEN_W2R 14:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING1_GEN_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING1_GEN_R2P 20:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING1_GEN_R2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING1_GEN_W2P 30:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING1_GEN_W2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING2_GEN 0x009A02B8 /* R-I4R */ #define NV_PFB_FBPA_TIMING2_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING2_GEN_RD_RCD 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING2_GEN_RD_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING2_GEN_WR_RCD 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING2_GEN_WR_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING2_GEN_RRD 22:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING2_GEN_RRD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING2_GEN_WDV 28:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING2_GEN_WDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING3_GEN 0x009A02BC /* R-I4R */ #define NV_PFB_FBPA_TIMING3_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING3_GEN_QUSE 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING3_GEN_QUSE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING3_GEN_QRST 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING3_GEN_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING3_GEN_QSAFE 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING3_GEN_QSAFE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING3_GEN_RDV 31:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING3_GEN_RDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING4_GEN 0x009A02C0 /* R-I4R */ #define NV_PFB_FBPA_TIMING4_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING4_GEN_PDEX2WR 5:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING4_GEN_PDEX2WR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING4_GEN_PDEX2RD 13:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING4_GEN_PDEX2RD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING4_GEN_PDEN2PDEX 19:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING4_GEN_PDEN2PDEX_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING4_GEN_FAW 28:20 /* R-IVF */ #define NV_PFB_FBPA_TIMING4_GEN_FAW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING4_GEN_PDEN2PDEX_MSB 30:29 /* R-IVF */ #define NV_PFB_FBPA_TIMING4_GEN_PDEN2PDEX_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING5_GEN 0x009A02C4 /* R-I4R */ #define NV_PFB_FBPA_TIMING5_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING5_GEN_PCHG2PDEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING5_GEN_PCHG2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING5_GEN_RW2PDEN 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING5_GEN_RW2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING5_GEN_ACT2PDEN 22:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING5_GEN_ACT2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING5_GEN_AR2PDEN 31:23 /* R-IVF */ #define NV_PFB_FBPA_TIMING5_GEN_AR2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING6_GEN 0x009A02C8 /* R--4R */ #define NV_PFB_FBPA_TIMING6_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING6_GEN_PPD 4:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING6_GEN_PPD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING6_GEN_BUS_W2R 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING6_GEN_BUS_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING6_GEN_CMD2MCIDLE_DRAMC 21:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING6_GEN_CMD2MCIDLE_DRAMC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING6_GEN_CMD2MCIDLE_FBIO 30:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING6_GEN_CMD2MCIDLE_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING7_GEN 0x009A02D0 /* R-I4R */ #define NV_PFB_FBPA_TIMING7_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING7_GEN_REXT 3:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING7_GEN_REXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING7_GEN_WEXT 11:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING7_GEN_WEXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING7_GEN_ATR 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING7_GEN_ATR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING7_GEN_ATRLEN 28:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING7_GEN_ATRLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING8_GEN 0x009A02D4 /* R-I4R */ #define NV_PFB_FBPA_TIMING8_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING8_GEN_ODT 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING8_GEN_ODT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING8_GEN_ODTLEN 11:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING8_GEN_ODTLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING8_GEN_QPOP_OFFSET 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING8_GEN_QPOP_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING8_GEN_RPRE 27:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING8_GEN_RPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING8_GEN_WPRE 31:28 /* R-IVF */ #define NV_PFB_FBPA_TIMING8_GEN_WPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING9_GEN 0x009A02D8 /* R-I4R */ #define NV_PFB_FBPA_TIMING9_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING9_GEN_CCDL 3:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING9_GEN_CCDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING9_GEN_CCDS 7:4 /* R-IVF */ #define NV_PFB_FBPA_TIMING9_GEN_CCDS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_ADR 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_ADR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_WCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_WCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_WREDC 31:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING9_GEN_QPOP_OFFSET_WREDC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING15_GEN 0x009A02DC /* R-I4R */ #define NV_PFB_FBPA_TIMING15_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING15_GEN_RDRET 6:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING15_GEN_RDRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_TIMING15_GEN_WRRET 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING15_GEN_WRRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_TIMING15_GEN_RDINTRP 22:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING15_GEN_RDINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_TIMING15_GEN_WRINTRP 30:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING15_GEN_WRINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_TIMING16_GEN 0x009A02E0 /* R--4R */ #define NV_PFB_FBPA_TIMING16_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING16_GEN_RDFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING16_GEN_RDFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING16_GEN_WRFLUSH 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING16_GEN_WRFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING16_GEN_RP 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING16_GEN_RP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING16_GEN_WCK_QRST 26:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING16_GEN_WCK_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING17_GEN 0x009A02E4 /* R-I4R */ #define NV_PFB_FBPA_TIMING17_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING17_GEN_RDRET_PRE 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING17_GEN_RDRET_PRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING17_GEN_WCK2RDWCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING17_GEN_WCK2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING17_GEN_MRS2RDWCK 31:24 /* R-IVF */ #define NV_PFB_FBPA_TIMING17_GEN_MRS2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING18_GEN 0x009A02EC /* R--4R */ #define NV_PFB_FBPA_TIMING18_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING18_GEN_WRCRCFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING18_GEN_WRCRCFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING18_GEN_REXT 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING18_GEN_REXT_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING18_GEN_QUSE_SETTLE 20:16 /* R-IVF */ #define NV_PFB_FBPA_TIMING18_GEN_QUSE_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING18_GEN_DLCELL_SETTLE 29:21 /* R-IVF */ #define NV_PFB_FBPA_TIMING18_GEN_DLCELL_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING19_GEN 0x009A02F0 /* R--4R */ #define NV_PFB_FBPA_TIMING19_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING19_GEN_QRST_OFFSET 4:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING19_GEN_QRST_OFFSET_INIT 0x00000002 /* R-I-V */ #define NV_PFB_FBPA_TIMING19_GEN_QRST_FLUSH 9:5 /* R-IVF */ #define NV_PFB_FBPA_TIMING19_GEN_QRST_FLUSH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING19_GEN_MPRR 16:10 /* R-IVF */ #define NV_PFB_FBPA_TIMING19_GEN_MPRR_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING19_GEN_REFSB_SUBP0 17:17 /* R-IVF */ #define NV_PFB_FBPA_TIMING19_GEN_REFSB_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING19_GEN_REFSB_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_TIMING19_GEN_REFSB_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING20_GEN 0x009A0288 /* R--4R */ #define NV_PFB_FBPA_TIMING20_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING20_GEN_RD_REFRESH 7:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING20_GEN_RD_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING20_GEN_WR_REFRESH 15:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING20_GEN_WR_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_TIMING22_GEN 0x009A03F8 /* R--4R */ #define NV_PFB_FBPA_TIMING22_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBA 9:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBA_INIT 0x00000032 /* R-I-V */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBR 17:10 /* R-IVF */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBR_INIT 0x00000020 /* R-I-V */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBA_MSB 21:20 /* R-IVF */ #define NV_PFB_FBPA_TIMING22_GEN_RFCSBA_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING24_GEN 0x009A03E8 /* R-I4R */ #define NV_PFB_FBPA_TIMING24_GEN__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TIMING24_GEN_RRDL 6:0 /* R-IVF */ #define NV_PFB_FBPA_TIMING24_GEN_RRDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING24_GEN_CCDMW 14:8 /* R-IVF */ #define NV_PFB_FBPA_TIMING24_GEN_CCDMW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING24_GEN_LPDDR4_RDV_OFFSET 18:15 /* R-IVF */ #define NV_PFB_FBPA_TIMING24_GEN_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING24_GEN_ABPA 25:20 /* R-IVF */ #define NV_PFB_FBPA_TIMING24_GEN_ABPA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TIMING24_GEN_XS_OFFSET 31:26 /* R-IVF */ #define NV_PFB_FBPA_TIMING24_GEN_XS_OFFSET_INIT 0x0000000A /* R-I-V */ #define NV_PFB_FBPA_PTR_RESET 0x009A0158 /* RW-4R */ #define NV_PFB_FBPA_PTR_RESET__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PTR_RESET_TESTCMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_PTR_RESET_TESTCMD_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PTR_RESET_TESTCMD_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PTR_RESET_WDATFIFO 1:1 /* RWIVF */ #define NV_PFB_FBPA_PTR_RESET_WDATFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PTR_RESET_WDATFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PTR_RESET_EDCFIFO 2:2 /* RWIVF */ #define NV_PFB_FBPA_PTR_RESET_EDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PTR_RESET_EDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PTR_RESET_RRDATAFIFO 3:3 /* RWIVF */ #define NV_PFB_FBPA_PTR_RESET_RRDATAFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PTR_RESET_RRDATAFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PTR_RESET_RREDCFIFO 4:4 /* RWIVF */ #define NV_PFB_FBPA_PTR_RESET_RREDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PTR_RESET_RREDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ASR_STALL_WKUP 0x009A0384 /* RW-4R */ #define NV_PFB_FBPA_ASR_STALL_WKUP__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_STALL_WKUP_EN 3:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_STALL_WKUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_STALL_WKUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ASR_STALL_WKUP_EN_ENABLE_LAT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ASR_STALL_WKUP_RES_THRES 15:4 /* RWIVF */ #define NV_PFB_FBPA_ASR_STALL_WKUP_RES_THRES_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_ASR_STALL_WKUP_LAT_THRES 27:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_STALL_WKUP_LAT_THRES_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_ASR_WAKEUP 0x009A02F8 /* RW-4R */ #define NV_PFB_FBPA_ASR_WAKEUP__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ASR_WAKEUP_CNT 15:0 /* RWIVF */ #define NV_PFB_FBPA_ASR_WAKEUP_CNT_5K 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN 17:16 /* RWIVF */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_ENABLE_STD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_ENABLE_STRICT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_ENABLE_TIMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ASR_WAKEUP_EN_ENABLE_NISO 0x00000003 /* RW--V */ #define NV_PFB_FBPA_ASR_WAKEUP_PIPE 27:24 /* RWIVF */ #define NV_PFB_FBPA_ASR_WAKEUP_PIPE_16 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR 0x009A02FC /* RW-4R */ #define NV_PFB_FBPA_DRAM_ASR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DRAM_ASR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_ASRPD 1:1 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_ASRPD_NO_POWERDOWN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_ASRPD_POWERDOWN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_ASRCLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_ASRCLK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_ASRCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_NOISO 3:3 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_NOISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_NOISO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_PREA 4:4 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_PREA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_PREA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_NO_WCKTR 5:5 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_NO_WCKTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_NO_WCKTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_REF 6:6 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_REF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_REF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_ACPD 7:7 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_ACPD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_ACPD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_ZQ 9:8 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_ZQ_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_ZQ_CL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_ZQ_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_DRAM_ASR_CHECK_DISPLAY_OK 10:10 /* RWIVF */ #define NV_PFB_FBPA_DRAM_ASR_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAM_ASR_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS 0x009A0300 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS__PRIV_LEVEL_MASK 0x009A2250 /* */ #define NV_PFB_FBPA_GENERIC_MRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_HBM_RDBI 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_WL 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_WL 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_HBM_WDBI 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_CL 6:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_CL 6:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR5_WR 11:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_ADR_GDDR6X_WR 11:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS 0x009A0304 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS_ADR_RTT_NOM 10:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_EMRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_EXT 0x009A0308 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS_EXT_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT 0x009A030C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS_EXT_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_REF 0x009A0310 /* -W-4R */ #define NV_PFB_FBPA_REF__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REF_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_REF_CMD_REFRESH 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_REF_CMD_REFRESH_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_REF_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_REF_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_REF_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_REF_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_REF_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_REF_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_REF_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_REF_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_REF_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_REF_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_REF_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_REF_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_REF_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_REF_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_REF_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_PRE 0x009A0314 /* -W-4R */ #define NV_PFB_FBPA_PRE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PRE_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_PRE_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_PRE_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_PRE_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_PRE_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_PRE_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_PRE_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_PRE_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_PRE_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_PRE_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_PRE_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_PRE_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_PRE_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_PRE_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_PRE_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_PRE_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_NOP 0x009A0318 /* -W-4R */ #define NV_PFB_FBPA_NOP__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_NOP_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_NOP_CMD_NOP 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_NOP_CMD_NOP_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_SELF_REF 0x009A031C /* RW-4R */ #define NV_PFB_FBPA_SELF_REF__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_SELF_REF_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_SELF_REF_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SELF_REF_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_SELF_REF_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_SELF_REF_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_SELF_REF_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_SELF_REF_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_SELF_REF_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS2 0x009A0320 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS2_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS2_ADR_CWL 5:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_EMRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS2_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS2_BA__PROD_C_SAMSUNG_DDR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS3 0x009A0324 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS3_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT 0x009A0328 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS2_EXT_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT 0x009A032C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_EMRS3_EXT_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1 0x009A0330 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_HBM_WR 4:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_HBM_DRV 7:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_NORMAL 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_FIXED 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_40 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_48 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM 5:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_CKE_VAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_RDBI 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_RDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_RDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_MTA 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_MTA_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_MTA_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_WDBI 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_WDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_WDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_PAM4 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_PAM4_PAM4 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_PAM4_GDDR6 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ABI 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_ABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CABI 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR6X_CABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL_RESET 11:11 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS1_BA_MRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS1_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS1_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS1_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2 0x009A0334 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_HBM_WL 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_HBM_RL 7:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR5_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR5_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR5_DATA_WCK_TERM_OFFSET 8:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR5_ADDRESS_TERM_OFFSET 11:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_SELF_REF 7:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_ATCSR 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST 11:11 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_NO 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_YES 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS2_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS2_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS2_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS2_BA_MRS 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS2_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS2_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS2_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS2_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS2_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS2_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3 0x009A0338 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH 1:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_16MS 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_8MS 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_HBM_RAS 5:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK01_INV 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_DATA_TERM_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK23_INV 3:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING 4:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_RDQS 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_RDQS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_RDQS_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_CA_TERM_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_INFO_VENDOR_ID 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID1 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID2 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK_TERM 9:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING 9:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_1X 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_2X 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_ENABLED 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_3 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_4 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_ON 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS3_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS3_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS3_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS3_BA_MRS 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS3_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS3_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS3_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS3_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS3_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS3_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4 0x009A033C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_EDC13_INV 11:11 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV 11:11 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS4_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_BA_MRS 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5 0x009A0340 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP1 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP1_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP1_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_PLL_BANDWIDTH 5:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR5_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_RAS_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_ADR_GDDR6X_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_DM 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_DM_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_DM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_WDBI 11:11 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_WDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_WDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_RDBI 12:12 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS5_RDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_RDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS5_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_BA_MRS 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS5_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6 0x009A0344 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_WCKPIN 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREFD 3:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREFD_EXTERNAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREFD_INTERNAL 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE23 7:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE01 11:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS6_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7 0x009A0348 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK_AP 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_1DB 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_2DB 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_40 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_48 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_5 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_35 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_2 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_35 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_25 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DCC_HOLD 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR5_DCC_RESET 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_DCC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_ADR_GDDR6X_DCC_HOLD 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS7_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS7_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS7_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS7_BA_MRS 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS7_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS7_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS7_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS7_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS7_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS7_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8 0x009A0354 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS8__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_CL_EHF 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_CL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_CL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_WR_EHF 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR5_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TERM 1:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_80 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_INV_READ 3:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_INV_READ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_INV_READ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TO 4:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TO_RESET 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CA_TO_PROG 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_DIS 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_EN 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_REFPB 7:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_REFPB_PB 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_REFPB_P2B 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_RL_EHF 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_WR_EHF 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6_CATH 3:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6_PLL_RANGE 4:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_ADR_GDDR6_MICRON_PLL_RANGE_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS8_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS8_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS8_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS8_BA_MRS 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS8_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS8_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS8_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS8_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS8_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS8_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9 0x009A0358 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS9__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR5_PRE_EMPHASIS 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_RX_MASK 1:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDL 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDM 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDU 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_TXEQ 6:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_TXEQ_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_TXEQ_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS9_ADR_GDDR6X_PIN_SUB_ADDRESS 11:7 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS9_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10 0x009A2200 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS10__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET 3:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT 5:4 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT 7:6 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK2CK 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET_MSB 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM 11:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS10_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS10_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS10_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS10_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS10_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS10_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS10_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS10_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS10_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS10_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11 0x009A2204 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS11__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS11_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS11_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS11_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS11_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS11_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS11_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS11_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS11_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS11_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS11_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS11_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS11_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12 0x009A2208 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS12__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_LSB 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_MSB 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_PRBS 2:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_PRBS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_PRBS_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK 11:3 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS12_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS12_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS12_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS12_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS12_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS12_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS12_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS12_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS12_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS12_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13 0x009A220C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS13__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS13_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS13_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS13_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS13_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS13_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS13_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS13_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS13_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS13_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS13_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS13_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS13_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14 0x009A035C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS14__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR_MICRON_CORE_VOLTAGE 4:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS14_ADR_MICRON_SUBREG_SELECT 11:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS14_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15 0x009A034C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS15__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_HBM_IVREF 2:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREA 0:0 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREA_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREA_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREB 1:1 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREB_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_MREB_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_CADT 3:2 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_CADT_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_CADT_RISING 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_CADT_FALLING 0x00000002 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR6X_CADT_CABI 0x00000003 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF0 8:8 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF1 9:9 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING 10:10 /* ----F */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_GENERIC_MRS15_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS15_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS15_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS15_BA_MRS 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS15_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS15_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS15_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS15_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS15_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS15_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16 0x009A2210 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS16__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS16_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS16_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS16_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS16_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS16_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS16_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS16_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS16_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS16_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS16_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS16_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS16_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17 0x009A2214 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS17__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS17_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS17_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS17_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS17_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS17_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS17_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS17_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS17_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS17_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS17_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS17_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS17_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18 0x009A2218 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS18__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS18_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS18_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS18_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS18_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS18_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS18_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS18_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS18_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS18_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS18_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS18_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS18_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19 0x009A221C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS19__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS19_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS19_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS19_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS19_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS19_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS19_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS19_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS19_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS19_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS19_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS19_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS19_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20 0x009A2220 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS20__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS20_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS20_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS20_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS20_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS20_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS20_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS20_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS20_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS20_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS20_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS20_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS20_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22 0x009A2224 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS22__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS22_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS22_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS22_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS22_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS22_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS22_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS22_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS22_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS22_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS22_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS22_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS22_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23 0x009A2228 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS23__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS23_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS23_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS23_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS23_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS23_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS23_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS23_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS23_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS23_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS23_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS23_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS23_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24 0x009A222C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS24__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS24_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS24_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS24_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS24_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS24_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS24_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS24_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS24_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS24_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS24_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS24_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS24_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25 0x009A2230 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS25__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS25_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS25_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS25_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS25_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS25_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS25_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS25_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS25_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS25_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS25_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS25_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS25_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32 0x009A2234 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS32__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS32_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS32_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS32_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS32_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS32_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS32_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS32_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS32_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS32_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS32_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS32_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS32_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40 0x009A2238 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS40__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS40_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS40_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS40_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS40_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS40_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS40_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS40_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS40_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS40_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS40_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS40_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS40_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MRR 0x009A223C /* RW-4R */ #define NV_PFB_FBPA_MRR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_MRR_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MRR_CMD_MRR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MRR_CMD_MRR_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MRR_BA 6:1 /* RWIVF */ #define NV_PFB_FBPA_MRR_BA_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MRR_RANK 7:7 /* RWIVF */ #define NV_PFB_FBPA_MRR_RANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MRR_CH 8:8 /* RWIVF */ #define NV_PFB_FBPA_MRR_CH_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MRR_GEN_DATA_VLD_SUBP0 10:10 /* R-IVF */ #define NV_PFB_FBPA_MRR_GEN_DATA_VLD_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MRR_GEN_DATA_SUBP0 18:11 /* R-IVF */ #define NV_PFB_FBPA_MRR_GEN_DATA_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MRR_GEN_DATA_VLD_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MRR_GEN_DATA_VLD_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MRR_GEN_DATA_SUBP1 27:20 /* R-IVF */ #define NV_PFB_FBPA_MRR_GEN_DATA_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MPC 0x009A2240 /* RW-4R */ #define NV_PFB_FBPA_MPC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_MPC_ADR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MPC_ADR_NOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MPC_ADR_START_DQS_OSC 0x0000004b /* RW--V */ #define NV_PFB_FBPA_MPC_ADR_STOP_DQS_OSC 0x0000004d /* RW--V */ #define NV_PFB_FBPA_MPC_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MPC_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MPC_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MPC_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MPC_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MPC_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MPC_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MPC_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MPC_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MPC_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MPC_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MPC_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MPC_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MPC_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MPC_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC 0x009A0350 /* RW-4R */ #define NV_PFB_FBPA_MISC_DRAMC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_BANK_SEQ 1:1 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_BANK_SEQ_INC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_BANK_SEQ_BG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_NO_TR_ACT_IN_TFAW 2:2 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_NO_TR_ACT_IN_TFAW_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_NO_TR_ACT_IN_TFAW_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_TR_RW_ALL_BANK 3:3 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_TR_RW_ALL_BANK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_TR_RW_ALL_BANK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_IDLE_ON_TR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_IDLE_ON_TR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_IDLE_ON_TR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_ACT_HIGH_PRIORITY 5:5 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_ACT_HIGH_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_ACT_HIGH_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_HOLDOFF_WRACT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_HOLDOFF_WRACT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_HOLDOFF_WRACT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY 7:7 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_WR_FEEDBACK 8:8 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_WR_FEEDBACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_WR_FEEDBACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_BG_ENABLE_ON_CCD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_BG_ENABLE_ON_CCD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_BG_ENABLE_ON_CCD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_ENABLE_RRDL_COUNTER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_ENABLE_RRDL_COUNTER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_ENABLE_RRDL_COUNTER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_KILL_PEND_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_KILL_PEND_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_KILL_PEND_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_TR_SAFE_SCHED 18:12 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_TR_SAFE_SCHED_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_ABPA_PER_RANK 19:19 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_ABPA_PER_RANK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_MAX_BANK_HITS 26:20 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_MAX_BANK_HITS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_MAX_BANK_HITS_MAX 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_PRIORITY 28:27 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_PRIORITY_HIGHEST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_PRIORITY_MEDIUM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_PRIORITY_LOWEST 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_GBL_RRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_GBL_RRD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_PBR_GBL_RRD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_CMDQ_ALWAYS_ON 30:30 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_CMDQ_ALWAYS_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_CMDQ_ALWAYS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MISC_DRAMC_FORCE_G5_TO_G5X 31:31 /* RWIVF */ #define NV_PFB_FBPA_MISC_DRAMC_FORCE_G5_TO_G5X_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MISC_DRAMC_FORCE_G5_TO_G5X_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_IC_CTRL 0x009A0208 /* RW-4R */ #define NV_PFB_FBPA_IC_CTRL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_DIRECTION_SYNC 0:0 /* RWIVF */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_DIRECTION_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_DIRECTION_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_IC_CTRL_SP2DRAMC_FLOP 1:1 /* RWIVF */ #define NV_PFB_FBPA_IC_CTRL_SP2DRAMC_FLOP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_IC_CTRL_SP2DRAMC_FLOP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_STALL_CMD_FIFO 0x009A23FC /* RW-4R */ #define NV_PFB_FBPA_STALL_CMD_FIFO__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_STALL_CMD_FIFO_THRESHOLD 4:0 /* RWIVF */ #define NV_PFB_FBPA_STALL_CMD_FIFO_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_STALL_CMD_FIFO_STALL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_STALL_CMD_FIFO_STALL_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0 0x009A0360 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1 0x009A0364 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS6_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0 0x009A0368 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1 0x009A036C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS9_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0 0x009A0370 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1 0x009A0374 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS14_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT 0x009A0378 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS4_EXT_BA_MRS4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT 0x009A037C /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS5_EXT_BA_MRS5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT 0x009A0380 /* RW-4R */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_GENERIC_MRS6_EXT_BA_MRS6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_CG1 0x009A0280 /* RW-4R */ #define NV_PFB_FBPA_CG1__PRIV_LEVEL_MASK 0x009A01B4 /* */ #define NV_PFB_FBPA_CG1_SLCG_TRAINING 0:0 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_TRAINING_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_TRAINING_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_PRIV 1:1 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_PRIV_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_PRIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_REPLAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_REPLAY_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_REPLAY_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SS2PACMD1 3:3 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SS2PACMD1_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SS2PACMD1_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_FABSCAN 4:4 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_FABSCAN_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_FABSCAN_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_PRIVSYNC 5:5 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_PRIVSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_PRIVSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_6 6:6 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_6_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_6_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_PAF2TSUBP 7:7 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_PAF2TSUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_PAF2TSUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_ILA 8:8 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_ILA_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_ILA_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_PAL 9:9 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_PAL_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_PAL_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_10 10:10 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_10_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_10_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_11 11:11 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_11_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_11_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_12 12:12 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_12_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_12_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_13 13:13 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_13_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_13_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_14 14:14 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_14_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_14_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_15_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_15_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_16 16:16 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_16_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_16_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_17 17:17 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_17_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_17_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_18 18:18 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_18_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_18_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_19 19:19 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_19_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_19_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_20 20:20 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_20_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_20_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_21 21:21 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_21_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_21_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_22 22:22 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_22_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_22_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_23 23:23 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_23_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_23_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_24 24:24 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_24_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_24_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_25 25:25 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_25_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_25_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_26 26:26 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_26_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_26_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_27 27:27 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_27_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_27_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_28 28:28 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_28_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_28_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_29 29:29 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_29_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_29_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_30 30:30 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_30_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_30_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_31 31:31 /* RWIVF */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_31_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG1_SLCG_SPARE_31_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG1_SLCG 31:0 /* ----F */ #define NV_PFB_FBPA_CG1_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_CG1_SLCG_DISABLED 0xFFFFFFFF /* ----V */ #define NV_PFB_FBPA_CG1_SLCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_CG2 0x009A0284 /* RW-4R */ #define NV_PFB_FBPA_CG2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CG2_FGCG_FAB_INTFC 0:0 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_FAB_INTFC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_FAB_INTFC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_SUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_SUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG_MISC 2:2 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_MISC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG_FABRIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG_PRI_REG_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_PRI_REG_UPDATE_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_PRI_REG_UPDATE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG_CMD_FABRIC 5:5 /* RWIVF */ #define NV_PFB_FBPA_CG2_FGCG_CMD_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CG2_FGCG_CMD_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CG2_FGCG 5:0 /* ----F */ #define NV_PFB_FBPA_CG2_FGCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_CG2_FGCG_DISABLED 0x0000003F /* ----V */ #define NV_PFB_FBPA_CG2_FGCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_READ_FT_CFG 0x009A0400 /* RW-4R */ #define NV_PFB_FBPA_READ_FT_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_CHAIN 4:0 /* RWIVF */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_CHAIN_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_CHAIN_32 0x0000001f /* RW--V */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_CHAIN_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_LIST_SIZE 10:8 /* RWIVF */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_LIST_SIZE_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_READ_FT_CFG_MAX_LIST_SIZE_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_READ_FT_CFG_PAGE_SIZE 12:12 /* RWIVF */ #define NV_PFB_FBPA_READ_FT_CFG_PAGE_SIZE_1K 0x00000000 /* RW--V */ #define NV_PFB_FBPA_READ_FT_CFG_PAGE_SIZE_2K 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_READ_FT_CFG_SET_SWIZZLE 16:16 /* RWIVF */ #define NV_PFB_FBPA_READ_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG 0x009A0410 /* RW-4R */ #define NV_PFB_FBPA_WRITE_FT_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_8 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN 8:8 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_EVICT_ON_CLEAN 9:9 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_EVICT_ON_CLEAN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_EVICT_ON_CLEAN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_BANKQ 10:10 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL 18:12 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_DISABLE 0x0000007f /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN 20:20 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_SET_SWIZZLE 24:24 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD 31:28 /* RWIVF */ #define NV_PFB_FBPA_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD_3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG 0x009A0420 /* RW-4R */ #define NV_PFB_FBPA_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG 0x009A0430 /* RW-4R */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0 0x009A0440 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG0_LATENCY_INTERVAL 7:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_LATENCY_INTERVAL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_LATENCY_INTERVAL_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LATENCY_OFFSET 11:8 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LATENCY_OFFSET_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LATENCY_OFFSET_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LATENCY_OFFSET_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LATENCY_OFFSET_F 0x0000000F /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_READ_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_WRITE_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY 27:24 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY 31:28 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1 0x009A0444 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT 2:2 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_SNAPSHOT_ARB 3:3 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_SNAPSHOT_ARB_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_SNAPSHOT_ARB_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR 5:5 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1 6:6 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_BLOCKS_SPSM 7:7 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN 11:8 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN 15:12 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1 31:28 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG2 0x009A0448 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG2_READ_SEC_THRESHOLD 7:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG2_READ_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG2_READ_SEC_OFFSET 15:8 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG2_READ_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD 23:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG2_WRITE_SEC_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG2_WRITE_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3 0x009A046C /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB 11:8 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB 15:12 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB 19:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB 23:20 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG3_LATENCY_USES_LTCCLK 31:31 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG3_LATENCY_USES_LTCCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG4 0x009A04BC /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG4_READ_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG4_READ_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG4_WRITE_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG4_WRITE_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG5 0x009A2580 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG5__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG6 0x009A2584 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG6__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG7 0x009A2588 /* RW-4R */ #define NV_PFB_FBPA_DIR_ARB_CFG7__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT 3:0 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT 7:4 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG 0x009A0450 /* RW-4R */ #define NV_PFB_FBPA_WRITE_ARB_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WRITEPULL_REQ 11:11 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WRITEPULL_REQ_IMM 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_WRITEPULL_REQ_WAIT_RWDIR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_USE_DRAMC_BUSY 12:12 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_USE_DRAMC_BUSY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_USE_DRAMC_BUSY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CMD_FIFO_DEPTH 17:13 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CMD_FIFO_DEPTH_NOLIMIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 18:18 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB 19:19 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_POLICY 20:20 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE 22:22 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_PRIORITY 23:23 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_PRIORITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_PRIORITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB 24:24 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB_NOLIMIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_DELAY 25:25 /* RWIVF */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_DELAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_WRITE_ARB_CFG_CCDMW_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG 0x009A0454 /* RW-4R */ #define NV_PFB_FBPA_READ_ARB_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_READ_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 11:11 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB 12:12 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_POLICY 13:13 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_LEVEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_COMBINE 15:15 /* RWIVF */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_READ_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG 0x009A0460 /* RW-4R */ #define NV_PFB_FBPA_ACT_ARB_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_RD_SUBPACKETS 5:0 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_RD_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_RESNAP_DURING_TURN 6:6 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_RESNAP_DURING_TURN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_RESNAP_DURING_TURN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SNAP_BASED_ON_VC 7:7 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_SNAP_BASED_ON_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SNAP_BASED_ON_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_WR_SUBPACKETS 14:8 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_WR_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_BGSEC 15:15 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_BGSEC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_BGSEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_BANKQ_ENTRIES 19:16 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_BANKQ_ENTRIES_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_MAX_SKIP_COUNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_MAX_SKIP_COUNT_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM 29:24 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM_6 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_PER_VC 30:30 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_PER_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_PER_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_MODE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG_SKIP_CNT_MODE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1 0x009A0464 /* RW-4R */ #define NV_PFB_FBPA_ACT_ARB_CFG1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACT_ARB_CFG1_ACTARB_CMD_DELAY 3:0 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_ACTARB_CMD_DELAY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_ACTARB_CMD_DELAY_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_HOLDOFF 5:4 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF 7:6 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH 13:8 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN 14:14 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT 15:15 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_HOLDOFF 17:16 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF 19:18 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH 25:20 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG1_ACTARB_FIFO_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG1_ACTARB_FIFO_DELAY_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2 0x009A0468 /* RW-4R */ #define NV_PFB_FBPA_ACT_ARB_CFG2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT 8:0 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE 9:9 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT 11:11 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT 20:12 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE 25:21 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE 30:26 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG3 0x009A04C8 /* RW-4R */ #define NV_PFB_FBPA_ACT_ARB_CFG3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACT_ARB_CFG3_IC_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG3_IC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG3_IC_MODE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG4 0x009A04D0 /* RW-4R */ #define NV_PFB_FBPA_ACT_ARB_CFG4__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT 10:0 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT 16:16 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH 0x009A04D4 /* RW-4R */ #define NV_PFB_FBPA_FIFO_DEPTH__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX 4:0 /* RWIVF */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR5 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR5 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MIN 12:8 /* RWIVF */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_MIN_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_TYPE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_TYPE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FIFO_DEPTH_ASYNC_CMDQ_TYPE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW 0x009A04D8 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_ACPD_ASR 0x009A0458 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_ACPD_ASR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR 0x009A04DC /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0 0x009A04F0 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1 0x009A04F4 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2 0x009A04F8 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR 0x009A04FC /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_WR 0x009A04E0 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_WR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_WR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_WR_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_VC0 0x009A04E4 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_VC0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_VC0_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_VC0_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_VC1 0x009A04E8 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_VC1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_VC1_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_VC1_UTIL_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_VC1_ECC 0x009A045C /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_VC1_ECC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_VC1_ECC_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_VC1_ECC_UTIL_INIT 0x00000555 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_VC2 0x009A04EC /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_VC2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_VC2_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_VC2_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_ACPD 0x009A04B0 /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_ACPD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_ACPD_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_ACPD_UTIL_INIT 0x000000CC /* RWI-V */ #define NV_PFB_FBPA_BW_TRACKER_ASR 0x009A044C /* RW-4R */ #define NV_PFB_FBPA_BW_TRACKER_ASR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BW_TRACKER_ASR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_BW_TRACKER_ASR_UTIL_INIT 0x00000199 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL 0x009A0470 /* RW-4R */ #define NV_PFB_FBPA_ECC_CONTROL__PRIV_LEVEL_MASK 0x009A0170 /* */ #define NV_PFB_FBPA_ECC_CONTROL_MASTER_EN 0:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_CONTROL_MASTER_EN_ENABLED 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_CONTROL_MASTER_EN_DISABLED 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_CONTROL_INCLUDE_ADDR 1:1 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_INCLUDE_ADDR_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_INCLUDE_ADDR_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL 4:3 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL_OFF 0x0 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_WRITE_KILL_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_EN 5:5 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_SIDEBAND_EN 6:6 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_SIDEBAND_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_SIDEBAND_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR_MODE 8:7 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR_MODE_OFF 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR_MODE_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR_MODE_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0 17:9 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR0_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1 28:20 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_WRITE_KILL_PTR1_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT 29:29 /* RWIVF */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_ECC_INTR_CTRL 0x009A0474 /* RW-4R */ #define NV_PFB_FBPA_ECC_INTR_CTRL_SEC_INTR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_INTR_CTRL_SEC_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_SEC_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_DED_INTR_EN 1:1 /* RWIVF */ #define NV_PFB_FBPA_ECC_INTR_CTRL_DED_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_DED_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_POISON_INTR_EN 2:2 /* RWIVF */ #define NV_PFB_FBPA_ECC_INTR_CTRL_POISON_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_POISON_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_ADDRERR_INTR_EN 3:3 /* RWIVF */ #define NV_PFB_FBPA_ECC_INTR_CTRL_ADDRERR_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_ECC_INTR_CTRL_ADDRERR_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_STATUS(i) (0x009A0478+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ECC_STATUS__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_STATUS_SEC_INTR 1:1 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_SEC_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_SEC_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_SEC_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_DED_INTR 2:2 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_DED_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_DED_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_DED_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_POISON_INTR 3:3 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_POISON_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_POISON_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_POISON_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_INTR 4:4 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_SEC_COUNTER_OVERFLOW 17:17 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_SEC_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_SEC_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_SEC_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_DED_COUNTER_OVERFLOW 18:18 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_DED_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_DED_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_DED_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW 19:19 /* RWIVF */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_ECC_SEC_COUNT(i) (0x009A0480+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ECC_SEC_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_SEC_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_SEC_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_DED_COUNT(i) (0x009A0488+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ECC_DED_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_DED_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_DED_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_DIAG(i) (0x009A0490+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_ECC_DIAG__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_DIAG_TYPE 1:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_DIAG_TYPE_SEC 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_DIAG_TYPE_DED 0x1 /* R---V */ #define NV_PFB_FBPA_ECC_DIAG_TYPE_POISON 0x2 /* R---V */ #define NV_PFB_FBPA_ECC_DIAG_DED 2:2 /* RWIVF */ #define NV_PFB_FBPA_ECC_DIAG_DED_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_DIAG_SEC 3:3 /* RWIVF */ #define NV_PFB_FBPA_ECC_DIAG_SEC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_DIAG_POISON 4:4 /* RWIVF */ #define NV_PFB_FBPA_ECC_DIAG_POISON_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_DIAG_SECBIT 16:8 /* R-IVF */ #define NV_PFB_FBPA_ECC_DIAG_SECBIT_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR(i) (0x009A0498+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR__PRIV_LEVEL_MASK 0x009A0170 /* */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_COL 8:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_COL_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_PC 9:9 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_PC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_ROW 26:10 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_ROW_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_BANK 30:27 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_BANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXTBANK 31:31 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXTBANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXT(i) (0x009A24B8+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXT__PRIV_LEVEL_MASK 0x009A0170 /* */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXT_SID 2:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_ERR_INJECTION_ADDR_EXT_SID_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_ECC_ADDR(i) (0x009A04A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT(i) (0x009A04A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT2(i) (0x009A2498+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT2__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_DED(i) (0x009A2448+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_DED_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_DED_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_DED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_DED_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_DED_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED(i) (0x009A2450+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_DED_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_DED(i) (0x009A24A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_DED_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_DED_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_SEC(i) (0x009A2458+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_SEC_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_SEC_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_SEC_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_SEC_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_SEC_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC(i) (0x009A2460+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_SEC_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SEC(i) (0x009A24A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SEC_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_SEC_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_POISON(i) (0x009A2468+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_POISON_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_POISON_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_POISON_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_POISON_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_POISON_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON(i) (0x009A2470+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_POISON_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_POISON(i) (0x009A24B0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_POISON_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT2_POISON_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR(i) (0x009A2480+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_ADDRERR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR(i) (0x009A2488+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_SID 22:20 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_ECC_ADDR_EXT_ADDRERR_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_ECC_ADDRERR_COUNT(i) (0x009A2490+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_ECC_ADDRERR_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_ECC_ADDRERR_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_ECC_ADDRERR_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_BANK_SWIZZLE 0x009A04B4 /* RW-4R */ #define NV_PFB_FBPA_BANK_SWIZZLE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_BANK_SWIZZLE_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_BANK_SWIZZLE_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_BANK_SWIZZLE_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_BANK_SWIZZLE_OVERRIDE 4+4:4 /* RWIVF */ #define NV_PFB_FBPA_BANK_SWIZZLE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_BANK_SWIZZLE_OVERRIDE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BANK_SWIZZLE_OVERRIDE_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION 0x009A04B8 /* RW-4R */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY 0:0 /* RWIVF */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR 10:2 /* RWIVF */ #define NV_PFB_FBPA_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER 0x009A04C0 /* RW-4R */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_READS 5:0 /* RWIVF */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_READS_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_READS_24 0x00000018 /* RW--V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_READS_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_RW 13:8 /* RWIVF */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_RW_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_RW_28 0x0000001C /* RW--V */ #define NV_PFB_FBPA_LTC_BANDWIDTH_LIMITER_RW_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO 0x009A04C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_INIT 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_INIT_VAL 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET 4:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET 7:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET 13:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET 16:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET 19:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET 28:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_READSCHEDULE_FIFO 0x009A04CC /* RW-4R */ #define NV_PFB_FBPA_READSCHEDULE_FIFO__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_READSCHEDULE_FIFO_DEPTH_LIMIT 8:0 /* RWIVF */ #define NV_PFB_FBPA_READSCHEDULE_FIFO_DEPTH_LIMIT_FULL 0x000001FF /* RWI-V */ #define NV_PFB_FBPA_TRIGGER_CNTRL 0x009A0500 /* RW-4R */ #define NV_PFB_FBPA_TRIGGER_CNTRL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE 5:0 /* RWIUF */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_MRS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_REFRESH 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_SELFREFRESH_ENTRY 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_POWERSTATE_EXIT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_POWERDOWN_ENTRY 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_PRECHARGE 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_PRECHARGE_ALL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_ACTIVATE 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_WRITE 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_WRITE_AUTOPRE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_WRITE_ANY 0x0000000B /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_READ 0x0000000C /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_READ_AUTOPRE 0x0000000D /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_READ_ANY 0x0000000E /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_CACHE_MGMT_OP_PENDING 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_LDFF 0x00000010 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_RDTR 0x00000011 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_WRTR 0x00000012 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_ZQCL 0x00000013 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_ZQCS 0x00000014 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_REPLAY 0x00000015 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_REPLAY_START 0x00000016 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_READ_TRAINING 0x00000017 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_WRITE_TRAINING 0x00000018 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_MRR 0x00000019 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_MPC 0x0000001A /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_REFSB 0x0000001B /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_STEP 0x00000020 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_SEQUENCE 0x00000021 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_ADR 0x00000022 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_WCK 0x00000023 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_RD 0x00000024 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_WR 0x00000025 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_QUSE 0x00000026 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_MODE 0x00000027 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_TRAINING_PERIODIC 0x00000028 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_CHAR_WRITE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_CHAR_READ 0x00000017 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_CHAR_ERROR 0x0000002C /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_CHAR_ERROR_ANY 0x0000002D /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_MASKED_PW 0x0000002F /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_PAIRED_RW 0x00000030 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_UNPAIRED_CH0 0x00000032 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_UNPAIRED_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_UNPAIRED_CH0_SW 0x00000032 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_UNPAIRED_CH1_SW 0x00000031 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_EDC_RD_ERR 0x00000033 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_EDC_WR_ERR 0x00000034 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_STATE_DQR 0x00000035 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_BASE_DELAY 12:8 /* RWIUF */ #define NV_PFB_FBPA_TRIGGER_CNTRL_BASE_DELAY_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_BASE_DELAY_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_LENGTH 23:20 /* RWIUF */ #define NV_PFB_FBPA_TRIGGER_CNTRL_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_LENGTH_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_LENGTH_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_INV 28:28 /* RWIUF */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_INV_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_INV_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_EN 31:31 /* RWIUF */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRIGGER_CNTRL_TRIGGER_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAP0 0x009A050C /* R--4R */ #define NV_PFB_FBPA_CAP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CAP0_FABRIC_PRESENT 0:0 /* R-IVF */ #define NV_PFB_FBPA_CAP0_FABRIC_PRESENT_YES 0x00000001 /* R-I-V */ #define NV_PFB_FBPA_CAP0_FABRIC_PRESENT_NO 0x00000000 /* R---V */ #define NV_PFB_FBPA_CAP0_ECC_PRESENT 4:4 /* R-IVF */ #define NV_PFB_FBPA_CAP0_ECC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CAP0_ECC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_CAP0_EDC_PRESENT 8:8 /* R-IVF */ #define NV_PFB_FBPA_CAP0_EDC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CAP0_EDC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_CAP0_REPLAY_PRESENT 12:12 /* R-IVF */ #define NV_PFB_FBPA_CAP0_REPLAY_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CAP0_REPLAY_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_PARITY 0x009A0510 /* RW-4R */ #define NV_PFB_FBPA_PARITY__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_DATALO 3:0 /* R-IVF */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_DATALO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_DATAHI 7:4 /* R-IVF */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_DATAHI_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_CMD 8:8 /* R-IVF */ #define NV_PFB_FBPA_PARITY_IB_FABRIC_ERROR_CMD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_PARITY_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_PARITY_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_PARITY_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x009A0554 /* RW-4R */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_BA_WT0 0x009A0514 /* RW-4R */ #define NV_PFB_FBPA_BA_WT0__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT0_INTERCEPT 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT0_INTERCEPT_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT0_1 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT0_1_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT0_2 29:20 /* RWBVF */ #define NV_PFB_FBPA_BA_WT0_2_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT1 0x009A0518 /* RW-4R */ #define NV_PFB_FBPA_BA_WT1__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT1_3 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT1_3_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT1_4 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT1_4_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT1_5 29:20 /* RWBVF */ #define NV_PFB_FBPA_BA_WT1_5_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT2 0x009A051C /* RW-4R */ #define NV_PFB_FBPA_BA_WT2__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT2_6 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT2_6_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT2_7 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT2_7_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT2_8 29:20 /* RWBVF */ #define NV_PFB_FBPA_BA_WT2_8_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT3 0x009A0520 /* RW-4R */ #define NV_PFB_FBPA_BA_WT3__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT3_9 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT3_9_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT3_10 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT3_10_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT3_11 29:20 /* RWBVF */ #define NV_PFB_FBPA_BA_WT3_11_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT4 0x009A0524 /* RW-4R */ #define NV_PFB_FBPA_BA_WT4__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT4_12 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT4_12_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT4_13 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT4_13_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT4_14 29:20 /* RWBVF */ #define NV_PFB_FBPA_BA_WT4_14_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT5 0x009A0528 /* RW-4R */ #define NV_PFB_FBPA_BA_WT5__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_WT5_15 9:0 /* RWBVF */ #define NV_PFB_FBPA_BA_WT5_15_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA_WT5_16 19:10 /* RWBVF */ #define NV_PFB_FBPA_BA_WT5_16_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_BA 0x009A0550 /* RW-4R */ #define NV_PFB_FBPA_BA__PRIV_LEVEL_MASK 0x009A0554 /* */ #define NV_PFB_FBPA_BA_BLKACTIVITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_BA_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_BA_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_BA_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_RD 0x009A0558 /* RW-4R */ #define NV_PFB_FBPA_CRC_RD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_RD_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_RD_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_RD_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_CRC_RD_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_RD_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC_WR 0x009A055C /* RW-4R */ #define NV_PFB_FBPA_CRC_WR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_WR_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_WR_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_WR_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_CRC_WR_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_WR_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC_TRIGGER 0x009A0560 /* RW-4R */ #define NV_PFB_FBPA_CRC_TRIGGER__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_TRIGGER_STATUS 0:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_TRIGGER_STATUS_NO_ERROR 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_TRIGGER_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_TRIGGER_STATUS_ERROR 0x00000001 /* R---V */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_NUM 6:4 /* R-IVF */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_NUM_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_TRIGGER_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_CRC_TRIGGER_MODE_CONTINUOUS 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_TRIGGER_MODE_ONCE 0x00000001 /* R---V */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_MASK_SUBP0 15:12 /* RWIVF */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_MASK_SUBP0_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_MASK_SUBP1 19:16 /* RWIVF */ #define NV_PFB_FBPA_CRC_TRIGGER_BYTE_MASK_SUBP1_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_CRC_DATA0 0x009A0564 /* R--4R */ #define NV_PFB_FBPA_CRC_DATA0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_DATA0_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_DATA0_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DATA1 0x009A0568 /* R--4R */ #define NV_PFB_FBPA_CRC_DATA1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_DATA1_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_DATA1_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DATA2 0x009A056C /* R--4R */ #define NV_PFB_FBPA_CRC_DATA2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_DATA2_DATA 7:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_DATA2_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DATA2_EXPECTED_EDC 15:8 /* R-IVF */ #define NV_PFB_FBPA_CRC_DATA2_EXPECTED_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DATA2_ACTUAL_EDC 23:16 /* R-IVF */ #define NV_PFB_FBPA_CRC_DATA2_ACTUAL_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_ERROR_RATE 0x009A0570 /* RW-4R */ #define NV_PFB_FBPA_CRC_ERROR_RATE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_ERROR_RATE_LIMIT 23:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_RATE_LIMIT_1000 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_CRC_ERROR_RATE_EXCEEDED 28:28 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_RATE_EXCEEDED_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_ERROR_RATE_EXCEEDED_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_ERROR_RATE_EXCEEDED_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_CRC_ERROR_RATE_TICK_CLOCK 31:31 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_RATE_TICK_CLOCK_LTCCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_ERROR_RATE_TICK_CLOCK_MEMREF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC_TICK 0x009A0574 /* RW-4R */ #define NV_PFB_FBPA_CRC_TICK__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_TICK_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_TICK_VALUE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC_TICK_VALUE_1US 0x000002EE /* RWI-V */ #define NV_PFB_FBPA_CRC_ERROR_MAX_DELTA 0x009A0578 /* R--4R */ #define NV_PFB_FBPA_CRC_ERROR_MAX_DELTA__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_ERROR_MAX_DELTA_VALUE 23:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_ERROR_MAX_DELTA_VALUE_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0 0x009A00D0 /* RW-4R */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1 0x009A00D4 /* RW-4R */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0 0x009A00D8 /* RW-4R */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1 0x009A00DC /* RW-4R */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC 0x009A0580 /* RW-4R */ #define NV_PFB_FBPA_CRC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_CRC_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_CRC_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CRC_ERROR_DURING_RETRY 26:26 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_DURING_RETRY_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_CRC_ERROR_DURING_RETRY_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_ERROR_DURING_RETRY_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_INTERRUPT 0x009A0584 /* RW-4R */ #define NV_PFB_FBPA_CRC_INTERRUPT__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_INTERRUPT_CNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_INTERRUPT_CNT_16384 0x00004000 /* RWI-V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_CNT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_CNT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_DELTA 26:26 /* RWIVF */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_DELTA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_MAX_DELTA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_ERR_ON_RETRY 28:28 /* RWIVF */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_ERR_ON_RETRY_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_CRC_INTERRUPT_EN_ERR_ON_RETRY_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CRC_DEBUG 0x009A0588 /* RW-4R */ #define NV_PFB_FBPA_CRC_DEBUG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_ERR 0:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_ERR 1:1 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_RPL 2:2 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_RPL 3:3 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP0_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_ERR 4:4 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_ERR 5:5 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_RPL 6:6 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_RPL 7:7 /* RWIVF */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_CRC_DEBUG_SUBP1_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_RD_BYTE(i) (0x009A2400+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_RD_BYTE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_RD_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_RD_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_WR_BYTE(i) (0x009A2420+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_WR_BYTE__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_WR_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_CRC_ERROR_COUNT_WR_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_DEBUG 0x009A2440 /* RWI4R */ #define NV_PFB_FBPA_REPLAY_DEBUG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REPLAY_DEBUG_MAXRETRY 7:0 /* RWIVF */ #define NV_PFB_FBPA_REPLAY_DEBUG_MAXRETRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REPLAY_DEBUG_SUBP0_SKIPCNT 15:8 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_DEBUG_SUBP0_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_REPLAY_DEBUG_SUBP1_SKIPCNT 23:16 /* R-IVF */ #define NV_PFB_FBPA_REPLAY_DEBUG_SUBP1_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR(i) (0x009A24D4+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_RR_FIFOERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_RR_FIFOERR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_1ST 0:0 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_1ST 1:1 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_1ST 2:2 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_1ST 3:3 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_2ND 4:4 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_2ND 5:5 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_2ND 6:6 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_2ND 7:7 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_RDAT3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_1ST 8:8 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_1ST 9:9 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_1ST 10:10 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_1ST 11:11 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_2ND 12:12 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_2ND 13:13 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_2ND 14:14 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_2ND 15:15 /* RWIVF */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_RR_FIFOERR_EDC3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_REFCTRL3 0x009A24DC /* RW-4R */ #define NV_PFB_FBPA_REFCTRL3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR 0:0 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR_SRC 1:1 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR_SRC_DRAMC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL3_PBR2ABR_SRC_PWRM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR 16:16 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_THRESHOLD 20:17 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_THRESHOLD_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_SPEEDUP 24:24 /* RWIVF */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_SPEEDUP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFCTRL3_SOFTKILLPBR_SPEEDUP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_ISO_LATENCY 0x009A058C /* RW-4R */ #define NV_PFB_FBPA_ISO_LATENCY__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_ISO_LATENCY_MAX 15:0 /* RWIVF */ #define NV_PFB_FBPA_ISO_LATENCY_MAX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_ISO_LATENCY_LAST 31:16 /* RWIVF */ #define NV_PFB_FBPA_ISO_LATENCY_LAST_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_INTR_STATUS 0x009A0398 /* R--4R */ #define NV_PFB_FBPA_INTR_STATUS__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP0 0:0 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP0 1:1 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP0 2:2 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP0 3:3 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP0 4:4 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP0 8:8 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP1 16:16 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_SEC_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP1 17:17 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_DED_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_OOR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_POISON_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP1 20:20 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_ADDRERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP1 24:24 /* R-IVF */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_INTR_STATUS_AERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_OOR 0x009A03A8 /* RW-4R */ #define NV_PFB_FBPA_OOR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_OOR_COUNT_SUBP0 7:0 /* R-IVF */ #define NV_PFB_FBPA_OOR_COUNT_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP0 8:8 /* RWIVF */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP0_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_OOR_COUNT_SUBP1 23:16 /* R-IVF */ #define NV_PFB_FBPA_OOR_COUNT_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP1 24:24 /* RWIVF */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_OOR_RESET_COUNT_SUBP1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_OOR_INTR_SUBP0 29:29 /* RWIVF */ #define NV_PFB_FBPA_OOR_INTR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_OOR_INTR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_OOR_INTR_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_OOR_INTR_SUBP1 30:30 /* RWIVF */ #define NV_PFB_FBPA_OOR_INTR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_OOR_INTR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_OOR_INTR_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_OOR_INTR_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_OOR_INTR_ENABLE_OFF 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_OOR_INTR_ENABLE_ON 0x00000001 /* R---V */ #define NV_PFB_FBPA_HBM_CFG0 0x009A038C /* RW-4R */ #define NV_PFB_FBPA_HBM_CFG0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK 0:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK_BANK 1:1 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK_BANK_8 0x00000000 /* RW--V */ #define NV_PFB_FBPA_HBM_CFG0_DUAL_RANK_BANK_16 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_SCHED_PC_LIMIT 9:2 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_SCHED_PC_LIMIT_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_HBM_CFG0_SCHED_PC_LIMIT_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_SID_OVR 10:10 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_SID_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_SID_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CFG0_SID_VAL 11:11 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_SID_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_SID_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CFG0_SID1_VAL 12:12 /* RWIVF */ #define NV_PFB_FBPA_HBM_CFG0_SID1_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CFG0_SID1_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_ARB_CFG 0x009A03A0 /* RW-4R */ #define NV_PFB_FBPA_HBM_ARB_CFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_ARB_CFG_SECCNT_ARB 0:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG_SECCNT_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_ARB_CFG_SECCNT_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_ARB_CFG_MIN_BG_SECTORS 4:1 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG_MIN_BG_SECTORS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_HBM_ARB_CFG_RESIDUAL_THRESHOLD 8:5 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG_RESIDUAL_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_HBM_ARB_CFG1 0x009A03A4 /* RW-4R */ #define NV_PFB_FBPA_HBM_ARB_CFG1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_ARB_CFG1_RD_RANK_DURATION 7:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG1_RD_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_ARB_CFG1_RD_RANK_MIN_STAY 15:8 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG1_RD_RANK_MIN_STAY_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_ARB_CFG1_WR_RANK_DURATION 23:16 /* RWIVF */ #define NV_PFB_FBPA_HBM_ARB_CFG1_WR_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR 0x009A03AC /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_PIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_PIN_DQ(i) (0x00000000 + (i)) /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN_DQ__SIZE_1 128 /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN_ECC(i) (0x00000090 + (i)) /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN_ECC__SIZE_1 16 /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN_DBI(i) (0x00000080 + (i)) /* */ #define NV_PFB_FBPA_HBM_CHAR_PIN_DBI__SIZE_1 16 /* */ #define NV_PFB_FBPA_HBM_CHAR_PC 9:8 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_PC_PC0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CHAR_PC_PC1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_HBM_CHAR_PC_PC01 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_DBI 10:10 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_DBI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CHAR_ECC 11:11 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x009A03B0 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x009A03B4 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x009A03B8 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x009A03BC /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x009A03C0 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x009A03C4 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x009A03C8 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x009A03CC /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI 0x009A03D0 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC 0x009A03D4 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MAX 0x009A03D8 /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MAX__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MAX_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_MAX_V_INIT 0xFFFFFFFF /* RWI-V */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_THRESHOLD 0x009A03DC /* RW-4R */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_THRESHOLD__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_THRESHOLD_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_HBM_CHAR_COUNTER_THRESHOLD_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_RR_CTRL 0x009A03FC /* RW-4R */ #define NV_PFB_FBPA_RR_CTRL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_RR_CTRL_PC_NPC_GAP 3:0 /* RWIVF */ #define NV_PFB_FBPA_RR_CTRL_PC_NPC_GAP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_RR_CTRL_RW_GAP 7:4 /* RWIVF */ #define NV_PFB_FBPA_RR_CTRL_RW_GAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK 0x009A08FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_FBIO_BROADCAST 0x009A0590 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BROADCAST__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_SDDR23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_DDR3 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MODE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MODE_LATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MODE_EARLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_SEND_A14_A15_ON_ABI 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_EYE_MASK 7:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_EYE_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_EYE_MASK_LOWER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_EYE_MASK_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_EYE_MASK_UPPER 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GENERIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GENERIC2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR3_BGA136 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_SDDR3_BGA100 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR5_GT215_COMP 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR1 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_X8 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR_X8 0x0000000B /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_SDDR4_BGA78 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_HBM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_SDDR4_3DS 0x0000000E /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_USE_EXTENDED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_MODE 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_SUBP 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_GEARDOWN 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_GEARDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_2T_CMD_GEARDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_G5X_CMD_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_G5X_CMD_MODE_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_G5X_CMD_MODE_G5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_MODE 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_RX_RCV_SEL 22:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_RX_RCV_SEL_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_RX_RCV_SEL_LOW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_RX_RCV_SEL_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_PAM4_RX_RCV_SEL_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_OB_FABRIC_DBI 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_OB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_OB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_IB_FABRIC_DBI 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_IB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_IB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT 29:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_LPDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_1 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_2 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_IC 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_4 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6X_BGA180_MODE_1 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_90D 0x0000000B /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_270D 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI 0x009A0594 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_ON 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_MODE_SSO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_OUT_MODE_LP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_IN_ON 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_IN_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG_DBI_IN_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CHANNELCFG 0x009A0598 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CHANNELCFG__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO_CHANNELCFG_CHANNEL_ENABLE 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CHANNELCFG_CHANNEL_ENABLE_32_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CHANNELCFG_CHANNEL_ENABLE_64_BIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST1 0x009A059C /* RW-4R */ #define NV_PFB_FBPA_FBIO_BROADCAST1__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_INTERP 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_INTERP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_INTERP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RCVR 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RCVR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RCVR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RX_CLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RX_CLK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BROADCAST1_POWER_EN_RX_CLK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5 0x009A0604 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CONFIG5__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CONFIG5_CMD_PAD_DISABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG5_CMD_PAD_DISABLE_NOT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_CMD_PAD_DISABLE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V1P2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V1P8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V2P1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_VDDP_MODE_V2P4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_ATDAT_FORCE 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG5_ATDAT_FORCE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CONFIG5_ATDAT_FORCE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_PU40_MODE_CMD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CONFIG5_PU40_MODE_CMD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CONFIG5_PU40_MODE_CMD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SPARE 0x009A060C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE__PROD_C_DDR1 0x00300000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE__PROD_C_DDR2 0x00300000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE__PROD_C_DDR3 0x00300001 /* RW--V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE__PROD_C_DDR4 0x80300001 /* RW--V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE__PROD_C_DDR5 0x80300001 /* RW--V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_DELAYED_CALDRV_SDDR 1:1 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_E_SER_FORCE_ONE 4:4 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_FORCE_MA_SDR 7:7 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_FORCE_MA_SDR_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_FORCE_MA_SDR_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_PAD_CALIBRATION 11:11 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_PAD_CALIBRATION_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_PAD_CALIBRATION_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_SERIALIZER 12:12 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_SERIALIZER_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_SERIALIZER_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_EN 25:25 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_EN_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_EN_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB 26:26 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV 27:27 /* */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_FBIO_SPARE_VALUE_CLK_OBS_CLK_SEL 29:28 /* */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN 0x009A0610 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN 0x009A0614 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR 0x009A061C /* RW-4R */ #define NV_PFB_FBPA_FBIO_ASR__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_ASR_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR_VAUXC 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR_VCLAMP 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VAUXP 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VAUXC 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VCLAMP 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ASR_BRICK_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL 0x009A0670 /* RW-4R */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_FILTER_BITS 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_FILTER_BITS_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_START_TRM 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_START_TRM_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_END_COUNT 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_END_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_LEGACY_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_LEGACY_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_IGNORE_START 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_CALIBRATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS 0x009A0674 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS 0x009A0678 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL 0x009A067C /* RW-4R */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DLCELL 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DLCELL 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_CORS_TRIMMER 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_CORS_TRIMMER 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_MDDLL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_WDQS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_ADR_DDLL 0x009A0694 /* RW-4R */ #define NV_PFB_FBPA_FBIO_ADR_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP0_ADR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP0_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP1_ADR0 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP1_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL 0x009A0698 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL 0x009A069C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL 0x009A06A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL 0x009A06A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL 0x009A06A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL 0x009A06AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL 0x009A06B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL 0x009A06B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL 0x009A06B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL 0x009A06BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1 0x009A0ED8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1 0x009A0EDC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE 0x009A0700 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_BYTE_VREF_MODE_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL 0x009A0704 /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_IB 7:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_IB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_OB 15:8 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_OB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_DQDQS 23:16 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_DQDQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_QUSE 31:24 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_DDLL_QUSE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC 0x009A0708 /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_MODE 1:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE 3:2 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_DAT 6:4 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_DAT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_DQS 10:8 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_VREF_DQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT 20:16 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1 0x009A070C /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE 31:24 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x009A0710 /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x009A0714 /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3 0x009A0718 /* -W-4R */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE 2:0 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE 5:3 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE 8:6 /* -WIVF */ #define NV_PFB_FBPA_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK 0x009A0650 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CML_CLK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CML_CLK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_PREDI 14:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_PREDI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK0_ON 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK0_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK0_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK1_ON 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK1_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK1_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK_RUN 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CML_CLK_CLK_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_POLARITY 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK_POLARITY_NORMAL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK_POLARITY_INVERT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DELAY 0x009A065C /* RW-4R */ #define NV_PFB_FBPA_FBIO_DELAY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DELAY_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DELAY_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DELAY_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_DELAY_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DELAY_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DELAY_PRIV_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_DELAY 0x009A08E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DELAY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DELAY_CMD_PRIV_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER 0x009A08E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER_PATTERN 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER_PATTERN_INIT 0x33330F0F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_QDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_DDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6x 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_FBIO_CML_WCK 0x009A066C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CML_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CML_WCK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_TX_DRVDN 19:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_TX_DRVUP 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_E_PU40 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_E_PU40_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_E_PU40_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_FREEZE 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL 0x009A0504 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_FBIO_CAL_CFG_DRVDLY 31:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_CFG_DRVDLY_A 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB 0x009A0508 /* RW-4R */ #define NV_PFB_FBPA_CAL_TRNG_ARB__PRIV_LEVEL_MASK 0x009A0168 /* */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_1CYCLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_2CYCLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_3CYCLE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_4CYCLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_SEL_TRNG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_SEL_CAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_CAL_TRNG_ARB_SKIP_CNT_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR 0x009A0720 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVR_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF 0x009A0724 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVF_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT 0x009A0728 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_DRVT_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR 0x009A0730 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_SLWR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS 0x009A0738 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVR 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVF 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVF_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVF_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVF_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_BYP_CS_DRVF_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0 0x009A07D0 /* RW-4R */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD0_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD0_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD0_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD1 3:2 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD1_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD1_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD1_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD2 5:4 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD2_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD2_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD2_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD3 7:6 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD3_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD3_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD3_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD4 9:8 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD4_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD4_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD4_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD5 11:10 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD5_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD5_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD5_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD6 13:12 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD6_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD6_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD6_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD7 15:14 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD7_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD7_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD7_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD8 17:16 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD8_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD8_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD8_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD9 19:18 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD9_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD9_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD9_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD10 21:20 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD10_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD10_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD10_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD11 23:22 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD11_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD11_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD11_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD12 25:24 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD12_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD12_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD12_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD13 27:26 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD13_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD13_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD13_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD14 29:28 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD14_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD14_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD14_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD15 31:30 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD15_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD15_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL0_CMD15_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1 0x009A07D4 /* RW-4R */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD16 1:0 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD16_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD16_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD16_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD17 3:2 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD17_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD17_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD17_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD18 5:4 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD18_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD18_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD18_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD19 7:6 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD19_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD19_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD19_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD20 9:8 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD20_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD20_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD20_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD21 11:10 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD21_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD21_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD21_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD22 13:12 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD22_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD22_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD22_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD23 15:14 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD23_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD23_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD23_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD24 17:16 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD24_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD24_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD24_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD25 19:18 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD25_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD25_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD25_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD26 21:20 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD26_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD26_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD26_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD27 23:22 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD27_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD27_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD27_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD28 25:24 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD28_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD28_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD28_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD29 27:26 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD29_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD29_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD29_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD30 29:28 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD30_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD30_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD30_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD31 31:30 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD31_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD31_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL1_CMD31_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2 0x009A07D8 /* RW-4R */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD32 1:0 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD32_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD32_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD32_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD33 3:2 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD33_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD33_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD33_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD34 5:4 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD34_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD34_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD34_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD35 7:6 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD35_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD35_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD35_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD36 9:8 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD36_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD36_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD36_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD37 11:10 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD37_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD37_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD37_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD38 13:12 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD38_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD38_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD38_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD39 15:14 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD39_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD39_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD39_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD40 17:16 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD40_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD40_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD40_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD41 19:18 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD41_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD41_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD41_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD42 21:20 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD42_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD42_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD42_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD43 23:22 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD43_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD43_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD43_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD44 25:24 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD44_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD44_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD44_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD45 27:26 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD45_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD45_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD45_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD46 29:28 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD46_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD46_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD46_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD47 31:30 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD47_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD47_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL2_CMD47_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3 0x009A07E8 /* RW-4R */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD48 1:0 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD48_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD48_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD48_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD49 3:2 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD49_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD49_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD49_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD50 5:4 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD50_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD50_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD50_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD51 7:6 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD51_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD51_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD51_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD52 9:8 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD52_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD52_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD52_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD53 11:10 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD53_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD53_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD53_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD54 13:12 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD54_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD54_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD54_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD55 15:14 /* RWIVF */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD55_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD55_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_CAL_ADR_DRV_SEL3_CMD55_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CALCFG 0x009A07E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CALCFG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CALCFG_CMD_STEP 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CALCFG_CMD_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CALCFG_CMD_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CALCFG_CK_STEP 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CALCFG_CK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CALCFG_CK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CALCFG_WCK_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CALCFG_WCK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CALCFG_WCK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CALCFG_BGCAL_FREEZE 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CALCFG_BGCAL_FREEZE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x009A1EC8 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x009A1ECC /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x009A1ED0 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x009A1ED4 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x009A1ED8 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x009A1EDC /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x009A1EE0 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x009A1EE4 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x009A1EE8 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x009A1EEC /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x009A1EF0 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x009A1EF4 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x009A1EF8 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x009A1EFC /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x009A1F00 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x009A1F04 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x009A1F08 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x009A1F0C /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x009A1F10 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x009A1F14 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x009A1F18 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x009A1F1C /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x009A1F20 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x009A1F24 /* RW-4R */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK 0x009A1F28 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_CLK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_CLK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DRVDN_BYP_SEL_INI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML 0x009A1F34 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_CLK_VML_SEL_VML 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK 0x009A1F2C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_WCK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML 0x009A1F38 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_SEL_CML 0x0 /* RW--V */ #define NV_PFB_FBPA_FBIO_CAL_WCK_VML_SEL_VML 0x1 /* RWI-V */ #define NV_PFB_FBPA_PRI_FBPA_CG 0x009A0000 /* RWE4R */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_DLY_CNT__PROD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_PRI_FBPA_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_PRI_FBPA_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_FBPA_PRI_FBPA_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_PRI_FBPA_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_PRI_FBPA_CG1 0x009A0004 /* RWE4R */ #define NV_PFB_FBPA_PRI_FBPA_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_FBPA_PRI_FBPA_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_PRI_FBPA_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_PRI_FBPA_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8 0x009A0800 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG8__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG8_RFU 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU__PROD_C_DDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INTERP_EDC_PWRD_ENABLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INTERP_EDC_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT 2:2 /* */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_CFG8_RFU_RDQS_RCVR_SEL_XOR 5:4 /* */ #define NV_PFB_FBPA_FBIO_CFG10 0x009A0808 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG10__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_DQ 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_RDQS 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_RDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_RDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_WDQS 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_CMD 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPD_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_DQ 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_RDQS 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_RDQS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_RDQS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_WDQS 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WKPU_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_DQ_TERM_MODE 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_DQ_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_DQ_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_DQ_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_DQ_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_TERM_MODE 23:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WDQS_TERM_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_WDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_WDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_WDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_E_RDQS_DIFF_MODE 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_E_RDQS_DIFF_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_E_RDQS_DIFF_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_SRC_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_SRC_SEL_RDQS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG10_RDQS_SRC_SEL_WDQS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_E_INTERNAL_VREF 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG10_E_INTERNAL_VREF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG10_E_INTERNAL_VREF_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BRLSHFT 0x009A0820 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BRLSHFT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BRLSHFT_CMD 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BRLSHFT_CMD_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD 0x009A0824 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG_PWRD__PRIV_LEVEL_MASK 0x009A086C /* */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CML_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CML_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CML_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_RDQS_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_PWRD 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_TX_PWRD 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_ON 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CLK_TX_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CLK_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CLK_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCK_TX_PWRD 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCK_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCKB_TX_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCKB_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DIFFAMP_PWRD 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DIFFAMP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DIFFAMP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CK_DIGDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11 0x009A0828 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG11__PRIV_LEVEL_MASK 0x009A086C /* */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_S_MACRO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_D_MACRO 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_S_PAD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_D_PAD 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11_LOOPBK_MODE_I_PAD 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG11_CK_DEEPLOOP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_CK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_E_LPBK_INTERFACE_MODE 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_E_LPBK_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_E_LP_MODE_CMD 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_E_LP_MODE_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_WCK_DEEPLOOP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_WCK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_VEND_ID_C0_LOAD_EN 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_VEND_ID_C0_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_VEND_ID_C1_LOAD_EN 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_VEND_ID_C1_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_PARALLEL_LPBK_MODE_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_PARALLEL_LPBK_MODE_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG11_CLAMP_VAL 23:23 /* R-IVF */ #define NV_PFB_FBPA_FBIO_CFG11_CLAMP_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CFG11_CONFIG_CMD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG11_CONFIG_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12 0x009A082C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG12__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG12_PVT_CODE_BYTE_C0_RB 10:8 /* R--VF */ #define NV_PFB_FBPA_FBIO_CFG12_PVT_CODE_BYTE_C1_RB 13:11 /* R--VF */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_INTRP_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_INTRP_8UI_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_INTRP_8UI_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_STEP16 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_STEP8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_STEP4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_STEP2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_STEP1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CYA_SELECT_NO_STEP 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_TX_EN_EARLY 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_TX_EN_EARLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_TAPERED_START 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_TAPERED_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_WCK_TAPERED_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CAP 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_INTERP_CAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_CMD_BR8_DELAY 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG12_CMD_BR8_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG12_CMD_BR8_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG12_CMD_BR8_DELAY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1 0x009A0830 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_FBIO_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_WPRE_TWO 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_WPRE_TWO_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_WPRE_TWO_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_WPOST 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_WPREPOST_DQ_VALUE 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_WPREPOST_DQ_VALUE_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_WPREPOST_DQ_VALUE_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_WDQS_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_WDQS_MODE_WDQS_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_WDQS_MODE_WDQS_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_HOLD_DQ 10:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_HOLD_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_SETUP_DQ 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_SETUP_DQ_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_SETUP_STR 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_TX_EN_SETUP_STR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_CMD_BRLSHFT 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_CMD_BRLSHFT_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_CMD_BRLSHFT_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_ON 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_SHORT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_NORMAL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_LONG 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_QUSE_FORCE_HIGH 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_QUSE_FORCE_HIGH_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_QUSE_FORCE_HIGH_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_BIT2 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_EXTENDED_QUSE_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_PADMACRO_SYNC 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_PADMACRO_SYNC_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_PADMACRO_SYNC_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_RCV_CLOCKING 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_RCV_CLOCKING_STROBE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_RCV_CLOCKING_CONTINUOUS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_CLK_ASSERT 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_TX_CLK_ASSERT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_TX_CLK_ASSERT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_IB_PMACRO_PTR_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RUN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RESET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_PADMACRO_RESET 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_PADMACRO_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_INTERP_RESET 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_INTERP_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG1_DDLL_INIT 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG1_DDLL_INIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CFG1_DDLL_INIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SPARE2 0x009A0834 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SPARE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SPARE2_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SPARE2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VEND_ID_C0 0x009A0838 /* R--4R */ #define NV_PFB_FBPA_FBIO_VEND_ID_C0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VEND_ID_C0_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VEND_ID_C0_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VEND_ID_C1 0x009A083C /* R--4R */ #define NV_PFB_FBPA_FBIO_VEND_ID_C1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VEND_ID_C1_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VEND_ID_C1_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CMOS_CLK 0x009A0860 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMOS_CLK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_DLY_CK0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_DLY_CK0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_DLY_CK1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_DLY_CK1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMOS_CLK_SEL_CMOS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK 0x009A0864 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK 0x009A0868 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL 0x009A0870 /* RW-4R */ #define NV_PFB_FBPA_FBIO_RCV_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE4 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE5 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE6 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE7 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_RCV_CTRL_LANE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG7 0x009A0874 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG7__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG7_CMD_RCV_CTRL 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG7_CMD_RCV_CTRL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG7_CMD_OB_SYNC_DLY 30:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG7_CMD_OB_SYNC_DLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL 0x009A0890 /* RW-4R */ #define NV_PFB_FBPA_FBIO_PWR_CTRL__PRIV_LEVEL_MASK 0x009A086C /* */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_OB_BYTE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_BYTE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_CMD 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WCK 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_TRAINING_PRIV 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_TRAINING_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_FABRIC_FGCG 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_BLCG_BYTE 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF 21:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF 25:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL 0x009A0894 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF 9:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF 14:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_31 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF 19:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 29:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1 0x009A0898 /* RW-4R */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CG 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_DQ_DISABLE_ASR 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_DQ_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_DISABLE_ASR 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_WCK_DISABLE_ASR 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_WCK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CK_DISABLE_ASR 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L 0x009A08C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H 0x009A08CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL 0x009A08D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CLK_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK0_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK0_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK0_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK0_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK1 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK1_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK1_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK1_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIO_CLK_CTRL_CLK1_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM 0x009A08D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM_BYTE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM_BYTE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM_CMD 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_LOOPBK_TRIM_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY 0x009A08D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_PARITY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE0 1:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE1 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE1 3:3 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE2 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE2 5:5 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE2_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE3 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE3 7:7 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE3_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE4 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE4 9:9 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE4_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE5 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE5 11:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE5_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE6 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE6 13:13 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE6_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE7 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PARITY_ENABLE_LANE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE7 15:15 /* R-IVF */ #define NV_PFB_FBPA_FBIO_PARITY_ERROR_LANE7_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY 0x009A08DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_PARITY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PARITY_ERR 1:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR 2:2 /* R-IVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PARITY_ERR 4:4 /* R-IVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR 5:5 /* R-IVF */ #define NV_PFB_FBPA_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG 0x009A0E00 /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_CFG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE_CML 8:8 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_ENABLE_CML_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_READY 16:16 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_LOCK 17:17 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSA 24:24 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSD 25:25 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_CML 26:26 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_CML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_4PHCML 27:27 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_4PHCML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_DLL 28:28 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_DLL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_600 29:29 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_600_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_600_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_PLL_600_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF 0x009A0E04 /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_COEFF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_COEFF_NDIV_INIT 0x00000014 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_NDIV_MIN 0x00000014 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_SEL_DIVBY2 28:28 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_COEFF_SEL_DIVBY2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_SEL_DIVBY2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_COEFF_SEL_DIVBY2_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_DRAMPLL_CTRL 0x009A0E08 /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_PLL_FREQLOCK 28:28 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_PLL_FREQLOCK_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_PLL_FREQLOCK_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_PLL_FREQLOCK_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_MON_TESTOUT 31:29 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_MON_TESTOUT_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_ENABLE_BG 22:22 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG2 0x009A0E0C /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS 0x009A0E14 /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_READY 0:0 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_LOCK 1:1 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK 2:2 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_READY 3:3 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_LOCK 4:4 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK 5:5 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_READY 6:6 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_LOCK 7:7 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK 8:8 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_READY 9:9 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_LOCK 10:10 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK 11:11 /* R-IUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_SETUP2 19:16 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_DUAL_STATUS_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3 0x009A0E18 /* RW-4R */ #define NV_PFB_FBPA_DRAMPLL_CFG3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DEBUG_DLL 7:0 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DEBUG_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_KCP_DLL 9:8 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_KCP_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DELAYGAIN 10:10 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DELAYGAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_BYPASS_ASYNC 12:12 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_BYPASS_ASYNC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DLL_ENABLE 14:14 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_DLL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_SEL_DLLCLK 15:15 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_SEL_DLLCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_TESTSEL 26:25 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_TESTSEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_SPEEDUP 28:28 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_SPEEDUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_DRAMPLL_CFG3_TESTEN 29:29 /* RWIUF */ #define NV_PFB_FBPA_DRAMPLL_CFG3_TESTEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG 0x009A0E20 /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_CFG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_SYNC_MODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_ENB_LCKDET_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_ENB_LCKDET_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_READY 16:16 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_LOCK 17:17 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSA 24:24 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSD 25:25 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_CML 26:26 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_4PHCML 27:27 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_DLL 28:28 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_REFMPLL_CFG_PLL_600 29:29 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF 0x009A0E24 /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_COEFF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_COEFF_NDIV_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_COEFF_NDIV_MIN 0x00000028 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CTRL 0x009A0E28 /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CTRL_MON_TESTOUT 31:29 /* R--UF */ #define NV_PFB_FBPA_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2 0x009A0E2C /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SDM 8:8 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SSC 9:9 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SSC_BYP 10:10 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SSC_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SSC_BYP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SSC_BYP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER 11:11 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SDM_RESET 12:12 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER2 13:13 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER2_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SSD_EN_DITHER2_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_REFMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_SSD0 0x009A0E30 /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_SSD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_SSD0_SDM_SSC_STEP 15:0 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_SSD0_SDM_DIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_SSD0_SDM_DIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_SSD1 0x009A0E34 /* RW-4R */ #define NV_PFB_FBPA_REFMPLL_SSD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_REFMPLL_SSD1_SDM_SSC_MAX 15:0 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_REFMPLL_SSD1_SDM_SSC_MIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_REFMPLL_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK 0x009A2030 /* RW-4R */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x009A2034 /* RW-4R */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_GSP_SEC2_IFF_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK 0x009A2038 /* RW-4R */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_TRAINING_ADR(i) (0x009A0900+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_ADR__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_ADR__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_ADR_ROW 15:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADR_EXTBANK 27:27 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADR_EXTBANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADR_BANK 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD(i) (0x009A0910+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_CMD__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_CMD__PRIV_LEVEL_MASK 0x009A2038 /* */ #define NV_PFB_FBPA_TRAINING_CMD_ADR 16:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_WCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_WCK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_WCK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_RD 18:18 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_RD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_WR 19:19 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_WR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE 21:21 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE_PRIME 22:22 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE_PRIME_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_QUSE_PRIME_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_CHAR_ENGINE 23:23 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_CHAR_ENGINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_CHAR_ENGINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_PERIODIC 24:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_RW_LEVEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_RW_LEVEL_BYTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_RW_LEVEL_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_STROBE 27:27 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_STROBE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_STROBE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_CONTROL 29:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_CONTROL_TRIMMER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_CONTROL_DLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_CONTROL_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_CONTROL_DLCELL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CMD_STEP 30:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_STEP_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_TRAINING_CMD_GO 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CMD_GO_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_TRAINING_DP(i) (0x009A0918+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_DP__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DP__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DP_LO 15:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DP_LO_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DP_HI 31:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DP_HI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD(i) (0x009A0920+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_DP_CNTD__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DP_CNTD__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_DBI 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_DBI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_EDC 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_EDC_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_SEL 8:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_SEL_RD 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_SEL_WR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_SEL_LEGACY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DP_CNTD_SEL_CHAR_ENGINE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL(i) (0x009A09C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0(i) (0x009A0938+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR4 19:16 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR4_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR5 23:20 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR5_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR6 27:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR6_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR7 31:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR7_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ0_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1(i) (0x009A0940+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR8 3:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR8_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR9 7:4 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR9_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR10 11:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR10_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR11 15:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR11_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR12 19:16 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR12_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR13 23:20 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR13_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR14 27:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR14_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR15 31:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR15_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ1_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2(i) (0x009A0948+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR16 3:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR16_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR17 7:4 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR17_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR18 11:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR18_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR19 15:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR19_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR20 19:16 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR20_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR21 23:20 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR21_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR22 27:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR22_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR23 31:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR23_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ2_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3(i) (0x009A0950+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR24 3:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR24_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR25 7:4 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR25_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR26 11:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR26_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR27 15:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR27_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR28 19:16 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR28_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR29 23:20 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR29_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR30 27:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR30_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR31 31:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR31_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_DQ3_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0(i) (0x009A0958+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_EDC_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR0 19:16 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR1 23:20 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR2 27:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR3 31:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC0_DBI_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1(i) (0x009A0960+(i)*4) /* R--4A */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR0 9:8 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR0_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR0_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR1 11:10 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR1_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR1_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC0 13:12 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC0_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC0_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC0_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC1 15:14 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC1_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC1_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC1_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR2 25:24 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR2_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR2_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR3 27:26 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR3_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_ERR3_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC2 29:28 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC2_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC2_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC2_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC3 31:30 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC3_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC3_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_DEBUG_MISC1_WCK_EDC3_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR(i) (0x009A0968+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ADR 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ADR_ACT_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ADR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_DP 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_DP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_DP_TRAIN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_DP_CHAR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ACT_ADR 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ACT_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATTERN_PTR_ACT_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TIMING 0x009A0970 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_TIMING__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_TIMING_ADRTRM_SETTLE 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING_ADRTRM_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING_ADRTRM_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TIMING_ADRTRM_FLUSH 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING_ADRTRM_FLUSH_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING_VREF_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING_VREF_SETTLE_INIT 0x0000006E /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING_INTRPLTR_SETTLE 29:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING_INTRPLTR_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING_INTRPLTR_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TIMING2 0x009A09C8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_TIMING2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_TIMING2_PRIV_DELAY 4:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING2_PRIV_DELAY_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING2_APPLY_DELAY 12:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING2_APPLY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TIMING3 0x009A2050 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_TIMING3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_TIMING3_TVREFD 9:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TIMING3_TVREFD_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL 0x009A2054 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_MIN_INIT 0x00000038 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_MAX_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_STATUS 0x009A0974 /* R--4R */ #define NV_PFB_FBPA_TRAINING_STATUS__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP0_STATUS 1:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP0_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP0_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP0_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP0_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP1_STATUS 3:2 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP1_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP1_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP1_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_TRAINING_STATUS_SUBP1_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_TRAINING_CTRL 0x009A0978 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CTRL_FAST_UPDATES 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_FAST_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_FAST_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_ASR_FAST_EXIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_ASR_FAST_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_ASR_FAST_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_DELAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_DELAY_2UI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_DELAY_4UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_ASYNC_UPDATES 3:3 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_ASYNC_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_ASYNC_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_DFE_OVERRIDE 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_DFE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_DFE_OVERRIDE_FORCE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE_CLEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_EXTENDED_RW_OFFSET 6:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_EXTENDED_RW_OFFSET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_EXTENDED_RW_OFFSET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_G5X_EDC_TR_MODE 7:7 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_G5X_EDC_TR_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_G5X_EDC_TR_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_VREF_TRAINING 8:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_VREF_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_VREF_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_TRAINING 9:9 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_CORS_INTRPLTR_TRAINING 10:10 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_FINE_INTRPLTR_TRAINING 11:11 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_TRIMMER_TRAINING 12:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_TRIMMER_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_TRIMMER_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_STOP_CLOCKS 13:13 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_STOP_CLOCKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_STOP_CLOCKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_EARLY_FLIP 14:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_EARLY_FLIP_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_EARLY_FLIP_DIABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0 15:15 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_CTRL_STALL_CMDQ 17:17 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_STALL_CMDQ_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_STALL_CMDQ_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_QUICK 18:18 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_DOUBLE_CORS_RANGE 19:19 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_DOUBLE_CORS_RANGE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_DOUBLE_CORS_RANGE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_RD 20:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_WR 21:21 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_FIRST_PARTIAL_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_PADS 23:23 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_PADS_FOUR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_WCK_PADS_EIGHT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL 0x009A097C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_START_WAIT 10:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_START_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_START_EN_WAIT 11:11 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_START_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_START_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_FINISH_WAIT 26:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_FINISH_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT 27:27 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_REFRESH 28:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_REFRESH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_REFRESH_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_WAIT_IDLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_WAIT_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_LEGACY_CTRL_WAIT_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2 0x009A2040 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CTRL2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CTRL2_USE_RD_DBI_EXPECTED 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_SWEEP_PHASE 1:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_SWEEP_PHASE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_SWEEP_PHASE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_USE_BL16 2:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_USE_BL16_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_USE_BL16_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_WR 3:3 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_SHIFT_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_CORS_STEP_OVERRIDE 5:5 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_CORS_STEP_OVERRIDE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_CORS_STEP_OVERRIDE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_WR 6:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_RD 7:7 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_INV_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_RD 8:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_WR 9:9 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_PI_OFFSET_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_DCC 13:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_DCC_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_DCC_HOLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_DCC_TRACK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_QUICK_WCK 14:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_QUICK_WCK_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_QUICK_WCK_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_8UI_MODE_G6 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL2_WCK_8UI_MODE_G6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL 0x009A2070 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_BS 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_BS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_BS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_CORS 1:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_CORS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALT_CORS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALF_FBPA 2:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALF_FBPA_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_HALF_FBPA_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_RX_CAPTURE 3:3 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_RX_CAPTURE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_RX_CAPTURE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD 4:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_BS_FOR_CA_TR 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_MISC_CTRL_BS_FOR_CA_TR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TAG 0x009A0A00 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_TAG__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_TAG_TAG 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TAG_TAG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL 18:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL_ALWAYS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL_GREATER_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL_GREATER_BYTE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL_GREATER_DOUBLE_BYTE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TAG_STORE_OPTIMAL_GREATER_DRAM 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TAG_FIRST_TAG 30:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TAG_FIRST_TAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TAG_FIRST_TAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_TAG_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_TAG_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_TAG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM 0x009A0A04 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_PATRAM__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_CHAR_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_CHAR_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_CHAR_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_CHAR_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_CHAR_MAX_MAX 0x0000005F /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_BURST_CNT 22:15 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_BURST_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_INV_EN 23:23 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_INV_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_INV_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_PATTERN_LEN 26:25 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS7 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS11 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS23 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_DUAL_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_DUAL_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_DUAL_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_ACCESS_UPPER32 29:29 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_ACCESS_UPPER32_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_ACCESS_UPPER32_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_USE_RESET_LAST 30:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_USE_RESET_LAST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_USE_RESET_LAST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_OVERRIDE_TRAINING 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_OVERRIDE_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_OVERRIDE_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT 0x009A0AE0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_RD 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_WR 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_PERIODIC_RD 22:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_PERIODIC_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_PERIODIC_WR 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT_PERIODIC_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2 0x009A0AE4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2_ADDR_START 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2_ADDR_START_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2_ADDR_END 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_SELECT2_ADDR_END_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER 0x009A0A08 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MAX 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_THRESHOLD 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x009A0AC0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0 1:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1 3:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3 7:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4 9:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5 11:10 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6 13:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7 15:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8 17:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9 19:18 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10 21:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11 23:22 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12 25:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13 27:26 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14 29:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15 31:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x009A0AC8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16 1:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17 3:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19 7:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20 9:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21 11:10 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22 13:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23 15:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24 17:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25 19:18 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26 21:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27 23:22 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28 25:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29 27:26 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30 29:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31 31:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x009A0AD0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0 1:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1 3:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3 7:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL 0x009A0A0C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_MODE_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_MODE_SWEEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_SWEEP_START 2:2 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_SWEEP_START_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_SWEEP_START_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_START_COUNT 3:3 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_START_COUNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_START_COUNT_ACCUMULATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_STOP_ON_ERROR 4:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_STOP_ON_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_STOP_ON_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_REFRESH 5:5 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_HOLD_TRAFFIC 7:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_AFTER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_ALWAYS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_NUM_BANKS 9:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_NUM_BANKS_1 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_NUM_BANKS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_FUNC_MTA 11:11 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_FUNC_MTA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_FUNC_MTA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_DBI_THRESHOLD 14:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_DBI_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_PATTERN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_DATA 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN 29:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ(i) (0x00000001 + (i)) /* */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ__SIZE_1 31 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI0 0x00000020 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI1 0x00000021 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI2 0x00000022 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC0 0x00000024 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC3 0x00000027 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC0 0x00000028 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC1 0x00000029 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC2 0x0000002A /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC3 0x0000002B /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_CTRL_ANALYSIS_PIN_ALL 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST 0x009A0A10 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST_COUNT_1BANK_LIMIT 0x00000100 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST_COUNT_2BANK_LIMIT 0x00000200 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BURST_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_TURN 0x009A0A14 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_TURN__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_TURN_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_TURN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_TURN_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL 0x009A0A18 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_MIN 11:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_MAX 23:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_INTRPLTR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_DDLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_TRIMMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_INTRPLTR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_TRIMMER 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_DDLL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_TRIMMER 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_DDLL 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_INTRPLTR 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL 0x009A0AD8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_MIN 4:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_MAX 9:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_MAX_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_MIN 14:11 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_MIN_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_MAX 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_MAX_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_PREA 21:21 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_PREA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_PREA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_RANK 22:22 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_A_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_RANK 23:23 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_SET_B_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_REFA 24:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_REFA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL_REFA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2 0x009A0ADC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT 31:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_FOREVER 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL 0x009A09CC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ADR_SETTING 9:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ADR_SETTING_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ADR_MAX 20:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ADR_MAX_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ENABLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_TADR_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL 0x009A09D0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL 0x009A09D4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_MIN_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL 0x009A0984 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_X8_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_X8_MODE_BOTH 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_X8_MODE_RISING_ONLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_X8_MODE_FALLING_ONLY 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_MIRROR 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_MIRROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_MIRROR_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_MIRROR_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_MIRROR_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_REFRESH 7:7 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_REF_CNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_REF_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_1TCK 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_3TCK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_5TCK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_31TCK 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_SKIP_CNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT 31:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL 0x009A0988 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x009A09D8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX_INIT 0x000000F0 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL 0x009A09DC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_DDLL_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_TRIMMER_CTRL 0x009A09E0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_TRIMMER_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_TRIMMER_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x009A098C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER 23:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16 31:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x009A0A1C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP 29:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_OPTIMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT 0x009A0990 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MIN 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MAX 31:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_WCK_EDC_LIMIT_LATE_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL 0x009A09F4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL 0x009A09F8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_MIN_INIT 0x000000D8 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL 0x009A09FC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_BURST_COUNT 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_QUSE_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL 0x009A0AE8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING 28:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_RPT_MODE 29:29 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_RPT_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL_RPT_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2 0x009A0AEC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_BURST_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3 0x009A0AFC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX 6:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR 0x009A0AF4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_MODE 2:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_MODE_SERIAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_MODE_PARALLEL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_MODE_STAGGER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PATTERN 3:3 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PATTERN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PATTERN_CUSTOM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DRAM_DEVICE 5:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DRAM_DEVICE_X4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DRAM_DEVICE_X8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DRAM_DEVICE_X16 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DRAM_DEVICE_X32 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PAGE_SELECT 7:6 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_0 9:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_0_MPR0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_0_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_0_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_0_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_1 11:10 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_1_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_1_MPR1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_1_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_1_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_2 13:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_2_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_2_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_2_MPR2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_2_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_3 15:14 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_3_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_3_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_3_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_READ_ADR_3_MPR3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_RPT_ORDER 16:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_RPT_ORDER_MPR_RPT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_RPT_ORDER_RPT_MPR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA 0x009A0AF8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR0_DEFAULT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR1 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR1_DEFAULT 0x00000033 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR2 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR2_DEFAULT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR3 31:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_CTRL_MPR_DATA_MPR3_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL 0x009A0994 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL_CMD_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR5_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL_CMD_CNT_DDR3_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR6X_MAX 0x0000000f /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL 0x009A0998 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_MAX_INIT 0x00000035 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_STEP_LN 26:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x009A09E4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD_INIT 0x00000013 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR_INIT 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL 0x009A099C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL 0x009A09A0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL 0x009A09E8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL 0x009A09EC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL 0x009A09A4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_TRIMMER_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL 0x009A09A8 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_AREA_BASED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_AREA_BASED_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_QUICK 30:30 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_VREF_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT 0x009A09AC /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR 23:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_TRIMMER 31:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_TRIMMER_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_ERR_LIMIT_TRIMMER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL 0x009A09B0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_EN_AVG 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL_EN_AVG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL 0x009A09F0 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2 0x009A09B4 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1 16:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3 0x009A2048 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL 0x009A204C /* RW-4R */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL_EDC_TRACKING_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME 29:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL 0x009A2044 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_AREA_BASED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x009A0A20+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x009A0A28+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x009A0A30+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x009A0A38+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x009A0A40+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x009A0A48+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x009A0A50+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x009A0A58+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x009A0A60+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x009A0A68+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x009A0A70+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x009A0A78+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x009A0A80+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x009A0A88+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC(i) (0x009A0A90+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_IB_MISC_EDC3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x009A0A98+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x009A0AA0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x009A0AA8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x009A0AB0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC(i) (0x009A0AB8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_RW_OFFSET_OB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_SEED(i) (0x009A2000+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_SEED__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_SEED_VAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PATRAM_PRBS_SEED_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL 0x009A2060 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL 7:4 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_ADDR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_ABI 0x00000003 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_WCK 0x00000004 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_FULL_PERIODIC 0x00000005 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_PHASE 11:8 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_PHASE_FINE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_PHASE_CORS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_CTRL_PHASE_BS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_TRAINING_PROFILE_FULL 0x009A2064 /* R--4R */ #define NV_PFB_FBPA_TRAINING_PROFILE_FULL__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PROFILE_FULL_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_PROFILE_FULL_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_PROFILE_PHASE 0x009A2068 /* R--4R */ #define NV_PFB_FBPA_TRAINING_PROFILE_PHASE__PRIV_LEVEL_MASK 0x009A2030 /* */ #define NV_PFB_FBPA_TRAINING_PROFILE_PHASE_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_TRAINING_PROFILE_PHASE_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL 0x009A2074 /* RW-4R */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL__PRIV_LEVEL_MASK 0x009A2034 /* */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS 0:0 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_PRBS_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_PRBS_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_TRAINING_ARRAY_CTRL_PRBS_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_SW_CONFIG 0x009A2078 /* RW-4R */ #define NV_PFB_FBPA_SW_CONFIG__PRIV_LEVEL_MASK 0x009A2034 /* */ #define NV_PFB_FBPA_SW_CONFIG_PTRIM_OPT 0:0 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_PTRIM_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_PTRIM_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_SELFREF_OPT 1:1 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_SELFREF_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_SELFREF_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_MSCG_OPT 2:2 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_MSCG_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_MSCG_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_GC6_HIB_OPT 3:3 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_GC6_HIB_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_GC6_HIB_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_PA_FALCON_OPT 4:4 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_PA_FALCON_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_PA_FALCON_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT 5:5 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT 6:6 /* RWIVF */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_NOISE_CFG1 0x009A207C /* RW-4R */ #define NV_PFB_FBPA_NOISE_CFG1__PRIV_LEVEL_MASK 0x009A2034 /* */ #define NV_PFB_FBPA_NOISE_CFG1_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG1_TRAFFIC 1:1 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_TRAFFIC_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG1_TRAFFIC_MANUAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_NOISE_CFG1_MANUAL 2:2 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_MANUAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG1_ACTIVE 3:3 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG1_THROTTLE 11:4 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_THROTTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG1_BANK 31:16 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG1_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_NOISE_CFG2 0x009A2080 /* RW-4R */ #define NV_PFB_FBPA_NOISE_CFG2__PRIV_LEVEL_MASK 0x009A2034 /* */ #define NV_PFB_FBPA_NOISE_CFG2_BURST 31:0 /* RWIVF */ #define NV_PFB_FBPA_NOISE_CFG2_BURST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK 0x009A0B04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB 0x009A0B14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK 0x009A0B08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB 0x009A0B18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL 0x009A0EE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CTRL 0x009A0B0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CTRL 0x009A0B10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET 0x009A0B00 /* RW-4R */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_IB 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_IB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_OB 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_OB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_ADDR 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_WCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTRPLTR_OFFSET_WCK_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x009A0B20 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x009A0B24 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x009A0B28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x009A0B2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x009A0B30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x009A0B34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x009A0B38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x009A0B3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x009A0B40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x009A0B44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x009A0B48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x009A0B4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x009A0B50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x009A0B54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x009A0B58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x009A0B5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x009A0B60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x009A0B64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x009A0B68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x009A0B6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x009A0B70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x009A0B74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x009A0B78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x009A0B7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x009A0BC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x009A0BC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x009A0BC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x009A0BCC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x009A0BD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x009A0BD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x009A0BD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x009A0BDC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x009A0BE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x009A0BE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x009A0BE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x009A0BEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x009A0BF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x009A0BF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x009A0BF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x009A0BFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x009A0C00 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x009A0C04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x009A0C08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x009A0C0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x009A0C10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x009A0C14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x009A0C18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x009A0C1C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x009A0C20 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x009A0C24 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x009A0C28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x009A0C2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x009A0C30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x009A0C34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x009A0C38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x009A0C3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x009A0C40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x009A0C44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x009A0C48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x009A0C4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x009A0C50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x009A0C54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x009A0C58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x009A0C5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x009A0C60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x009A0C64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x009A0C68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x009A0C6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x009A0C70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x009A0C74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x009A0C78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x009A0C7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x009A0CC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x009A0CC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x009A0CC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x009A0CCC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x009A0CD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x009A0CD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x009A0CD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x009A0CDC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x009A0CE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x009A0CE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x009A0CE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x009A0CEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x009A0CF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x009A0CF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x009A0CF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x009A0CFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x009A0D00 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x009A0D04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x009A0D08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x009A0D0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x009A0D10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x009A0D14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x009A0D18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x009A0D1C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x009A0D70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x009A0D74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x009A0D78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x009A0D7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x009A0D80 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x009A0D84 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x009A0D88 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x009A0D8C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x009A0D90 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x009A0D94 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x009A0D98 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x009A0D9C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x009A0DA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x009A0DA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x009A0DA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x009A0DAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x009A0DB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x009A0DB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x009A0EE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x009A0EE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD 0x009A0D28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DLCELL 0x0000000B /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL_RANK1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_LEG_TRIM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD 0x009A0D2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL 0x009A0D30 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_TX_DCC_MODE 27:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_TX_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_PHASE0_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_PAD_CTRL_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL 0x009A0D34 /* RW-4R */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE 26:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE 30:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0 0x009A0D38 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2 0x009A0D40 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_VREF_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_E_RX_DFE 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE 10:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TX_E_DCC 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1 0x009A0DB8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2 0x009A0DBC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1 0x009A0DC0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2 0x009A0DC4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1 0x009A0DC8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2 0x009A0DCC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1 0x009A0DD0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2 0x009A0DD4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1 0x009A0DD8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2 0x009A0DDC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1 0x009A0DE0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2 0x009A0DE4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1 0x009A0DE8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2 0x009A0DEC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1 0x009A0DF0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2 0x009A0DF4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x009A05A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x009A05A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x009A05A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x009A05AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x009A05B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x009A05B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x009A05B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x009A05BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x009A05C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x009A05C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x009A05C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x009A05CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x009A05D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x009A05D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x009A05D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x009A05DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x009A05E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL 0x009A05E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD 3:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC 27:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC 0x009A0D44 /* RW-4R */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_CMD_CONFIG 13:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_CMD_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_DQ_CONFIG 23:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_DQ_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_MODE 28:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1 0x009A0D48 /* RW-4R */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC 7:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DFE_CTRL 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_DFE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_RFU 20:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL 0x009A0EB0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_RX_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL 0x009A0EB4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL 0x009A0EB8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_RX_SUBP0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_RX_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_SUBP0 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_SUBP0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_RX_SUBP1 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_RX_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_SUBP1 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_SUBP1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL 0x009A0EBC /* RW-4R */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL 0x009A0ED0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL 0x009A0EC4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CNTL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VTT_CNTL_CLKDIST_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL_CLKDIST_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2 0x009A0EC8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_SPARE 4:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_IREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL 8:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_IREF_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL 11:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CK_IREF_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_WCK_IREF_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_WCK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG 19:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG 23:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3 0x009A0EEC /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4 0x009A0EF0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5 0x009A0EF4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD 7:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD 9:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD 11:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD 15:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD 17:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_SPARE 19:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_DQ_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_SPARE 21:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VTT_CNTL5_CMD_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL 0x009A0EF8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG 0x009A0ECC /* RW-4R */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_CK 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_WCK 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_WCK_PATTERN_MASK 31:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_MISC_CONFIG_WCK_PATTERN_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2 0x009A0ED4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CML_CLK2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CML_CLK2_TX_DRVDN 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_TX_DRVUP 9:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_E_PU40 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_E_PU40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_FREEZE 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DELTA_DRVR 17:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DELTA_DRVF 21:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR 25:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF 29:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CML_CLK2_FORCE_CAL_UPDATE 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CML_CLK2_FORCE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0 0x009A1004 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_FBIO_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_LOOPBK_MODE 4:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_LOOPBK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_TX_EN_SETUP 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_TX_EN_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_BRLSHFT 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_BRLSHFT_1UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_DRAM_ECC 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_DRAM_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_DRAM_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_LEKAGE_STRENGTH 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG0_LEKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_1 0x009A1008 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_1_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_1_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_2 0x009A100C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_2_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_SPARE_2_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL 0x009A1010 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_OB_BYTE 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_BYTE 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_BLCG_BYTE 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF 17:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL 0x009A1014 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG 0x009A1018 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_CLK_CNTRL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_CLK_CNTRL_NORMAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_CLK_CNTRL_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_CLK_CNTRL_FLIP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY 0x009A1020 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR 5:5 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR 7:7 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR 9:9 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR 11:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR 13:13 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR 15:15 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY 0x009A1024 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR 4:4 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x009A103C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x009A1040 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x009A1044 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x009A1048 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x009A104C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x009A1050 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x009A1054 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x009A1058 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x009A105C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x009A1060 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x009A1064 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x009A1068 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x009A106C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x009A1070 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x009A1074 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x009A1078 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x009A107C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x009A1080 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x009A1084 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x009A1088 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x009A108C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x009A1090 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x009A1094 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x009A1098 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x009A109C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x009A10A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x003FFFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x009A10A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x000FFFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x009A10A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x009A10AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x009A10B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x009A10B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x009A10B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x009A10BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x009A10C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x009A10C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x009A10C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE 0x009A10CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_TEMP 31:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG3_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG4_BRICK_SPARE 0x009A10D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG4_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG4_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG4_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG5_BRICK_SPARE 0x009A10D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG5_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG5_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG5_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x009A10D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x009A10DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x009A10E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x009A10E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x009A10E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x009A10EC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x009A10F0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x009A10F4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x009A10F8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x009A10FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x009A1100 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x009A1104 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x009A1108 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x009A110C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x009A1110 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x009A1114 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x009A1118 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x009A111C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x009A1120 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x009A1124 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x009A1128 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x009A112C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x009A1130 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x009A1134 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x009A1138 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x009A113C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x009A1140 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x009A1144 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x009A1148 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x009A114C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x009A1150 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x009A1154 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL 0x009A1158 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY 8:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT 14:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS 20:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_START_TRM 31:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL_START_TRM_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1 0x009A11DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x009A1160 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x009A1164 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x009A1168 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x009A116C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x009A1170 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x009A1174 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x009A1178 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x009A117C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x009A1180 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE_INIT 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x009A1184 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x009A1188 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x009A118C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x009A1190 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x009A1194 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x009A1198 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x009A119C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x009A11A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x009A11A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG 0x009A11A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_FREEZE 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_CMD_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_CMD_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_SAMPLE_COUNT 6:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALCFG_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009A11B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009A11B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009A11BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009A11C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009A11C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009A11C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009A11CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009A11D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR 0x009A11D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE 16:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x009A11D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD 3:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x009A11FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x009A1200 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x009A1204 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x009A1208 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x009A120C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x009A1210 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x009A1214 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x009A1218 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG 0x009A121C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL 15:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0 0x009A1224 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM 21:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1 0x009A1228 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL 16:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE1 0x009A1030 /* R--4R */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE1_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE1_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE2 0x009A1034 /* R--4R */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE2_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE2_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE3 0x009A1038 /* R--4R */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE3_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_DONT_USE3_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x009A12C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x009A12C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x009A12CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x009A12D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG6_BRICK_SPARE 0x009A12D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG6_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE 0x009A12D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE 0x009A12DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG9_BRICK_SPARE 0x009A12F4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG9_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE 0x009A12E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE 0x009A12E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x009A1700 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x009A1704 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x009A1708 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x009A170C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x009A1710 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x009A1714 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x009A1718 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x009A171C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x009A1720 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x009A1724 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x009A1728 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x009A172C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x009A1730 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x009A1734 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x009A1738 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x009A173C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x009A1740 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x009A1744 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x009A1748 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x009A174C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x009A1750 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x009A1754 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x009A1758 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x009A175C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x009A1760 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x009A1764 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x009A1768 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x009A176C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x009A1770 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x009A1774 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x009A1778 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x009A177C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x009A1780 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x009A1784 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x009A1788 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x009A178C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x009A1790 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x009A1794 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x009A1798 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x009A179C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x009A17A0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x009A17A4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x009A17A8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x009A17AC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x009A17B0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x009A17B4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x009A17B8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x009A17BC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x009A17C0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x009A17C4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x009A17C8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x009A17CC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x009A17D0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x009A17D4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x009A17D8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x009A17DC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x009A17E0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x009A17E4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x009A17E8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x009A17EC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x009A17F0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x009A17F4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x009A17F8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x009A17FC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x009A1800 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x009A1804 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x009A1808 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x009A180C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x009A1810 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x009A1814 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x009A1818 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x009A181C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x009A1860 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x009A1864 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x009A1868 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x009A186C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x009A1870 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x009A1874 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x009A1878 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x009A187C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x009A1880 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x009A1884 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x009A1888 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x009A188C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x009A1890 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x009A1894 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x009A1898 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x009A189C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x009A18A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x009A18A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x009A18A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x009A18AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x009A18B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x009A18B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x009A18B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x009A18BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x009A18D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x009A18D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x009A18D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x009A18DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x009A18E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x009A18E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x009A18E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x009A18EC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x009A18F0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x009A18F4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x009A18F8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x009A18FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x009A1900 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x009A1904 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x009A1908 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x009A190C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x009A1910 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x009A1914 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x009A1918 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x009A191C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x009A1920 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x009A1924 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x009A1928 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x009A192C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x009A1930 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x009A1934 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x009A1938 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x009A193C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x009A1940 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x009A1944 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x009A1948 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x009A194C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x009A1950 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x009A1954 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x009A1958 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x009A195C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x009A1960 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x009A1964 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x009A1968 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x009A196C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x009A1970 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x009A1974 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x009A1978 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x009A197C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x009A1980 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x009A1984 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x009A1988 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x009A198C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x009A2600 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x009A2604 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x009A2608 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x009A260C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x009A2610 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x009A2614 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x009A2618 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x009A261C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x009A2620 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x009A2624 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x009A2628 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x009A262C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x009A2630 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x009A2634 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x009A2638 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x009A263C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x009A2640 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x009A2644 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x009A2648 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x009A264C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x009A2650 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x009A2654 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x009A2658 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x009A265C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x009A2660 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x009A2664 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x009A2668 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x009A266C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x009A2670 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x009A2674 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x009A2678 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x009A267C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x009A2680 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x009A2684 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x009A2688 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x009A268C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x009A2690 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x009A2694 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x009A2698 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x009A269C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x009A26A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x009A26A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x009A26A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x009A26AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x009A26B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x009A26B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x009A26B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x009A26BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x009A26C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x009A26C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x009A26C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x009A26CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x009A26D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x009A26D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x009A26D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x009A26DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x009A26E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x009A26E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x009A26E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x009A26EC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x009A26F0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x009A26F4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x009A26F8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x009A26FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x009A2700 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x009A2704 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x009A2708 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x009A270C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x009A2710 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x009A2714 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x009A2718 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x009A271C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x009A2720 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x009A2724 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x009A2728 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x009A272C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x009A2730 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x009A2734 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x009A2738 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x009A273C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x009A2740 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x009A2744 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x009A2748 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x009A274C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x009A2750 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x009A2754 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x009A2758 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x009A275C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x009A2760 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x009A2764 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x009A2768 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x009A276C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x009A2770 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x009A2774 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x009A2778 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x009A277C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT 0x009A27A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x009A27A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT 0x009A27A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x009A27AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT 0x009A27B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_DDLLCAL_LT_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x009A1990 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x009A1994 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x009A1998 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x009A199C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x009A19A0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x009A19A4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x009A19A8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x009A19AC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x009A19B0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x009A19B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x009A19B8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x009A19BC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x009A19C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x009A19C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x009A19C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x009A19CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x009A19D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x009A19D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x009A19D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x009A19DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x009A19E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x009A19E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x009A19E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x009A19EC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x009A1FC0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x009A1FC4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x009A1FC8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x009A1FCC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x009A1FD0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x009A1FD4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x009A1FD8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x009A1FDC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x009A1FE0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x009A1FE4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x009A1FE8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x009A1FEC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x009A1FF0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x009A1FF4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x009A1FF8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x009A1FFC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x009A1820 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x009A1824 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x009A1828 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x009A182C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x009A1830 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x009A1834 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x009A1838 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x009A183C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL 0x009A1A00 /* RW-4R */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT 4:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY 11:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_STARTVAL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_STARTVAL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SEL_ODD 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SEL_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SEL_VREFU 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_OFFSET_CAL_CTRL_SEL_VREFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_MISC_CTRL 0x009A1A04 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VREF_MISC_CTRL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x009A1A10 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x009A1A14 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x009A1A18 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x009A1A1C /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x009A1A20 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x009A1A24 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x009A1A28 /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x009A1A2C /* R--4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x009A1A30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x009A1A34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x009A1A38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x009A1A3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x009A1A40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x009A1A44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x009A1A48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x009A1A4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x009A1A50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x009A1A54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x009A1A58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x009A1A5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x009A1A60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x009A1A64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x009A1A68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x009A1A6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x009A1A70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x009A1A74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x009A1A78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x009A1A7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x009A1A80 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x009A1A84 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x009A1A88 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x009A1A8C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x009A1A90 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x009A1A94 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x009A1A98 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x009A1A9C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x009A1AA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x009A1AA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x009A1AA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x009A1AAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x009A1AB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x009A1AB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x009A1AB8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x009A1ABC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x009A1AC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x009A1AC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x009A1AC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x009A1ACC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x009A1AD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x009A1AD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x009A1AD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x009A1ADC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x009A1AE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x009A1AE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x009A1AE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x009A1AEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x009A1AF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x009A1AF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x009A1AF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x009A1AFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x009A1B00 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x009A1B04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x009A1B08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x009A1B0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x009A1B10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x009A1B14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x009A1B18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x009A1B1C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x009A1B20 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x009A1B24 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x009A1B28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x009A1B2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x009A1B30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x009A1B34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x009A1B38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x009A1B3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x009A1B40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x009A1B44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x009A1B48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x009A1B4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x009A1B50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x009A1B54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x009A1B58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x009A1B5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x009A1B60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x009A1B64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x009A1B68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x009A1B6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x009A1B70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x009A1B74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x009A1B78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x009A1B7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x009A1B80 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x009A1B84 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x009A1B88 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x009A1B8C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x009A1B90 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x009A1B94 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x009A1B98 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x009A1B9C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x009A1BA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x009A1BA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x009A1BA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x009A1BAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x009A1BB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x009A1BB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x009A1BB8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x009A1BBC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x009A1BC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x009A1BC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x009A1BC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x009A1BCC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x009A1BD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x009A1BD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x009A1BD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x009A1BDC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x009A1BE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x009A1BE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x009A1BE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x009A1BEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x009A1BF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x009A1BF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x009A1BF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x009A1BFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x009A1C00 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x009A1C04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x009A1C08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x009A1C0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x009A1C10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x009A1C14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x009A1C18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x009A1C1C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x009A1C20 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x009A1C24 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x009A1C28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x009A1C2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x009A1C30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x009A1C34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x009A1C38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x009A1C3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x009A1C40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x009A1C44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x009A1C48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x009A1C4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x009A1C50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x009A1C54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x009A1C58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x009A1C5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x009A1C60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x009A1C64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x009A1C68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x009A1C6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x009A1C70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x009A1C74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x009A1C78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x009A1C7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x009A1C80 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x009A1C84 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x009A1C88 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x009A1C8C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x009A1C90 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x009A1C94 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x009A1C98 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x009A1C9C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x009A1CA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x009A1CA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x009A1CA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x009A1CAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x009A1CB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x009A1CB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x009A1CB8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x009A1CBC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x009A1CC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x009A1CC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x009A1CC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x009A1CCC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x009A1CD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x009A1CD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x009A1CD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x009A1CDC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x009A1CE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x009A1CE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x009A1CE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x009A1CEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x009A1CF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x009A1CF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x009A1CF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x009A1CFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x009A1D00 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x009A1D04 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x009A1D08 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x009A1D0C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x009A1D10 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x009A1D14 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x009A1D18 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x009A1D1C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x009A1D20 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x009A1D24 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x009A1D28 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x009A1D2C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x009A1D30 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x009A1D34 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x009A1D38 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x009A1D3C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x009A1D40 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x009A1D44 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x009A1D48 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x009A1D4C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x009A1D50 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x009A1D54 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x009A1D58 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x009A1D5C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x009A1D60 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x009A1D64 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x009A1D68 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x009A1D6C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x009A1D70 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x009A1D74 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x009A1D78 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x009A1D7C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x009A1D80 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x009A1D84 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x009A1D88 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x009A1D8C /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x009A1DA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x009A1DA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x009A1DA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x009A1DAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x009A1DB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x009A1DB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x009A1DB8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x009A1DBC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x009A1DC0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x009A1DC4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x009A1DC8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x009A1DCC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x009A1DD0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x009A1DD4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x009A1DD8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x009A1DDC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x009A1DE0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x009A1DE4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x009A1DE8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x009A1DEC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x009A1DF0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x009A1DF4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x009A1DF8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x009A1DFC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLLCAL 0x009A1E00 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLLCAL 0x009A1E04 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLLCAL 0x009A1E08 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLLCAL 0x009A1E0C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLLCAL 0x009A1E10 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLLCAL 0x009A1E14 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLLCAL 0x009A1E18 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLLCAL 0x009A1E1C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF 0x009A1E20 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLLCAL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF 0x009A1E24 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF 0x009A1E28 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF 0x009A1E2C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF 0x009A1E30 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF 0x009A1E34 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF 0x009A1E38 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF 0x009A1E3C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF 0x009A1E40 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF 0x009A1E44 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1 0x009A1E48 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2 0x009A1E4C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1 0x009A1E50 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2 0x009A1E54 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1 0x009A1E58 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2 0x009A1E5C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1 0x009A1E60 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2 0x009A1E64 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1 0x009A1E68 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2 0x009A1E6C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1 0x009A1E70 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2 0x009A1E74 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1 0x009A1E78 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2 0x009A1E7C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1 0x009A1E80 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2 0x009A1E84 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU 0x009A1E88 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU 0x009A1E8C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU 0x009A1E90 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU 0x009A1E94 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU 0x009A1E98 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU 0x009A1E9C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU 0x009A1EA0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU 0x009A1EA4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD 0x009A1EA8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD 0x009A1EAC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD 0x009A1EB0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD 0x009A1EB4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD 0x009A1EB8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD 0x009A1EBC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD 0x009A1EC0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD 0x009A1EC4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT 0x009A1F30 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BG_VTT__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BG_VTT_TEMP_COEFF 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_TEMP_COEFF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_IBG_CNTL 4:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_BG_CNTL 8:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_LV_CDBVAUXC 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_LV_CDBVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_LIMITER 16:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_CDBVAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BG_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BG_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB 0x009A1F4C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB 0x009A1F40 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB 0x009A1F3C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB 0x009A1F44 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS 0x009A1F48 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SUBP0_CK 10:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SUBP1_CK 23:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1 0x009A1F50 /* RW-4R */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0 0x009A2780 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1 0x009A2784 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2 0x009A2788 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3 0x009A278C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0 0x009A2790 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1 0x009A2794 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2 0x009A2798 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3 0x009A279C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING 0x009A1F54 /* RW-4R */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_RD_GAIN 7:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_RD_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_WR_GAIN 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_WR_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET 20:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EDGE_BRLSHFT 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EDGE_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_CENTER_BRLSHFT 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_CENTER_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_BLOCK_COUNT 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_BLOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EN 27:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_HUNT_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_HUNT_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_USE_CENTER_ONLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_USE_CENTER_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_HALF_RATE_EDC 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_HALF_RATE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING 0x009A1F58 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_GAIN 6:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_ACCUM 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_ACCUM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN 10:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT 19:11 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW 20:20 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW 21:21 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF 28:22 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_VREF_EDGE_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_VREF_EDGE_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2 0x009A27B4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_SHADOW_LOAD 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_SHADOW_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_SHADOW_SELECT 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_SHADOW_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_CDR_MASK 9:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING2_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1 0x009A27B8 /* R--4R */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFP_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFP_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFP_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFP_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFN_EVEN 23:16 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFN_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFN_ODD 31:24 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ1_VREFN_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2 0x009A27BC /* R--4R */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x009A27C8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x009A27CC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x009A27D0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x009A27D4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x009A27D8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x009A27DC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x009A27E0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x009A27E4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x009A27E8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x009A27EC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x009A27F0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x009A27F4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x009A27F8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x009A27FC /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x009A2800 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x009A2804 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG 0x009A1F5C /* RW-4R */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT 11:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW 13:13 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW 14:14 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW 15:15 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DQ_SEL 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DQ_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL 22:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DIR_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DIR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL 26:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW 27:27 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW 28:28 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1 0x009A1F60 /* R--4R */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI 6:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI 13:7 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_DQ_PI 20:14 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_DQ_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT 26:21 /* R-IVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x009A1F64 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x009A1F68 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x009A1F6C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x009A1F70 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x009A1F74 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x009A1F78 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x009A1F7C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x009A1F80 /* RW-4R */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14 0x009A1F84 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CFG14__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE1 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE2 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE3 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE4 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE5 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE6 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE7 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_EDC_PIN_STATE_BYTE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CFG14_FORCE_PIN_STATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CFG14_FORCE_PIN_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC 0x009A1F8C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HSDAC__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_HSDAC_EN_X 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_EN_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_SIGNAL_SEL_X 4:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_SIGNAL_SEL_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_OFFSET_X 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_OFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_SELECT_X 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_SELECT_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_EN_Y 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_EN_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_SIGNAL_SEL_Y 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_SIGNAL_SEL_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_OFFSET_Y 26:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_OFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HSDAC_SELECT_Y 29:27 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HSDAC_SELECT_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0 0x009A27C0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC0_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1 0x009A27C4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_FBIO_CMD_HSDAC1_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0 0x009A1F90 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1 0x009A1F94 /* RW-4R */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS 0x009A1F98 /* RW-4R */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_TERM 23:23 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_TERM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTERP_2UI 0x009A1F9C /* RW-4R */ #define NV_PFB_FBPA_FBIO_INTERP_2UI__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_RX 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_TX 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_SPARE 31:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_INTERP_2UI_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x009A1FA0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x009A1FA4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x009A1FA8 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x009A1FAC /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x009A1FB0 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x009A1FB4 /* RW-4R */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1 0x009A1FB8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1__PRIV_LEVEL_MASK 0x009A08FC /* */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_CDR_MASK 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS 15:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_SUPPORT 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_EDC_TRACKING1_LOCK_SUPPORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK 0x009A3C7C /* RW-4R */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG 0x009A3C90 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SYNCMODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SYNCMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SYNCMODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SYNCMODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_LCKDET 3:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_LCKDET_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_LCKDET_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_LOCK_OVERRIDE 4:4 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_PLL_LOCK 5:5 /* R--UF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_FSTLCK 6:6 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_IDDQ 7:7 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE_BG 8:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_STOP_SYNCMUX 9:9 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_BYPASSPLL 10:10 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_BYPASSPLL_VCO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_BYPASSPLL_BYPASSCLK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO 11:11 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE 13:13 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE 31:31 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL 0x009A3C94 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF 0x009A3C98 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_NDIV_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO 0x009A3C9C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST 0x009A3CA0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL 9:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL 12:10 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE 16:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RFU 24:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG 0x009A3CA4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN 13:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK 20:14 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK 27:21 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG1 0x009A3CA8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG1_TX_EN 23:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_CFG1_TX_EN_INIT 0x00FFD98A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD1 0x009A3CAC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD1_TX 23:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD1_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD2 0x009A3CB0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD2_RX 23:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_BRICK_TEST_PWRD2_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE 0x009A3CCC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA 23:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CFG13_BRICK_SPARE 0x009A3CD0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CFG13_BRICK_SPARE__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB 15:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG 0x009A3CD4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF 5:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_INT_VREF 11:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_INT_VREF_INIT 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV 19:17 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE 30:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1 0x009A3CD8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK 7:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK 14:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK 21:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK 28:22 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL 31:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2 0x009A3CDC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT 0:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE 1:1 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE 3:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH 6:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW 10:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD 12:11 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST 15:13 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV 24:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV 26:25 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1 0x009A3CE0 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREG14V_CTRL 5:4 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREG10V_CTRL 7:6 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG1_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0 0x009A3CE4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER 5:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL 26:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1 0x009A3CE8 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD 1:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL 6:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL 8:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF 11:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST 14:12 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_RFU 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_HBMCDB_CFG1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0 0x009A3CEC /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL 4:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU_INIT 0x00000030 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG2 0x009A3CF4 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG2_SETUP 27:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBMPLL_CFG2_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG 0x009A3C00 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN 0x009A3C04 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX 0x009A3C08 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL 0x009A3C0C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB 0x009A3C10 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_RISE_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_FALL_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_TERM 22:16 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2 0x009A3C14 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_RISE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_FALL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_SPARE 15:15 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3 0x009A3C18 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4 0x009A3C1C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5 0x009A3C20 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x009A3C30 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x009A3C34 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x009A3C38 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x009A3C3C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x009A3C40 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x009A3C44 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x009A3C48 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x009A3C4C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x009A3C50 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x009A3C54 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x009A3C58 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x009A3C5C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x009A3C60 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x009A3C64 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2 0x009A3C68 /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3 0x009A3C6C /* RW-4R */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG 0x009A3D00 /* RW-4R */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_SYNC_MODE 1:1 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX 3:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL 0x009A3D04 /* RW-4R */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2 0x009A3D08 /* RW-4R */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_SEL_TESTOUT 2:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_SETUP2 27:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_TESTMODE 28:28 /* RWIUF */ #define NV_PFB_FBPA_FBIO_REFMPLL_CFG2_TESTMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG 0x009A3D20 /* RW-4R */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_CLAMP_P0 3:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_CLAMP_P0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_CLAMP_P0_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_CLAMP_P0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4 4:4 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL 0x009A3D24 /* RW-4R */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL 31:29 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2 0x009A3D28 /* RW-4R */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2_SETUP2 11:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0 0x009A3D40 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_LV_VAUXC 18:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_BW 22:19 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD 27:26 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST 30:28 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1 0x009A3D44 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CMD_VTT_SPARE 17:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CMD_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_BYTE_VTT_SPARE 19:18 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_BYTE_VTT_SPARE_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VTT_SPARE 21:20 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_CDB_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL 29:22 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL 0x009A3D48 /* RW-4R */ #define NV_PFB_FBPA_FBIO_CDBCTRL__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_CDBCTRL_BG_CNTL 3:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IBG_CNTL 5:4 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IRX_CNTL 7:6 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IRX_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IRX_SRC_SEL 10:8 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IRX_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEMP_COEF 13:11 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_CDB_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_CDB_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_SEL 20:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_E_RES_CAL_CODE_IN 21:21 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_E_RES_CAL_CODE_IN_BYP_SEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL 26:22 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IBG_SRC_SEL 29:27 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CDBCTRL_IBG_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV 0x009A3D4C /* RW-4R */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL 2:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_SPARE 10:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_PTRIM_OVRD 11:11 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_PTRIM_OVRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_MODE_SWITCH 13:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_MODE_SWITCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_MODE_SWITCH_DRAMPLL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_MODE_SWITCH_ONESOURCE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_MODE_SWITCH_REFMPLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_DPD 16:16 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_DPD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_DPD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE 17:17 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL 18:18 /* RWIUF */ #define NV_PFB_FBPA_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2 0x009A3D50 /* RW-4R */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2__PRIV_LEVEL_MASK 0x009A3C7C /* */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM 2:0 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM 5:3 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM 8:6 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_BGAP_TRIM 11:9 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_BGAP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_E_TRIM 12:12 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_E_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXC 16:13 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXC_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXP 20:17 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VAUXP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VCLAMP 24:21 /* RWIUF */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VCLAMP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_FBIO_VTT_CTRL2_CDB_VCLAMP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK 0x00900168 /* RW-4R */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK 0x00900148 /* RW-4R */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK 0x0090014C /* RW-4R */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK 0x00900170 /* RW-4R */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_ecc" /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK 0x009001B0 /* RW-4R */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK 0x009001B4 /* RW-4R */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK 0x00902578 /* RW-4R */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK 0x0090000C /* RW-4R */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK 0x00902250 /* RW-4R */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK 0x0090086C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_SPARE 0x00900050 /* RW-4R */ #define NV_PFB_FBPA_0_SPARE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SPARE_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_SPARE_BITS_INIT 0xFF001040 /* RWI-V */ #define NV_PFB_FBPA_0_SPARE_BITS_OFIFO_OFFSET 5:0 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_OFIFO_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_CMDFF_DEPTH 12:8 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_CMDFF_DEPTH_INIT 0x00000010 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_CMDFF_DEPTH_MAX 0x00000010 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_CMDFF_DEPTH_SAFE 0x00000004 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_SYNC_PULSE_POLARITY 13:13 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_SYNC_PULSE_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_OFIFO_OFFSET_POLARITY 14:14 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_OFIFO_OFFSET_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_PDEN_OFFSET 19:16 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_PDEN_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_L2_CRC_MODE 20:20 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_L2_CRC_MODE_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_VS_DELAY 23:21 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_VS_DELAY_INIT 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_BIT30 30:30 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_BIT30_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_BUG765178_TEST_MODE 31:31 /* ----F */ #define NV_PFB_FBPA_0_SPARE_BITS_BUG765178_TEST_MODE_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_BUG765178_TEST_MODE_SKIP 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_SPARE_BITS_BUG765178_TEST_MODE_RUN 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_SPARE2 0x009000CC /* RW-4R */ #define NV_PFB_FBPA_0_SPARE2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SPARE2_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_SPARE2_BITS_INIT 0xFFFF0000 /* RWI-V */ #define NV_PFB_FBPA_0_FALCON_MONITOR 0x00900054 /* RW-4R */ #define NV_PFB_FBPA_0_FALCON_MONITOR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FALCON_MONITOR_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FALCON_MONITOR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER 0x00900064 /* R--4R */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_DEV 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_ECO 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_MINOR 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_MINOR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_MAJOR 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_FALCON_CTRL_VER_MAJOR_INIT 0x00000004 /* R-I-V */ #define NV_PFB_FBPA_0_CFG_PWRD 0x00900060 /* RW-4R */ #define NV_PFB_FBPA_0_CFG_PWRD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_80 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_120 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_CFG_PWRD_RCVR_PWRD_DLY 8:5 /* RWIVF */ #define NV_PFB_FBPA_0_CFG_PWRD_RCVR_PWRD_DLY_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0 0x00900080 /* RW-4R */ #define NV_PFB_FBPA_0_DEBUG_0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_0_MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_MRS_256 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_MRS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_PERIODIC_QRST 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_PERIODIC_QRST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_PERIODIC_QRST_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_SPARE0 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_PIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_PIN_CMD 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_PIN_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_PIN_DEBUG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_MODE 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_MODE_WRITE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_ODT_MODE_NOTREAD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_USE_CFG0_BL8_HBM 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_USE_CFG0_BL8_HBM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_USE_CFG0_BL8_HBM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_BL16EDC_SET 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_BL16EDC_SET_EVEN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_BL16EDC_SET_ODD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_WFT_IDLE 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_WFT_IDLE_NEW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_WFT_IDLE_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_FB_IDLE_NOPBR 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_FB_IDLE_NOPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_FB_IDLE_NOPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HANDSHAKE 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HANDSHAKE_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HANDSHAKE_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_FORCE_FULL_MEMREF 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_FORCE_FULL_MEMREF_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_FORCE_FULL_MEMREF_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_R2P_BL_ADJUST 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_R2P_BL_ADJUST_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_R2P_BL_ADJUST_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_POST_SP_TR 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_POST_SP_TR_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_POST_SP_TR_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_TOGGLE_FIX 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_TOGGLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_TOGGLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_MODE 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_MODE_SDR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_MODE_DDR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_PRI_REG_UPDATE_EXT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_PRI_REG_UPDATE_EXT_15 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_PRI_REG_UPDATE_EXT_31 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_REFCFG_REQ_PENDING 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_REFCFG_REQ_PENDING_FIXED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_REFCFG_REQ_PENDING_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_BECS_ACK 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_BECS_ACK_LEVEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_BECS_ACK_PULSE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_DRAM_ACK 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_DRAM_ACK_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_DRAM_ACK_IDLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_0_TREFI_UPDATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_0_TREFI_UPDATE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_0_TREFI_UPDATE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_1 0x00900084 /* RW-4R */ #define NV_PFB_FBPA_0_DEBUG_1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_1_L2_ECC 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_1_L2_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_1_L2_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DEBUG_2 0x00902340 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_2_XBAR_ASR_OK 0:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_2_XBAR_ASR_OK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_2_XBAR_ASR_WAKEUP 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_2_XBAR_ASR_WAKEUP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_2_STOP_FB_REQ 2:2 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_2_STOP_FB_REQ_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_2_STOP_FB_ACK 3:3 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_2_STOP_FB_ACK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_SUBPIDLE(i) (0x00902344+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_DEBUG_SUBPIDLE__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_DEBUG_SUBPIDLE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_SUBPIDLE_IDLES 27:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_SUBPIDLE_IDLES_INIT 0x0FFFFFFF /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_PAIDLE 0x0090234C /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_PAIDLE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_PAIDLE_IDLES 21:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_PAIDLE_IDLES_INIT 0x003FFFFF /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0 0x00902350 /* RW-4R */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0_EN_COUNT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0_EN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0_CLR_COUNT 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_0_CLR_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1 0x00902354 /* RW-4R */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_1 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_2 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_3 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_DEBUG_CTRL_1_SEL_3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_BASE 0x00902358 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_BASE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_BASE 0x0090235C /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_BASE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_0 0x00902360 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_0 0x00902364 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_1 0x00902368 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_1 0x0090236C /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_2 0x00902370 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_2 0x00902374 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_3 0x00902378 /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_LO_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_3 0x0090237C /* R--4R */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DEBUG_COUNT_HI_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_ROW_REMAP 0x009001DC /* R--4R */ #define NV_PFB_FBPA_0_ROW_REMAP__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_ENABLE 0:0 /* R-IVF */ #define NV_PFB_FBPA_0_ROW_REMAP_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_ROW_REMAP_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD(i) (0x009001F0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ROW_REMAP_RD__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ENTRY_VLD 8:8 /* R-IVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ENTRY_VLD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ROW 25:9 /* R-IVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ROW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_RD_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR(i) (0x009001F8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ROW_REMAP_WR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ROW_REMAP_WR__PRIV_LEVEL_MASK 0x0090000C /* */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_ROW 25:9 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_ROW_REMAP_WR_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD 0x00900090 /* RW-4R */ #define NV_PFB_FBPA_0_TESTCMD__PRIV_LEVEL_MASK 0x0090014C /* */ #define NV_PFB_FBPA_0_TESTCMD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LPDDR4_SELF_REF_ENTRY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LPDDR4_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CKE_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_CS0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_CS1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CS1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_RAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_CAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_CAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_WE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_HBM_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_WE_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_RES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_RES_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_4_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR6_SELF_REF_ENTRY1 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR6_SELF_REF_ENTRY2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_BANK_DDR6_SELF_REF_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR 25:12 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER 28:26 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_GO_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_HOLD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT 0x00900094 /* RW-4R */ #define NV_PFB_FBPA_0_TESTCMD_EXT__PRIV_LEVEL_MASK 0x0090014C /* */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ADR_DRAM1 10:3 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ADR_DRAM1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DEBUG 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DEBUG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ODT 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ODT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_RW_CMD 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_RW_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_MRS_CMD 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_MRS_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DR_CMD 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DR_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_4CK_CMD 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_4CK_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_LAM_CMD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_LAM_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_CMD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_SID 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_SID_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1 0x00900154 /* RW-4R */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1__PRIV_LEVEL_MASK 0x0090014C /* */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_ENTRY 0x00018018 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_EXIT 0x00014014 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0 0x009000A0 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1 0x009000A4 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2 0x009000A8 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3 0x009000AC /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0 0x009000B0 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1 0x009000B4 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2 0x009000B8 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3 0x009000BC /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI 0x009000C0 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_DBI__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_DBI_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC 0x009000C8 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_ECC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_ECC_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE 0x009000C4 /* RW-4R */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE1 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE2 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE3 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE0 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE1 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE2 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE3 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCK01 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCKB01 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCK23 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCKB23 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP0_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCK01 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCKB01 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCK23 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCKB23 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_SWIZZLE_BYTE_SUBP1_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_PM 0x00900100 /* RW-4R */ #define NV_PFB_FBPA_0_PM__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_0_PM_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC0 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT0 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT1 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ0 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ2 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC2 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ3 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ4 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ5 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC4 0x00000013 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT4 0x00000015 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT5 0x00000016 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ4 0x00000017 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ6 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRTYREQ7 0x0000001A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC6 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SLC7 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT6 0x0000001D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDAT7 0x0000001E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ6 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READREQ7 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_SUBP0 0x00000021 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_SUBP1 0x00000022 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_CH0_SUBP0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_CH0_SUBP1 0x00000024 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_CH1_SUBP0 0x00000025 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_ACT_CH1_SUBP1 0x00000026 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_BANK_ACT_SUBP0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_BANK_ACT_SUBP1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_NO_ACT_SUBP0 0x00000029 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_NO_ACT_SUBP1 0x0000002A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP0 0x0000002B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP1 0x0000002C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BANKQ_EMPTY_SUBP0 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BANKQ_EMPTY_SUBP1 0x0000002E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BA_OUTPUT 0x0000002F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BA_SIGS 0x00000030 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_CKG0 0x00000031 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_CKG1 0x00000032 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRARB_SUBP0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DIRARB_SUBP1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_BANKS_SUBP0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_BANKS_SUBP1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_EXTRA_SUBP0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_EXTRA_SUBP1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RWALL 0x00000039 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_SUBP0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_SUBP1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_CH0_SUBP0 0x0000003C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_CH0_SUBP1 0x0000003D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_CH1_SUBP0 0x0000003E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RW_CH1_SUBP1 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_SUBP0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_SUBP1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_CH0_SUBP0 0x00000042 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_CH0_SUBP1 0x00000043 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_CH1_SUBP0 0x00000044 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_CH1_SUBP1 0x00000045 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_CH0_SUBP0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_CH0_SUBP1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_CH1_SUBP0 0x00000048 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_CH1_SUBP1 0x00000049 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_PART2_SUBP0 0x0000004A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_PART2_SUBP1 0x0000004B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_PP_SUBP0 0x0000004C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_WAIT_PP_SUBP1 0x0000004D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ECC_CH0_SUBP0 0x0000004E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ECC_CH0_SUBP1 0x0000004F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ECC_CH1_SUBP0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ECC_CH1_SUBP1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_FT_IDLE_SUBP0 0x00000052 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_FT_IDLE_SUBP1 0x00000053 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE 0x00000054 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_CH0_SUBP0 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_CH0_SUBP1 0x00000056 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_CH1_SUBP0 0x00000057 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_CH1_SUBP1 0x00000058 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SUBP0 0x00000059 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_IDLE_SUBP1 0x0000005A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_INFLIGHT_READ_COUNT 0x0000005B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_INFLIGHT_READ_COUNT_VC0 0x0000005C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_INFLIGHT_READ_COUNT_VC1 0x0000005D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_INFLIGHT_READ_COUNT_VC2 0x0000005E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_INFLIGHT_WRITE_COUNT 0x0000005F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_OUT_READS 0x00000060 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_OUT_WRITES 0x00000061 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_PENDING_REFRESH_SUBP0 0x00000062 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_PENDING_REFRESH_SUBP1 0x00000063 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_PART2_SUBP0 0x00000064 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_PART2_SUBP1 0x00000065 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_SUBP0 0x00000066 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_SUBP1 0x00000067 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP0 0x00000068 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP1 0x00000069 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP0 0x0000006A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP1 0x0000006B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP0 0x0000006C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP1 0x0000006D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READARB_SUBP0 0x0000006E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READARB_SUBP1 0x0000006F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_READARB_VC 0x00000070 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_REFSB_SUBP0 0x00000071 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_REFSB_SUBP1 0x00000072 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT0_PART2_SUBP0 0x00000073 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT0_PART2_SUBP1 0x00000074 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT0_SUBP0 0x00000075 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT0_SUBP1 0x00000076 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT1_PART2_SUBP0 0x00000077 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT1_PART2_SUBP1 0x00000078 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT1_SUBP0 0x00000079 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RFT1_SUBP1 0x0000007A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_STAT_CH0_SUBP0 0x0000007B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_STAT_CH0_SUBP1 0x0000007C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_STAT_CH1_SUBP0 0x0000007D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_STAT_CH1_SUBP1 0x0000007E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_SINGLE_PASS_SUBP0 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_SINGLE_PASS_SUBP1 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000081 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000082 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_SUBP01_TRAFFIC 0x00000083 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_SUBP01_TRAFFIC_CH0 0x00000084 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_SUBP01_TRAFFIC_CH1 0x00000085 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WFT0_SUBP0 0x00000086 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WFT0_SUBP1 0x00000087 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WFT1_SUBP0 0x00000088 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WFT1_SUBP1 0x00000089 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP0 0x0000008A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP1 0x0000008B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRBANKQ_SUBP0 0x0000008C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRBANKQ_SUBP1 0x0000008D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEARB_SUBP0 0x0000008E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEARB_SUBP1 0x0000008F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_UTIL_SUBP0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_UTIL_SUBP1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RCMD_CH0_SUBP0 0x00000092 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RCMD_CH0_SUBP1 0x00000093 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RCMD_CH1_SUBP0 0x00000094 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_DRAMC_RCMD_CH1_SUBP1 0x00000095 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_SUBP0 0x00000096 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_SUBP1 0x00000097 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_CH0_SUBP0 0x00000098 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_CH0_SUBP1 0x00000099 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_CH1_SUBP0 0x0000009A /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BUCKET_CH1_SUBP1 0x0000009B /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ISO_TRACKING0_SUBP0 0x0000009C /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ISO_TRACKING0_SUBP1 0x0000009D /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ISO_TRACKING1_SUBP0 0x0000009E /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ISO_TRACKING1_SUBP1 0x0000009F /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC0_SUBP0 0x000000A0 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC0_SUBP1 0x000000A1 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC1_SUBP0 0x000000A2 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC1_SUBP1 0x000000A3 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC2_SUBP0 0x000000A4 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_BW_TRACKING_VC2_SUBP1 0x000000A5 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG0 0x000000A6 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG1 0x000000A7 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG2 0x000000A8 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG3 0x000000A9 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_RETURN_FIFO_SG0 0x000000AA /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_RETURN_FIFO_SG1 0x000000AB /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_RETURN_FIFO_SG2 0x000000AC /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_RR_RETURN_FIFO_SG3 0x000000AD /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR0_SUBP0 0x000000AE /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR0_SUBP1 0x000000AF /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR1_SUBP0 0x000000B0 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR1_SUBP1 0x000000B1 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR2_SUBP0 0x000000B2 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR2_SUBP1 0x000000B3 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR3_SUBP0 0x000000B4 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR3_SUBP1 0x000000B5 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR4_SUBP0 0x000000B6 /* RW--V */ #define NV_PFB_FBPA_0_PM_SELECT_ACPD_ASR4_SUBP1 0x000000B7 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP(i) (0x009001E0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_SUBP__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_SUBP__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_SUBP_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_SUBP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_ACT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_ACT_CH0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_ACT_CH1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_BANK_ACT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_NO_ACT 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACTARB_NUM_RW_BANKS 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BANKQ_EMPTY 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DIRARB 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_CH0 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_CH1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_BANKS 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_EXTRA 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_RW 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_RW_CH0 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_RW_CH1 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_WAIT_CH0 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_WAIT_CH1 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_WAIT_PART2 0x00000013 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_WAIT_PP 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ECC_CH0 0x00000015 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ECC_CH1 0x00000016 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_FT_IDLE 0x00000017 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_IDLE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_IDLE_CH0 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_IDLE_CH1 0x0000001A /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_PENDING_REFRESH 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RDBANKQ 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RDBANKQ_PART2 0x0000001D /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RDBANKQ_VC0_REQ_FIFO 0x0000001E /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RDBANKQ_VC1_REQ_FIFO 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RDBANKQ_VC2_REQ_FIFO 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_READARB 0x00000021 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_REFSB 0x00000022 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RFT0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RFT0_PART2 0x00000024 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RFT1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RFT1_PART2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RR_STAT_CH0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_RR_STAT_CH1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_SINGLE_PASS 0x00000029 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WFT0 0x0000002A /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WFT1 0x0000002B /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WRBANKQ 0x0000002C /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WRBANKQ_REQ_FIFO 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WRITEARB 0x0000002E /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_WRITEPULL_UTIL 0x0000002F /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_RCMD_CH0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_DRAMC_RCMD_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BUCKET 0x00000032 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BUCKET_CH0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BUCKET_CH1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ISO_TRACKING0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ISO_TRACKING1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BW_TRACKING_VC0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BW_TRACKING_VC1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_BW_TRACKING_VC2 0x00000039 /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACPD_ASR0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACPD_ASR1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACPD_ASR2 0x0000003C /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACPD_ASR3 0x0000003D /* RW--V */ #define NV_PFB_FBPA_0_PM_SUBP_SELECT_ACPD_ASR4 0x0000003E /* RW--V */ #define NV_PFB_FBPA_0_PM_CAPTURE(i) (0x00900180+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_CAPTURE__SIZE_1 12 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_CAPTURE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_CAPTURE_HI(i) (0x00902500+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_CAPTURE_HI__SIZE_1 12 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_HI__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_HI_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_CAPTURE_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_CAPTURE_WINDOW(i) (0x009001D0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_CAPTURE_WINDOW__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_WINDOW__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_WINDOW_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_CAPTURE_WINDOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_CAPTURE_CTL 0x009001D8 /* RW-4R */ #define NV_PFB_FBPA_0_PM_CAPTURE_CTL__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_CAPTURE_CTL_INVERT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_CAPTURE_CTL_INVERT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_BUCKET(i) (0x00902530+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_BUCKET__SIZE_1 11 /* */ #define NV_PFB_FBPA_0_PM_BUCKET__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_BUCKET_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_BUCKET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL 0x0090255C /* RW-4R */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE_RD_CMD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE_WR_CMD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE_COL_CMD 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE_ANY_CMD 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_PM_BUCKET_CTL_TYPE_ISO_TRACKING 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_PM_CTL 0x00902560 /* RW-4R */ #define NV_PFB_FBPA_0_PM_CTL__PRIV_LEVEL_MASK 0x009001B0 /* */ #define NV_PFB_FBPA_0_PM_CTL_ISO_SUBID_MSB_INDEX 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_CTL_ISO_SUBID_MSB_INDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PM_CTL_ISO_SUBID_MSB_INDEX_MAX 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_REG_CTL 0x00902564 /* RW-4R */ #define NV_PFB_FBPA_0_REG_CTL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REG_CTL_FBIO_NOACK 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_REG_CTL_FBIO_NOACK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REG_CTL_FBIO_NOACK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_ASR_NUM(i) (0x00900110+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_ASR_NUM__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASR_NUM__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASR_NUM_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_ASR_NUM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_ASR_CYCCNT(i) (0x00900118+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_ASR_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASR_CYCCNT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASR_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_ASR_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_ASR_MAXCYC(i) (0x00900120+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_PM_ASR_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASR_MAXCYC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASR_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_PM_ASR_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_PM_ASR_MINCYC(i) (0x00900128+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_PM_ASR_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASR_MINCYC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASR_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_PM_ASR_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_0_PM_ASRSTALL_CYCCNT(i) (0x00900130+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_CYCCNT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_PM_ASRSTALL_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MAXCYC(i) (0x00900138+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MAXCYC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MINCYC(i) (0x00900140+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MINCYC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_PM_ASRSTALL_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_0_ASRCTRL_NONISO 0x00900150 /* RW-4R */ #define NV_PFB_FBPA_0_ASRCTRL_NONISO__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASRCTRL_NONISO_THRESHOLD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASRCTRL_NONISO_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_CTRL 0x00900160 /* RW-4R */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_10 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_11 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_12 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_13 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_14 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_15 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_16 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_EN 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_CTRL_INTERVAL_TIMER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_NUM_ACTIVE_FBPS 0x00900164 /* RW-4R */ #define NV_PFB_FBPA_0_NUM_ACTIVE_FBPS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_NUM_ACTIVE_FBPS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_NUM_ACTIVE_LTCS 0x0090016C /* RW-4R */ #define NV_PFB_FBPA_0_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_NUM_ACTIVE_LTCS_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WPRE0 0x00900174 /* RW-4R */ #define NV_PFB_FBPA_0_WPRE0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPRE0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE0_DQ0_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_0_WPRE0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE0_DQ1_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_WPRE0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE0_DQ2_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_0_WPRE0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE0_DQ3_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_WPRE1 0x00900178 /* RW-4R */ #define NV_PFB_FBPA_0_WPRE1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPRE1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE1_DQ4_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_0_WPRE1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE1_DQ5_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_WPRE1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE1_DQ6_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_0_WPRE1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE1_DQ7_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_WPRE2 0x0090017C /* RW-4R */ #define NV_PFB_FBPA_0_WPRE2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPRE2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE2_DBI_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_WPRE2_TR_PATTERN 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_WPRE2_TR_PATTERN_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST0 0x009001B8 /* RW-4R */ #define NV_PFB_FBPA_0_WPOST0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPOST0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST0_DQ0_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST0_DQ1_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST0_DQ2_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST0_DQ3_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST1 0x009001BC /* RW-4R */ #define NV_PFB_FBPA_0_WPOST1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPOST1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST1_DQ4_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST1_DQ5_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST1_DQ6_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST1_DQ7_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_WPOST2 0x009001C0 /* RW-4R */ #define NV_PFB_FBPA_0_WPOST2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WPOST2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_WPOST2_DBI_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_CFG0 0x00900200 /* RW-4R */ #define NV_PFB_FBPA_0_CFG0__PRIV_LEVEL_MASK 0x00902250 /* */ #define NV_PFB_FBPA_0_CFG0_BL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_BL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_BL_BL4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_BL_BL8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_BL_BL16 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_EXTBANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_EXTBANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_EXTBANK_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_EXTBANK__PROD_C_SINGLE_SIDED_MEM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_EXTBANK__PROD_C_DUAL_SIDED_MEM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_X8 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_X8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_X8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_CA_RETURN_TO_ZERO 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_CA_RETURN_TO_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_CA_RETURN_TO_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_HBM_CMD_PARITY_OVERRIDE 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_HBM_CMD_PARITY_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_HBM_CMD_PARITY_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_EDC_RATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_EDC_RATE_HALF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_EDC_RATE_FULL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_GAPLESS_WTR 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_GAPLESS_WTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_GAPLESS_WTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACPD 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACPD_NO_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACPD_ACTIVE_POWERDOWN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ATR__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_DATA_SCRAMBLE 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_DATA_SCRAMBLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_DATA_SCRAMBLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_SYNC 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_AUTO_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_AUTO_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_LOW_POWER 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_LOW_POWER_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_LOW_POWER_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_ABI 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_BURST_LENGTH 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_BURST_LENGTH_4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_BURST_LENGTH_8 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_DM_ON_ADR 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_DM_ON_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_DM_ON_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_TIMING_UNIT 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_TIMING_UNIT_DRAMCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_TIMING_UNIT_DRAMDIV2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_CMD_PARITY 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_CMD_PARITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_CMD_PARITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_ODT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_CLAMSHELL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_CLAMSHELL_X32 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_CLAMSHELL_X16 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_EDC_EARLY_VALUE 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_EDC_EARLY_VALUE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_EDC_EARLY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_BG_8 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_BG_8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_BG_8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_PRE 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_AUTO_PRE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_AUTO_PRE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_SAME_QUSE_TWO_RANKS 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_SAME_QUSE_TWO_RANKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_SAME_QUSE_TWO_RANKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_RDEDC 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_RDEDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_RDEDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_WREDC 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_WREDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_WREDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_REPLAY 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_REPLAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_REPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_MS01_ECC 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_MS01_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_MS01_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACK 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG0_DRAM_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1 0x00900204 /* RW-4R */ #define NV_PFB_FBPA_0_CFG1__PRIV_LEVEL_MASK 0x00900148 /* */ #define NV_PFB_FBPA_0_CFG1_SUBP 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_SUBP_256B 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_SUBP_512B 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_SUBP_1KB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_SUBP_2KB 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_AP 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_AP_A8 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_AP_A9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_AP_A10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_AP_A11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_AP_A12 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_AP_A13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_STACK 9:7 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_STACK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_STACK_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_STACK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_COL_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_COL_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_CFG1_COL_15 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_ROWB_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_ROWB_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_ROWB_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_BANK 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_BANK_2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_BANK_3 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_BANK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_BG_8_OVR 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_BG_8_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_BG_8_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_BG 28:27 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_ROW_BG 30:29 /* RWIVF */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_ROW_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_ROW_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CFG1_NUM_BANKS_PER_ROW_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CSTATUS 0x0090020C /* R--4R */ #define NV_PFB_FBPA_0_CSTATUS__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CSTATUS_RAMAMOUNT 16:0 /* R-IVF */ #define NV_PFB_FBPA_0_CSTATUS_RAMAMOUNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CSTATUS_OVERRIDE 0x0090257C /* RW-4R */ #define NV_PFB_FBPA_0_CSTATUS_OVERRIDE__PRIV_LEVEL_MASK 0x00902578 /* */ #define NV_PFB_FBPA_0_CSTATUS_OVERRIDE_RAMAMOUNT 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_CSTATUS_OVERRIDE_RAMAMOUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL 0x00900210 /* RW-4R */ #define NV_PFB_FBPA_0_REFCTRL__PRIV_LEVEL_MASK 0x00902250 /* */ #define NV_PFB_FBPA_0_REFCTRL_PUT 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL_PUT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL_GET 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL_GET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL_RESET 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL_RESET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL_RESET_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFCTRL_VALID 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL_VALID_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL_VALID_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ 0x00900214 /* RW-4R */ #define NV_PFB_FBPA_0_ZQ__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ZQ_CL_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_CL_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_CS_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_CS_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_CL_PERIODIC 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_CL_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_CL_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_CS_PERIODIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_CS_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_CS_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_CH 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_CH_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_CH_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_RANK 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_RANK_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_PERIODIC_RANK_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_ZQ_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ZQ_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ZQ_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_PIN 0x00900218 /* RW-4R */ #define NV_PFB_FBPA_0_PIN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PIN_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PIN_DQM 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_DQM_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_DQM_INACTIVE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PIN_RESET 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_RESET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PIN_CKE_POLARITY 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_CKE_POLARITY_ACTIVE_HI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_CKE_POLARITY_ACTIVE_LO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PIN_A0 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_A0_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_A0_LOW 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_PIN_A0_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_PIN_WDQS_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_WDQS_MODE_RETURN_TO_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PIN_WDQS_MODE_RETURN_TO_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_PIN_WDQS_MODE_FREERUNNING 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_PIN_DBI 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_PIN_DBI_X8 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_PAD 0x0090021C /* RW-4R */ #define NV_PFB_FBPA_0_PAD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PAD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_CKE__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_CMD27 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_CMD27_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_CMD27_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_CMD28 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_CMD28_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_CMD28_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_CHANNEL_PULLDN 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_CHANNEL_PULLDN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_CHANNEL_PULLDN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_INPUT_DRIVER_CTRL 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_INPUT_DRIVER_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_INPUT_DRIVER_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PAD_DBI 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_PAD_DBI_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PAD_DBI_OVERRIDE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING 0x009003F4 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING_ACT2PDEN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING_ACT2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING_ACT2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING_PCHG2PDEN 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING_PCHG2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING_PCHG2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING_AR2PDEN 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING_AR2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING_AR2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING_DQRQPOP 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING_DQRQPOP_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING_DQRQPOP_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING_NOP2MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING_NOP2MRS_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING_NOP2MRS_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0 0x00900220 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING0_RC 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RFC 22:12 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_0_TIMING0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RFC_MAX 0x000003FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RAS 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RAS_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1 0x00900224 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING1_R2W 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING1_R2W_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2W_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING1_R2W_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2W_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2W__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2R 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING1_W2R_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_0_TIMING1_W2R_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2R_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2R__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2P 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING1_R2P_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING1_R2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2P_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_R2P__PROD_C_SAMSUNG_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2P 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING1_W2P_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING1_W2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2P_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TIMING1_W2P__PROD_C_SAMSUNG_DDR3 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2 0x00900228 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING2_RD_RCD 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING2_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_TIMING2_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_RD_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_RD_RCD__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WR_RCD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING2_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING2_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WR_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WR_RCD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_RRD 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING2_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING2_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_RRD_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_RRD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING2_WDV_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING2_WDV_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV__PROD_C_WL1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV__PROD_C_WL6 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TIMING2_WDV__PROD_C_SAMSUNG_DDR3 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3 0x0090022C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING3_QUSE 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING3_QUSE_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_0_TIMING3_QUSE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QUSE_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QUSE__PROD_C_CL11 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QUSE__PROD_C_SAMSUNG_DDR3 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QRST 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING3_QRST_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING3_QRST_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QRST_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QRST__PROD_C_CL11 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QRST__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QSAFE 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING3_QSAFE_17 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING3_QSAFE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_QSAFE_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_RDV 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING3_RDV_60 0x0000003C /* RWI-V */ #define NV_PFB_FBPA_0_TIMING3_RDV_27 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_RDV_MIN 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_RDV_MAX 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_RDV__PROD_C_CL11 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_TIMING3_RDV__PROD_C_SAMSUNG_DDR3 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_TIMING4 0x00900230 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING4_PDEX2WR 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING4_PDEX2WR_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2WR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2WR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2WR__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2RD 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING4_PDEX2RD_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2RD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2RD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEX2RD__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_FAW 28:20 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING4_FAW_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_FAW_40 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING4_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_FAW_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_FAW__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_MSB 30:29 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING4_PDEN2PDEX_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING5 0x00900234 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING5_PCHG2PDEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING5_PCHG2PDEN_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING5_PCHG2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_PCHG2PDEN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_PCHG2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_RW2PDEN 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING5_RW2PDEN_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_0_TIMING5_RW2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_RW2PDEN_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_RW2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_ACT2PDEN 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING5_ACT2PDEN_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_TIMING5_ACT2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_ACT2PDEN_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_ACT2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_AR2PDEN 31:23 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING5_AR2PDEN_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_0_TIMING5_AR2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_AR2PDEN_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING5_AR2PDEN__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_TIMING6 0x00900238 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING6_PPD 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING6_PPD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING6_BUS_W2R 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING6_BUS_W2R_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING6_BUS_W2R_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_DRAMC 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_DRAMC_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_DRAMC_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO_70 0x00000046 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO_20 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_TIMING6_CMD2MCIDLE_FBIO_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING7 0x0090023C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING7_REXT 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING7_REXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING7_WEXT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING7_WEXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING7_ATR 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING7_ATR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING7_ATR_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING7_ATR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING7_ATRLEN 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING7_ATRLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING7_ATRLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING7_ATRLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING8 0x00900240 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING8__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING8_ODT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING8_ODT_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING8_ODT_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_ODT_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_ODTLEN 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING8_ODTLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_ODTLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING8_ODTLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_QPOP_OFFSET 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING8_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_QPOP_OFFSET_ELEVEN 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_0_TIMING8_QPOP_OFFSET_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_RPRE 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING8_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING8_RPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_WPRE 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING8_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING8_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING8_WPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING9 0x00900244 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING9__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING9_CCDL 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING9_CCDL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING9_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TIMING9_CCDL_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING9_CCDS 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING9_CCDS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING9_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING9_CCDS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_ADR 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_ADR_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_WCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_WCK_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_WREDC 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING9_QPOP_OFFSET_WREDC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10 0x00900248 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING10__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_WCK2TR 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_WCK2TR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_LTLTR 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_LTLTR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_LTL7TR 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_LTL7TR_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_MRD 22:17 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_MRD_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS_MSB2 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS_MSB2_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_REFTR 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_REFTR_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_REFTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING10_REFTR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING10_WCK2TR_MSB 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_WCK2TR_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS_MSB 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING10_WCK2MRS_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11 0x0090024C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING11__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING11_ADZ 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING11_ADZ_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11_WTR_RCD 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING11_WTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11_WTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_WTR_RCD_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_LTR_RCD 14:10 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING11_LTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11_LTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_LTR_RCD_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_LTRTR 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING11_LTRTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_LTRTR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11_LTRTR_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_KO 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING11_KO_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING11_KO_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING11_KO_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING12 0x00900250 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING12__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING12_RDCRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING12_RDCRC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING12_CKE 9:4 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING12_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING12_CKE_5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TIMING12_CKSRE 13:10 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING12_CKSRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING12_CKSRE_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TIMING12_LOCKPLL 29:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING12_LOCKPLL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING12_LOCKPLL_3000 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING12_LOCKPLL_MAX 0x00003FFF /* RW--V */ #define NV_PFB_FBPA_0_TIMING13 0x00900254 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING13__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK_5 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK_MSB 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASREX2CLK_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD_MSB 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX_MSB 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD_120 0x00000078 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASR2NRD__PROD_C_SAMSUNG_DDR3 0x00000078 /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX_5K 0x00001388 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX_MAX 0x0000FFFF /* RW--V */ #define NV_PFB_FBPA_0_TIMING13_ASR2ASREX__PROD_C_SAMSUNG_DDR3 0x00004E20 /* RW--V */ #define NV_PFB_FBPA_0_TIMING14 0x00900258 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING14__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING14_ZQCS 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING14_ZQCS_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING14_ZQCL 17:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING14_ZQCL_100 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING15 0x0090025C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING15__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING15_RDRET 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING15_RDRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING15_WRRET 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING15_WRRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING15_RDINTRP 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING15_RDINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING15_WRINTRP 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING15_WRINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING16 0x00900260 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING16__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING16_RDFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING16_RDFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING16_WRFLUSH 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING16_WRFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING16_RP 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING16_RP_10 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING16_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING16_RP_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING16_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TIMING16_WCK_QRST 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING16_WCK_QRST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING17 0x00900264 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING17__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING17_RDRET_PRE 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING17_RDRET_PRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING17_WCK2RDWCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING17_WCK2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING17_MRS2RDWCK 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING17_MRS2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING18 0x00900268 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING18__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING18_WRCRCFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING18_WRCRCFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING18_REXT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING18_REXT_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING18_QUSE_SETTLE 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING18_QUSE_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING18_DLCELL_SETTLE 29:21 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING18_DLCELL_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING19 0x0090026C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING19__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING19_QRST_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING19_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING19_QRST_FLUSH 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING19_QRST_FLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING19_MPRR 16:10 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING19_MPRR_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING20 0x0090028C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING20__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING20_RD_REFRESH 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING20_RD_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING20_WR_REFRESH 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING20_WR_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21 0x00900390 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING21__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING21_REFSB 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_FORCE_FULL 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_FORCE_FULL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_FORCE_FULL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DUAL_REQUEST 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DUAL_REQUEST_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DUAL_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DELAYED_THRESHOLD 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DELAYED_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_FULL_REF_PERIOD 19:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_FULL_REF_PERIOD_INIT 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DISPATCH_PERIOD 31:22 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING21_REFSB_DISPATCH_PERIOD_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING22 0x00900394 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING22__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING22_RFCSBA 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING22_RFCSBA_INIT 0x00000032 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING22_RFCSBR 17:10 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING22_RFCSBR_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING22_RFCSBA_MSB 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING22_RFCSBA_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23 0x0090039C /* RW-4R */ #define NV_PFB_FBPA_0_TIMING23__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING23_CCDR 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING23_CCDR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23_CCDR_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TIMING23_RD_RANK_SEL_DELAY 10:4 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING23_RD_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23_WR_RANK_SEL_DELAY 17:11 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING23_WR_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TIMING23_WR_CCDS_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TIMING24 0x009003E0 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING24__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING24_RRDL 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING24_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING24_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING24_RRDL_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TIMING24_CCDMW 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING24_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING24_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_TIMING24_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING24_CCDMW_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TIMING24_LPDDR4_RDV_OFFSET 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING24_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING24_ABPA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING24_ABPA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING24_XS_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING24_XS_OFFSET_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING25 0x009003EC /* RW-4R */ #define NV_PFB_FBPA_0_TIMING25__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING25_ZQCAL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING25_ZQCAL_1_US 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING25_MRRW 21:13 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING25_MRRW_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING25_MRRWL 30:22 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING25_MRRWL_256 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING26 0x009024E0 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING26__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING26_RFC_DLR 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING26_RFC_DLR_58 0x0000003A /* RWI-V */ #define NV_PFB_FBPA_0_TIMING26_RFC_DLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TIMING26_RFC_DLR_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_0_TIMING27 0x009024E4 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING27__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING27_REFSR 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING27_REFSR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING27_REFSR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING28 0x009024E8 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING28__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING28_WRIDON 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING28_WRIDON_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING28_WRIDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING28_WRIDOFF_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING28_NOP2QPOP 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING28_NOP2QPOP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING28_NOP2MRS 22:18 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING28_NOP2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING28_TKO2MRS 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING28_TKO2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING29 0x009024EC /* RW-4R */ #define NV_PFB_FBPA_0_TIMING29__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING29_TDCC1 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING29_TDCC1_INIT 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING29_TDCC2 29:16 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING29_TDCC2_INIT 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_0_TIMING30 0x009024FC /* RW-4R */ #define NV_PFB_FBPA_0_TIMING30__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_INIT 0x0000013C /* RWI-V */ #define NV_PFB_FBPA_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_GDDR6 0x0000013C /* RW--V */ #define NV_PFB_FBPA_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_SDDR4 0x00000278 /* RW--V */ #define NV_PFB_FBPA_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_HBM2 0x0000009E /* RW--V */ #define NV_PFB_FBPA_0_TIMING30_FBIO_CKE_CKOFF_SKEW 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING30_FBIO_CKE_CKOFF_SKEW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TIMING31 0x009024F8 /* RW-4R */ #define NV_PFB_FBPA_0_TIMING31__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING31_XSMRS 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_TIMING31_XSMRS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_0 0x009024F0 /* RW-4R */ #define NV_PFB_FBPA_0_POWER_0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRUP_RD_INTERP 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRUP_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRDN_RD_INTERP 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRDN_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRUP_WR_INTERP 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRUP_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRDN_WR_INTERP 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_0_OFFSET_PWRDN_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_1 0x009024F4 /* RW-4R */ #define NV_PFB_FBPA_0_POWER_1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRUP_RCVR 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRUP_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRDN_RCVR 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRDN_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRUP_RX_CLK 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRUP_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRDN_RX_CLK 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_POWER_1_OFFSET_PWRDN_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL0 0x00902300 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL0_DELAY_REF 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL0_DELAY_REF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL0_BLCG_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL0_BLCG_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL1 0x00902304 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL2 0x00902308 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL3 0x0090230C /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL4 0x00902310 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL5 0x00902314 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL6 0x00902318 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL7 0x0090231C /* RW-4R */ #define NV_PFB_FBPA_0_ASR_CTRL7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0 0x00902320 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0_STALL_DELAY 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL0_STALL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0_INV_BW_EVAL 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL0_INV_BW_EVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0_EN_WCKTR 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL0_EN_WCKTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0_CHECK_DISPLAY_OK 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL0_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL0_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACPD_CTRL1 0x00902324 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL2 0x00902328 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL3 0x0090232C /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL4 0x00902330 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL5 0x00902334 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL6 0x00902338 /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL7 0x0090233C /* RW-4R */ #define NV_PFB_FBPA_0_ACPD_CTRL7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_ACPD_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL 0x00902444 /* RW-4R */ #define NV_PFB_FBPA_0_DQR_CTRL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_CTRL_PERIOD 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_SET 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_SET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_CLR 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_CLR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC0_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC0_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC1_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_CTRL_EN_IC1_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP0 0x009024C0 /* R--4R */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP1 0x009024C4 /* R--4R */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC0_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP0 0x009024C8 /* R--4R */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP1 0x009024CC /* R--4R */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_DQR_STATUS_DQ_IC1_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD 0x009024D0 /* RW-4R */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC0_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DQR_STATUS_VLD_IC1_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CONFIG0 0x00900290 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG0_RC 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RC_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RFC 16:8 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RFC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RAS 23:17 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RAS_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RP 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG0_RP_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG0_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RP_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_USE_TIMING_REGS 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG0_USE_TIMING_REGS_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_USE_TIMING_REGS_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG0_USE_TIMING_REGS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG0_USE_TIMING_REGS_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1 0x00900294 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG1_CL 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG1_CL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG1_CL_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_CL_MAX 0x00000024 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_WL 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG1_WL_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG1_WL_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_WL_MAX 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_RD_RCD 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG1_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG1_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_RD_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_WR_RCD 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG1_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG1_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_WR_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_HBM_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_G6_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_G6_HS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_G6X_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_CONFIG1_QPOP_OFFSET_G6X_HS 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2 0x00900298 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG2_RPRE 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_RPRE_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_WPRE 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_WPRE_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_CDLR 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_CDLR_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_CDLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_CDLR_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_WR 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_WR_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_WR_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_WR_MAX 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_W2R_BUS 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_W2R_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_W2R_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_W2R_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_R2W_BUS 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG2_R2W_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG2_R2W_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG2_R2W_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3 0x0090029C /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG3_PDEX 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_PDEX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_PDEX_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_PDEN2PDEX 8:5 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_FAW 16:9 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_FAW_40 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_FAW_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_AOND 23:17 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_AOND_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_AOND_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_AOND_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_AOND_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_CCDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_CCDL_MAX 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG3_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG3_CCDS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG3_CCDS_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4 0x009002A0 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO_1F 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO_MIN 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO_3_9_US 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_LO_7_8_US 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH 14:3 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_11 0x0000002F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_MAX 0x00000FFF /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_3_9_US 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH_7_8_US 0x0000001A /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_REFRESH__PROD_C_SAMSUNG_DDR3 0x0000002F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_RRD 20:15 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG4_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG4_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_RRD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_DDR5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_DDR5X 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_DDR6 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_HBM 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_SDDR4 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY__PROD_C_LEGACY 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_IDLE_DELAY_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC 31:27 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_18 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_26 0x0000001A /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5X 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6X 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_HBM 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_SDDR4 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_LEGACY 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG5 0x009002A4 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG5_ADR_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_ADR_MIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_WRCRC 10:4 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_WRCRC_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_WRCRC_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG5_WRCRC_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_CONFIG5_QSAFE_OFFSET 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_QSAFE_OFFSET_39 0x00000027 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_INTRP_MSB 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_INTRP_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_RDRET_OFFSET 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_RDRET_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_WRRET_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_WRRET_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG5_INTRP 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG5_INTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6 0x009002A8 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG6_RDFLUSH_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_RDFLUSH_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_WRFLUSH_OFFSET 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_WRFLUSH_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG6_WDAT_LATENCY 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_WDAT_LATENCY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_PPD 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_PPD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_SDDR4_RDV_OFFSET 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_SDDR4_RDV_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_CMD_ADJUST 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG6_CMD_ADJUST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG6_CMD_ADJUST_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG7 0x009002AC /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG7_ZQCS_INTERVAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG7_ZQCS_INTERVAL_64 0x0061A800 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG7_ZQCS_INTERVAL_128 0x00C35000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG8 0x009002CC /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG8__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG8_ATR_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG8_ATR_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG8_ATR_PADDING 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG8_ATR_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG8_ODT_PADDING 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG8_ODT_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG8_WCK2PH 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG8_WCK2PH_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG8_MRSTWCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG8_MRSTWCK_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9 0x009002E8 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG9__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG9_QUSE_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_QUSE_OFFSET_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9_QUSE_DDLL_SETTLE 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_QUSE_DDLL_SETTLE_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9_REXT_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_REXT_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9_DLCELL_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_DLCELL_SETTLE_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9_QRST_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG9_MPRR 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG9_MPRR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10 0x009002F4 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG10__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG10_RFC_MSB 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_RFC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_PDEN2PDEX_MSB 6:5 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_PDEN2PDEX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_RD_RCD_MSB 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_RD_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_WR_RCD_MSB 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_WR_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI 17:14 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_SDDR4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_IDLE_DELAY_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG10_RDRET_OFFSET_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG10_RDRET_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11 0x009003E4 /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG11__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG11_RRDL 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_RRDL_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_CCDMW 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_CCDMW_MAX 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_MTA 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_MTA_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_MTA_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_WPOST 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_LPDDR4_RDV_OFFSET 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_WEXT_OFFSET 22:19 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_WEXT_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_RPRE_TOGGLE 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_RPRE_TOGGLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG11_RPRE_TOGGLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_RD_RANK_SEL_DELAY 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_RD_RANK_SEL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG11_WR_RANK_SEL_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG11_WR_RANK_SEL_DELAY_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG12 0x0090015C /* RW-4R */ #define NV_PFB_FBPA_0_CONFIG12__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFIG12_BLDIV 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG12_BLDIV_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG12_ADR_TERM 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG12_ADR_TERM_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG12_ADR_TERM_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFIG12_ADRTR_FIFO_MARGIN 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG12_ADRTR_FIFO_MARGIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG12_CABI_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_CONFIG12_CABI_MODE_DC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFIG12_CABI_MODE_AC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TIMING0_GEN 0x009002B0 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING0_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING0_GEN_RC 8:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING0_GEN_RC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING0_GEN_RFC 22:12 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING0_GEN_RFC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING0_GEN_RAS 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING0_GEN_RAS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING1_GEN 0x009002B4 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING1_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING1_GEN_R2W 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING1_GEN_R2W_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING1_GEN_W2R 14:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING1_GEN_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING1_GEN_R2P 20:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING1_GEN_R2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING1_GEN_W2P 30:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING1_GEN_W2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING2_GEN 0x009002B8 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING2_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING2_GEN_RD_RCD 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING2_GEN_RD_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING2_GEN_WR_RCD 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING2_GEN_WR_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING2_GEN_RRD 22:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING2_GEN_RRD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING2_GEN_WDV 28:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING2_GEN_WDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING3_GEN 0x009002BC /* R-I4R */ #define NV_PFB_FBPA_0_TIMING3_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING3_GEN_QUSE 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING3_GEN_QUSE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING3_GEN_QRST 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING3_GEN_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING3_GEN_QSAFE 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING3_GEN_QSAFE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING3_GEN_RDV 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING3_GEN_RDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING4_GEN 0x009002C0 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING4_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEX2WR 5:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEX2WR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEX2RD 13:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEX2RD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEN2PDEX 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEN2PDEX_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING4_GEN_FAW 28:20 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING4_GEN_FAW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEN2PDEX_MSB 30:29 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING4_GEN_PDEN2PDEX_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING5_GEN 0x009002C4 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING5_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING5_GEN_PCHG2PDEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING5_GEN_PCHG2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING5_GEN_RW2PDEN 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING5_GEN_RW2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING5_GEN_ACT2PDEN 22:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING5_GEN_ACT2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING5_GEN_AR2PDEN 31:23 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING5_GEN_AR2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING6_GEN 0x009002C8 /* R--4R */ #define NV_PFB_FBPA_0_TIMING6_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING6_GEN_PPD 4:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING6_GEN_PPD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING6_GEN_BUS_W2R 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING6_GEN_BUS_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING6_GEN_CMD2MCIDLE_DRAMC 21:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING6_GEN_CMD2MCIDLE_DRAMC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING6_GEN_CMD2MCIDLE_FBIO 30:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING6_GEN_CMD2MCIDLE_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING7_GEN 0x009002D0 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING7_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING7_GEN_REXT 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING7_GEN_REXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING7_GEN_WEXT 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING7_GEN_WEXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING7_GEN_ATR 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING7_GEN_ATR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING7_GEN_ATRLEN 28:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING7_GEN_ATRLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING8_GEN 0x009002D4 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING8_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING8_GEN_ODT 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING8_GEN_ODT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING8_GEN_ODTLEN 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING8_GEN_ODTLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING8_GEN_QPOP_OFFSET 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING8_GEN_QPOP_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING8_GEN_RPRE 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING8_GEN_RPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING8_GEN_WPRE 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING8_GEN_WPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING9_GEN 0x009002D8 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING9_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING9_GEN_CCDL 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING9_GEN_CCDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING9_GEN_CCDS 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING9_GEN_CCDS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_ADR 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_ADR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_WCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_WCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_WREDC 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING9_GEN_QPOP_OFFSET_WREDC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING15_GEN 0x009002DC /* R-I4R */ #define NV_PFB_FBPA_0_TIMING15_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING15_GEN_RDRET 6:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING15_GEN_RDRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING15_GEN_WRRET 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING15_GEN_WRRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING15_GEN_RDINTRP 22:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING15_GEN_RDINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING15_GEN_WRINTRP 30:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING15_GEN_WRINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING16_GEN 0x009002E0 /* R--4R */ #define NV_PFB_FBPA_0_TIMING16_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING16_GEN_RDFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING16_GEN_RDFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING16_GEN_WRFLUSH 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING16_GEN_WRFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING16_GEN_RP 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING16_GEN_RP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING16_GEN_WCK_QRST 26:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING16_GEN_WCK_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING17_GEN 0x009002E4 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING17_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING17_GEN_RDRET_PRE 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING17_GEN_RDRET_PRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING17_GEN_WCK2RDWCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING17_GEN_WCK2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING17_GEN_MRS2RDWCK 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING17_GEN_MRS2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING18_GEN 0x009002EC /* R--4R */ #define NV_PFB_FBPA_0_TIMING18_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING18_GEN_WRCRCFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING18_GEN_WRCRCFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING18_GEN_REXT 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING18_GEN_REXT_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING18_GEN_QUSE_SETTLE 20:16 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING18_GEN_QUSE_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING18_GEN_DLCELL_SETTLE 29:21 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING18_GEN_DLCELL_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING19_GEN 0x009002F0 /* R--4R */ #define NV_PFB_FBPA_0_TIMING19_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING19_GEN_QRST_OFFSET 4:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING19_GEN_QRST_OFFSET_INIT 0x00000002 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING19_GEN_QRST_FLUSH 9:5 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING19_GEN_QRST_FLUSH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING19_GEN_MPRR 16:10 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING19_GEN_MPRR_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING19_GEN_REFSB_SUBP0 17:17 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING19_GEN_REFSB_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING19_GEN_REFSB_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING19_GEN_REFSB_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING20_GEN 0x00900288 /* R--4R */ #define NV_PFB_FBPA_0_TIMING20_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING20_GEN_RD_REFRESH 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING20_GEN_RD_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING20_GEN_WR_REFRESH 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING20_GEN_WR_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_0_TIMING22_GEN 0x009003F8 /* R--4R */ #define NV_PFB_FBPA_0_TIMING22_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBA 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBA_INIT 0x00000032 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBR 17:10 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBR_INIT 0x00000020 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBA_MSB 21:20 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING22_GEN_RFCSBA_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING24_GEN 0x009003E8 /* R-I4R */ #define NV_PFB_FBPA_0_TIMING24_GEN__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TIMING24_GEN_RRDL 6:0 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING24_GEN_RRDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING24_GEN_CCDMW 14:8 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING24_GEN_CCDMW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING24_GEN_LPDDR4_RDV_OFFSET 18:15 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING24_GEN_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING24_GEN_ABPA 25:20 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING24_GEN_ABPA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TIMING24_GEN_XS_OFFSET 31:26 /* R-IVF */ #define NV_PFB_FBPA_0_TIMING24_GEN_XS_OFFSET_INIT 0x0000000A /* R-I-V */ #define NV_PFB_FBPA_0_PTR_RESET 0x00900158 /* RW-4R */ #define NV_PFB_FBPA_0_PTR_RESET__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PTR_RESET_TESTCMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_PTR_RESET_TESTCMD_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PTR_RESET_TESTCMD_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PTR_RESET_WDATFIFO 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_PTR_RESET_WDATFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PTR_RESET_WDATFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PTR_RESET_EDCFIFO 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_PTR_RESET_EDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PTR_RESET_EDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PTR_RESET_RRDATAFIFO 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_PTR_RESET_RRDATAFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PTR_RESET_RRDATAFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PTR_RESET_RREDCFIFO 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_PTR_RESET_RREDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PTR_RESET_RREDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP 0x00900384 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_EN 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_EN_ENABLE_LAT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_RES_THRES 15:4 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_RES_THRES_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_LAT_THRES 27:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_STALL_WKUP_LAT_THRES_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_ASR_WAKEUP 0x009002F8 /* RW-4R */ #define NV_PFB_FBPA_0_ASR_WAKEUP__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ASR_WAKEUP_CNT 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_WAKEUP_CNT_5K 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_ENABLE_STD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_ENABLE_STRICT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_ENABLE_TIMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_EN_ENABLE_NISO 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_ASR_WAKEUP_PIPE 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_ASR_WAKEUP_PIPE_16 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR 0x009002FC /* RW-4R */ #define NV_PFB_FBPA_0_DRAM_ASR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DRAM_ASR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRPD 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRPD_NO_POWERDOWN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRPD_POWERDOWN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRCLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRCLK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_ASRCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_NOISO 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_NOISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_NOISO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_PREA 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_PREA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_PREA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_NO_WCKTR 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_NO_WCKTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_NO_WCKTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_REF 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_REF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_REF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_ACPD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_ACPD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_ACPD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_ZQ 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_ZQ_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_ZQ_CL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_ZQ_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_DRAM_ASR_CHECK_DISPLAY_OK 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_DRAM_ASR_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAM_ASR_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS 0x00900300 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS__PRIV_LEVEL_MASK 0x00902250 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_HBM_RDBI 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_WL 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_WL 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_HBM_WDBI 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_CL 6:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_CL 6:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR5_WR 11:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_ADR_GDDR6X_WR 11:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS 0x00900304 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_ADR_RTT_NOM 10:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_EMRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT 0x00900308 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS_EXT_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT 0x0090030C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS_EXT_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_REF 0x00900310 /* -W-4R */ #define NV_PFB_FBPA_0_REF__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REF_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_0_REF_CMD_REFRESH 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_REF_CMD_REFRESH_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_REF_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_0_REF_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_REF_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_REF_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_REF_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_REF_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_0_REF_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_REF_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_REF_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_REF_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_REF_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_0_REF_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_REF_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_REF_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_REF_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_PRE 0x00900314 /* -W-4R */ #define NV_PFB_FBPA_0_PRE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PRE_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_0_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_PRE_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_0_PRE_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_PRE_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_PRE_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_PRE_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_PRE_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_0_PRE_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_PRE_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_PRE_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_PRE_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_PRE_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_0_PRE_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_PRE_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_PRE_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_0_PRE_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_0_NOP 0x00900318 /* -W-4R */ #define NV_PFB_FBPA_0_NOP__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_NOP_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_0_NOP_CMD_NOP 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_NOP_CMD_NOP_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_SELF_REF 0x0090031C /* RW-4R */ #define NV_PFB_FBPA_0_SELF_REF__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_SELF_REF_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_SELF_REF_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SELF_REF_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_SELF_REF_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_SELF_REF_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_SELF_REF_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_SELF_REF_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_SELF_REF_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2 0x00900320 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_ADR_CWL 5:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_BA__PROD_C_SAMSUNG_DDR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS3 0x00900324 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT 0x00900328 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS2_EXT_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT 0x0090032C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_EMRS3_EXT_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1 0x00900330 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_HBM_WR 4:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_HBM_DRV 7:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_NORMAL 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_FIXED 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_40 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_48 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM 5:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_CKE_VAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_RDBI 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_RDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_RDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_MTA 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_MTA_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_MTA_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_WDBI 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_WDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_WDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_PAM4 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_PAM4_PAM4 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_PAM4_GDDR6 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ABI 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_ABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CABI 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR6X_CABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET 11:11 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS1_BA_MRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS1_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS1_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2 0x00900334 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_HBM_WL 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_HBM_RL 7:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR5_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR5_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR5_DATA_WCK_TERM_OFFSET 8:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR5_ADDRESS_TERM_OFFSET 11:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF 7:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_ATCSR 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST 11:11 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_NO 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_YES 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS2_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS2_BA_MRS 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS2_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS2_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS2_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3 0x00900338 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH 1:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_16MS 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_8MS 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_HBM_RAS 5:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_DATA_TERM_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV 3:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING 4:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_RDQS 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_RDQS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_RDQS_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_CA_TERM_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_INFO_VENDOR_ID 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID1 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID2 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM 9:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING 9:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_1X 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_2X 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_ENABLED 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_3 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_4 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_ON 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS3_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS3_BA_MRS 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS3_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS3_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS3_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4 0x0090033C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV 11:11 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV 11:11 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_BA_MRS 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5 0x00900340 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP1 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP1_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP1_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_PLL_BANDWIDTH 5:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR5_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_RAS_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_ADR_GDDR6X_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_DM 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_DM_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_DM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_WDBI 11:11 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_WDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_WDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RDBI 12:12 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_BA_MRS 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6 0x00900344 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREFD 3:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREFD_EXTERNAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREFD_INTERNAL 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE23 7:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE01 11:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS6_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7 0x00900348 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_1DB 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_2DB 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_40 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_48 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_5 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_35 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_2 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_35 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_25 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DCC_HOLD 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR5_DCC_RESET 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_DCC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_ADR_GDDR6X_DCC_HOLD 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS7_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS7_BA_MRS 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS7_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS7_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS7_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8 0x00900354 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS8__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM 1:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_80 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ 3:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO 4:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO_RESET 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO_PROG 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_DIS 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_EN 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_REFPB 7:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_REFPB_PB 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_REFPB_P2B 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6_CATH 3:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6_PLL_RANGE 4:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_ADR_GDDR6_MICRON_PLL_RANGE_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS8_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS8_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS8_BA_MRS 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS8_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS8_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS8_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9 0x00900358 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS9__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR5_PRE_EMPHASIS 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK 1:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDL 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDM 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDU 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ 6:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_ADR_GDDR6X_PIN_SUB_ADDRESS 11:7 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS9_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10 0x00902200 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS10__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET 3:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT 5:4 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT 7:6 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET_MSB 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM 11:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS10_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS10_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS10_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS10_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS10_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11 0x00902204 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS11__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS11_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS11_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS11_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS11_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS11_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS11_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS11_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12 0x00902208 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS12__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_LSB 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_MSB 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_PRBS 2:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_PRBS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_PRBS_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK 11:3 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS12_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS12_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS12_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS12_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS12_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13 0x0090220C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS13__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS13_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS13_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS13_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS13_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS13_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS13_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS13_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14 0x0090035C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS14__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR_MICRON_CORE_VOLTAGE 4:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS14_ADR_MICRON_SUBREG_SELECT 11:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS14_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15 0x0090034C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS15__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_HBM_IVREF 2:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREA 0:0 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREA_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREA_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREB 1:1 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREB_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_MREB_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_CADT 3:2 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_CADT_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_CADT_RISING 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_CADT_FALLING 0x00000002 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR6X_CADT_CABI 0x00000003 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0 8:8 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1 9:9 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING 10:10 /* ----F */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS15_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS15_BA_MRS 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS15_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS15_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS15_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16 0x00902210 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS16__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS16_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS16_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS16_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS16_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS16_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS16_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS16_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17 0x00902214 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS17__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS17_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS17_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS17_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS17_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS17_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS17_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS17_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18 0x00902218 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS18__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS18_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS18_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS18_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS18_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS18_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS18_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS18_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19 0x0090221C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS19__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS19_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS19_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS19_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS19_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS19_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS19_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS19_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20 0x00902220 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS20__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS20_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS20_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS20_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS20_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS20_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS20_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS20_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22 0x00902224 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS22__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS22_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS22_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS22_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS22_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS22_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS22_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS22_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23 0x00902228 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS23__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS23_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS23_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS23_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS23_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS23_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS23_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS23_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24 0x0090222C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS24__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS24_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS24_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS24_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS24_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS24_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS24_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS24_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25 0x00902230 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS25__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS25_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS25_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS25_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS25_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS25_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS25_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS25_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32 0x00902234 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS32__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS32_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS32_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS32_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS32_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS32_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS32_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS32_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40 0x00902238 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS40__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS40_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS40_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS40_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS40_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS40_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS40_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS40_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_MRR 0x0090223C /* RW-4R */ #define NV_PFB_FBPA_0_MRR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_MRR_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_MRR_CMD_MRR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MRR_CMD_MRR_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MRR_BA 6:1 /* RWIVF */ #define NV_PFB_FBPA_0_MRR_BA_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MRR_RANK 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_MRR_RANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MRR_CH 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_MRR_CH_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_VLD_SUBP0 10:10 /* R-IVF */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_VLD_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_SUBP0 18:11 /* R-IVF */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_VLD_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_VLD_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_SUBP1 27:20 /* R-IVF */ #define NV_PFB_FBPA_0_MRR_GEN_DATA_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_MPC 0x00902240 /* RW-4R */ #define NV_PFB_FBPA_0_MPC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_MPC_ADR 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_MPC_ADR_NOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MPC_ADR_START_DQS_OSC 0x0000004b /* RW--V */ #define NV_PFB_FBPA_0_MPC_ADR_STOP_DQS_OSC 0x0000004d /* RW--V */ #define NV_PFB_FBPA_0_MPC_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_MPC_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MPC_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MPC_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_MPC_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_MPC_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_MPC_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MPC_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MPC_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_MPC_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_MPC_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_MPC_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MPC_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MPC_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_MPC_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC 0x00900350 /* RW-4R */ #define NV_PFB_FBPA_0_MISC_DRAMC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_BANK_SEQ 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_BANK_SEQ_INC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_BANK_SEQ_BG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_TR_RW_ALL_BANK 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_TR_RW_ALL_BANK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_TR_RW_ALL_BANK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_IDLE_ON_TR 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_IDLE_ON_TR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_IDLE_ON_TR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_ACT_HIGH_PRIORITY 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_ACT_HIGH_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_ACT_HIGH_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_HOLDOFF_WRACT 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_HOLDOFF_WRACT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_HOLDOFF_WRACT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_WR_FEEDBACK 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_WR_FEEDBACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_WR_FEEDBACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_BG_ENABLE_ON_CCD 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_BG_ENABLE_ON_CCD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_BG_ENABLE_ON_CCD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_ENABLE_RRDL_COUNTER 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_ENABLE_RRDL_COUNTER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_ENABLE_RRDL_COUNTER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_KILL_PEND_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_KILL_PEND_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_KILL_PEND_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_TR_SAFE_SCHED 18:12 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_TR_SAFE_SCHED_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_ABPA_PER_RANK 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_ABPA_PER_RANK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_MAX_BANK_HITS 26:20 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_MAX_BANK_HITS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_MAX_BANK_HITS_MAX 0x0000007E /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_PRIORITY 28:27 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_PRIORITY_HIGHEST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_PRIORITY_MEDIUM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_PRIORITY_LOWEST 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_GBL_RRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_GBL_RRD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_PBR_GBL_RRD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_CMDQ_ALWAYS_ON 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_CMDQ_ALWAYS_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_CMDQ_ALWAYS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MISC_DRAMC_FORCE_G5_TO_G5X 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_MISC_DRAMC_FORCE_G5_TO_G5X_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MISC_DRAMC_FORCE_G5_TO_G5X_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_IC_CTRL 0x00900208 /* RW-4R */ #define NV_PFB_FBPA_0_IC_CTRL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_DIRECTION_SYNC 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_DIRECTION_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_DIRECTION_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_IC_CTRL_SP2DRAMC_FLOP 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_IC_CTRL_SP2DRAMC_FLOP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_IC_CTRL_SP2DRAMC_FLOP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO 0x009023FC /* RW-4R */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO_THRESHOLD 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO_STALL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_STALL_CMD_FIFO_STALL_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0 0x00900360 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1 0x00900364 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0 0x00900368 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1 0x0090036C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS9_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0 0x00900370 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1 0x00900374 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS14_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT 0x00900378 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS4_EXT_BA_MRS4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT 0x0090037C /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS5_EXT_BA_MRS5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT 0x00900380 /* RW-4R */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_GENERIC_MRS6_EXT_BA_MRS6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_CG1 0x00900280 /* RW-4R */ #define NV_PFB_FBPA_0_CG1__PRIV_LEVEL_MASK 0x009001B4 /* */ #define NV_PFB_FBPA_0_CG1_SLCG_TRAINING 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_TRAINING_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_TRAINING_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIV 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIV_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_REPLAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_REPLAY_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_REPLAY_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SS2PACMD1 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SS2PACMD1_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SS2PACMD1_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_FABSCAN 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_FABSCAN_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_FABSCAN_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIVSYNC 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIVSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_PRIVSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_6 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_6_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_6_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_PAF2TSUBP 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_PAF2TSUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_PAF2TSUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_ILA 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_ILA_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_ILA_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_PAL 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_PAL_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_PAL_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_10 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_10_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_10_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_11 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_11_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_11_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_12 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_12_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_12_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_13 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_13_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_13_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_14 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_14_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_14_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_15_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_15_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_16 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_16_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_16_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_17 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_17_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_17_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_18 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_18_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_18_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_19 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_19_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_19_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_20 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_20_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_20_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_21 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_21_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_21_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_22 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_22_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_22_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_23 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_23_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_23_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_24 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_24_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_24_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_25 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_25_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_25_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_26 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_26_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_26_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_27 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_27_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_27_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_28 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_28_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_28_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_29 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_29_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_29_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_30 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_30_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_30_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_31 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_31_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG1_SLCG_SPARE_31_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG1_SLCG 31:0 /* ----F */ #define NV_PFB_FBPA_0_CG1_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_CG1_SLCG_DISABLED 0xFFFFFFFF /* ----V */ #define NV_PFB_FBPA_0_CG1_SLCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_CG2 0x00900284 /* RW-4R */ #define NV_PFB_FBPA_0_CG2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CG2_FGCG_FAB_INTFC 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_FAB_INTFC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_FAB_INTFC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_SUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_SUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG_MISC 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_MISC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG_FABRIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG_PRI_REG_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_PRI_REG_UPDATE_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_PRI_REG_UPDATE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG_CMD_FABRIC 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_CG2_FGCG_CMD_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CG2_FGCG_CMD_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CG2_FGCG 5:0 /* ----F */ #define NV_PFB_FBPA_0_CG2_FGCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_CG2_FGCG_DISABLED 0x0000003F /* ----V */ #define NV_PFB_FBPA_0_CG2_FGCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_READ_FT_CFG 0x00900400 /* RW-4R */ #define NV_PFB_FBPA_0_READ_FT_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_CHAIN 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_CHAIN_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_CHAIN_32 0x0000001f /* RW--V */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_CHAIN_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_LIST_SIZE 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_LIST_SIZE_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_READ_FT_CFG_MAX_LIST_SIZE_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_READ_FT_CFG_PAGE_SIZE 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_READ_FT_CFG_PAGE_SIZE_1K 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_READ_FT_CFG_PAGE_SIZE_2K 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_READ_FT_CFG_SET_SWIZZLE 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_READ_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG 0x00900410 /* RW-4R */ #define NV_PFB_FBPA_0_WRITE_FT_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_8 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_EVICT_ON_CLEAN 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_EVICT_ON_CLEAN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_EVICT_ON_CLEAN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL 18:12 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_DISABLE 0x0000007f /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_SET_SWIZZLE 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD_3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG 0x00900420 /* RW-4R */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG 0x00900430 /* RW-4R */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0 0x00900440 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_LATENCY_INTERVAL 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_LATENCY_INTERVAL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_LATENCY_INTERVAL_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_F 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_READ_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_WRITE_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1 0x00900444 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_SNAPSHOT_ARB 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_SNAPSHOT_ARB_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_SNAPSHOT_ARB_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2 0x00900448 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_READ_SEC_THRESHOLD 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_READ_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_READ_SEC_OFFSET 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_READ_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_WRITE_SEC_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG2_WRITE_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3 0x0090046C /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_LATENCY_USES_LTCCLK 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG3_LATENCY_USES_LTCCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4 0x009004BC /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4_READ_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4_READ_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4_WRITE_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG4_WRITE_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5 0x00902580 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6 0x00902584 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7 0x00902588 /* RW-4R */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG 0x00900450 /* RW-4R */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WRITEPULL_REQ 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WRITEPULL_REQ_IMM 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_WRITEPULL_REQ_WAIT_RWDIR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_USE_DRAMC_BUSY 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_USE_DRAMC_BUSY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_USE_DRAMC_BUSY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH 17:13 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_NOLIMIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_PRIORITY 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_PRIORITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_PRIORITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB_NOLIMIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_DELAY 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_DELAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_WRITE_ARB_CFG_CCDMW_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG 0x00900454 /* RW-4R */ #define NV_PFB_FBPA_0_READ_ARB_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_READ_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_POLICY 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG 0x00900460 /* RW-4R */ #define NV_PFB_FBPA_0_ACT_ARB_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_RD_SUBPACKETS 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_RD_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_RESNAP_DURING_TURN 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_RESNAP_DURING_TURN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_RESNAP_DURING_TURN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SNAP_BASED_ON_VC 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SNAP_BASED_ON_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SNAP_BASED_ON_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_WR_SUBPACKETS 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_WR_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_BGSEC 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_BGSEC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_BGSEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_BANKQ_ENTRIES 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_BANKQ_ENTRIES_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MAX_SKIP_COUNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MAX_SKIP_COUNT_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM_6 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_PER_VC 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_PER_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_PER_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_MODE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG_SKIP_CNT_MODE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1 0x00900464 /* RW-4R */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH 25:20 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_ACTARB_FIFO_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG1_ACTARB_FIFO_DELAY_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2 0x00900468 /* RW-4R */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT 20:12 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE 25:21 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE 30:26 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG3 0x009004C8 /* RW-4R */ #define NV_PFB_FBPA_0_ACT_ARB_CFG3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACT_ARB_CFG3_IC_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG3_IC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG3_IC_MODE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4 0x009004D0 /* RW-4R */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH 0x009004D4 /* RW-4R */ #define NV_PFB_FBPA_0_FIFO_DEPTH__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR5 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR5 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MIN 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_MIN_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW 0x009004D8 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_ACPD_ASR 0x00900458 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_ACPD_ASR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR 0x009004DC /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0 0x009004F0 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1 0x009004F4 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2 0x009004F8 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR 0x009004FC /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_WR 0x009004E0 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_WR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_WR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_WR_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_VC0 0x009004E4 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_VC0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_VC0_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_VC0_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1 0x009004E8 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_UTIL_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_ECC 0x0090045C /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_ECC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_ECC_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_VC1_ECC_UTIL_INIT 0x00000555 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_VC2 0x009004EC /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_VC2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_VC2_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_VC2_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_ACPD 0x009004B0 /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_ACPD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_ACPD_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_ACPD_UTIL_INIT 0x000000CC /* RWI-V */ #define NV_PFB_FBPA_0_BW_TRACKER_ASR 0x0090044C /* RW-4R */ #define NV_PFB_FBPA_0_BW_TRACKER_ASR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BW_TRACKER_ASR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_BW_TRACKER_ASR_UTIL_INIT 0x00000199 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL 0x00900470 /* RW-4R */ #define NV_PFB_FBPA_0_ECC_CONTROL__PRIV_LEVEL_MASK 0x00900170 /* */ #define NV_PFB_FBPA_0_ECC_CONTROL_MASTER_EN 0:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_MASTER_EN_ENABLED 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_CONTROL_MASTER_EN_DISABLED 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_INCLUDE_ADDR 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_INCLUDE_ADDR_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_INCLUDE_ADDR_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL 4:3 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL_OFF 0x0 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_WRITE_KILL_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_EN 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_SIDEBAND_EN 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_SIDEBAND_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_SIDEBAND_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR_MODE 8:7 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_OFF 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0 17:9 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR0_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1 28:20 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_WRITE_KILL_PTR1_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL 0x00900474 /* RW-4R */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_SEC_INTR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_SEC_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_SEC_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_DED_INTR_EN 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_DED_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_DED_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_POISON_INTR_EN 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_POISON_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_POISON_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_ADDRERR_INTR_EN 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_ADDRERR_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_0_ECC_INTR_CTRL_ADDRERR_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_STATUS(i) (0x00900478+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ECC_STATUS__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_INTR 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_INTR 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_POISON_INTR 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_POISON_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_POISON_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_POISON_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_INTR 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_COUNTER_OVERFLOW 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_COUNTER_OVERFLOW 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_DED_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_0_ECC_SEC_COUNT(i) (0x00900480+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ECC_SEC_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_SEC_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_SEC_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_DED_COUNT(i) (0x00900488+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ECC_DED_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_DED_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_DED_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_DIAG(i) (0x00900490+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_0_ECC_DIAG__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_DIAG_TYPE 1:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_DIAG_TYPE_SEC 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_DIAG_TYPE_DED 0x1 /* R---V */ #define NV_PFB_FBPA_0_ECC_DIAG_TYPE_POISON 0x2 /* R---V */ #define NV_PFB_FBPA_0_ECC_DIAG_DED 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_DIAG_DED_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_DIAG_SEC 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_DIAG_SEC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_DIAG_POISON 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_DIAG_POISON_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_DIAG_SECBIT 16:8 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_DIAG_SECBIT_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR(i) (0x00900498+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR__PRIV_LEVEL_MASK 0x00900170 /* */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_COL 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_COL_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_PC 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_PC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_ROW 26:10 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_ROW_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_BANK 30:27 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_BANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXTBANK 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXTBANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXT(i) (0x009024B8+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXT__PRIV_LEVEL_MASK 0x00900170 /* */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXT_SID 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ERR_INJECTION_ADDR_EXT_SID_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_ECC_ADDR(i) (0x009004A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT(i) (0x009004A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2(i) (0x00902498+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_DED(i) (0x00902448+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_DED_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED(i) (0x00902450+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_DED_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_DED(i) (0x009024A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_DED_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_DED_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC(i) (0x00902458+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_SEC_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC(i) (0x00902460+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_SEC_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SEC(i) (0x009024A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SEC_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_SEC_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON(i) (0x00902468+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_POISON_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON(i) (0x00902470+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_POISON_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_POISON(i) (0x009024B0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_POISON_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT2_POISON_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR(i) (0x00902480+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_ADDRERR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR(i) (0x00902488+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_SID 22:20 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_0_ECC_ADDR_EXT_ADDRERR_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_0_ECC_ADDRERR_COUNT(i) (0x00902490+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_ECC_ADDRERR_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_ECC_ADDRERR_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_ECC_ADDRERR_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_0_BANK_SWIZZLE 0x009004B4 /* RW-4R */ #define NV_PFB_FBPA_0_BANK_SWIZZLE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_OVERRIDE 4+4:4 /* RWIVF */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_OVERRIDE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BANK_SWIZZLE_OVERRIDE_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION 0x009004B8 /* RW-4R */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR 10:2 /* RWIVF */ #define NV_PFB_FBPA_0_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER 0x009004C0 /* RW-4R */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_READS 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_READS_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_READS_24 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_READS_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_RW 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_RW_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_RW_28 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_LTC_BANDWIDTH_LIMITER_RW_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO 0x009004C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_INIT 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_INIT_VAL 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET 4:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET 13:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET 16:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET 19:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET 28:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_READSCHEDULE_FIFO 0x009004CC /* RW-4R */ #define NV_PFB_FBPA_0_READSCHEDULE_FIFO__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_READSCHEDULE_FIFO_DEPTH_LIMIT 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_READSCHEDULE_FIFO_DEPTH_LIMIT_FULL 0x000001FF /* RWI-V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL 0x00900500 /* RW-4R */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE 5:0 /* RWIUF */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_MRS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_REFRESH 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_SELFREFRESH_ENTRY 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_POWERSTATE_EXIT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_POWERDOWN_ENTRY 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_PRECHARGE 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_PRECHARGE_ALL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_ACTIVATE 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_WRITE 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_WRITE_AUTOPRE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_WRITE_ANY 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_READ 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_READ_AUTOPRE 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_READ_ANY 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_CACHE_MGMT_OP_PENDING 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_LDFF 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_RDTR 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_WRTR 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_ZQCL 0x00000013 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_ZQCS 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_REPLAY 0x00000015 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_REPLAY_START 0x00000016 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_READ_TRAINING 0x00000017 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_WRITE_TRAINING 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_MRR 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_MPC 0x0000001A /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_REFSB 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_STEP 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_SEQUENCE 0x00000021 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_ADR 0x00000022 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_WCK 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_RD 0x00000024 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_WR 0x00000025 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_QUSE 0x00000026 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_MODE 0x00000027 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_TRAINING_PERIODIC 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_CHAR_WRITE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_CHAR_READ 0x00000017 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_CHAR_ERROR 0x0000002C /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_CHAR_ERROR_ANY 0x0000002D /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_MASKED_PW 0x0000002F /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_PAIRED_RW 0x00000030 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH0 0x00000032 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH0_SW 0x00000032 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH1_SW 0x00000031 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_EDC_RD_ERR 0x00000033 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_EDC_WR_ERR 0x00000034 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_STATE_DQR 0x00000035 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_BASE_DELAY 12:8 /* RWIUF */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_BASE_DELAY_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_BASE_DELAY_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_LENGTH 23:20 /* RWIUF */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_LENGTH_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_LENGTH_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_INV 28:28 /* RWIUF */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_INV_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_INV_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_EN 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRIGGER_CNTRL_TRIGGER_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAP0 0x0090050C /* R--4R */ #define NV_PFB_FBPA_0_CAP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CAP0_FABRIC_PRESENT 0:0 /* R-IVF */ #define NV_PFB_FBPA_0_CAP0_FABRIC_PRESENT_YES 0x00000001 /* R-I-V */ #define NV_PFB_FBPA_0_CAP0_FABRIC_PRESENT_NO 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_CAP0_ECC_PRESENT 4:4 /* R-IVF */ #define NV_PFB_FBPA_0_CAP0_ECC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CAP0_ECC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CAP0_EDC_PRESENT 8:8 /* R-IVF */ #define NV_PFB_FBPA_0_CAP0_EDC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CAP0_EDC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CAP0_REPLAY_PRESENT 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_CAP0_REPLAY_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CAP0_REPLAY_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_PARITY 0x00900510 /* RW-4R */ #define NV_PFB_FBPA_0_PARITY__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_DATALO 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_DATALO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_DATAHI 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_DATAHI_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_CMD 8:8 /* R-IVF */ #define NV_PFB_FBPA_0_PARITY_IB_FABRIC_ERROR_CMD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_PARITY_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_PARITY_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_PARITY_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00900554 /* RW-4R */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT0 0x00900514 /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT0__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT0_INTERCEPT 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT0_INTERCEPT_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT0_1 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT0_1_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT0_2 29:20 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT0_2_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT1 0x00900518 /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT1__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT1_3 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT1_3_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT1_4 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT1_4_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT1_5 29:20 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT1_5_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT2 0x0090051C /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT2__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT2_6 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT2_6_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT2_7 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT2_7_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT2_8 29:20 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT2_8_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT3 0x00900520 /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT3__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT3_9 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT3_9_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT3_10 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT3_10_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT3_11 29:20 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT3_11_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT4 0x00900524 /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT4__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT4_12 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT4_12_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT4_13 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT4_13_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT4_14 29:20 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT4_14_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT5 0x00900528 /* RW-4R */ #define NV_PFB_FBPA_0_BA_WT5__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_WT5_15 9:0 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT5_15_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA_WT5_16 19:10 /* RWBVF */ #define NV_PFB_FBPA_0_BA_WT5_16_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_BA 0x00900550 /* RW-4R */ #define NV_PFB_FBPA_0_BA__PRIV_LEVEL_MASK 0x00900554 /* */ #define NV_PFB_FBPA_0_BA_BLKACTIVITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_BA_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_BA_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_BA_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_RD 0x00900558 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_RD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_RD_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_RD_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_RD_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_RD_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_RD_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC_WR 0x0090055C /* RW-4R */ #define NV_PFB_FBPA_0_CRC_WR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_WR_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_WR_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_WR_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_WR_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_WR_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC_TRIGGER 0x00900560 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_TRIGGER__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_TRIGGER_STATUS 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_TRIGGER_STATUS_NO_ERROR 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_TRIGGER_STATUS_ERROR 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_NUM 6:4 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_NUM_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_TRIGGER_MODE_CONTINUOUS 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_MODE_ONCE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_MASK_SUBP0 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_MASK_SUBP0_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_MASK_SUBP1 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_TRIGGER_BYTE_MASK_SUBP1_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DATA0 0x00900564 /* R--4R */ #define NV_PFB_FBPA_0_CRC_DATA0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_DATA0_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_DATA0_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DATA1 0x00900568 /* R--4R */ #define NV_PFB_FBPA_0_CRC_DATA1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_DATA1_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_DATA1_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DATA2 0x0090056C /* R--4R */ #define NV_PFB_FBPA_0_CRC_DATA2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_DATA2_DATA 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_DATA2_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DATA2_EXPECTED_EDC 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_DATA2_EXPECTED_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DATA2_ACTUAL_EDC 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_DATA2_ACTUAL_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE 0x00900570 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_LIMIT 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_LIMIT_1000 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_EXCEEDED 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_EXCEEDED_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_EXCEEDED_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_EXCEEDED_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_TICK_CLOCK 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_TICK_CLOCK_LTCCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_ERROR_RATE_TICK_CLOCK_MEMREF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC_TICK 0x00900574 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_TICK__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_TICK_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_TICK_VALUE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC_TICK_VALUE_1US 0x000002EE /* RWI-V */ #define NV_PFB_FBPA_0_CRC_ERROR_MAX_DELTA 0x00900578 /* R--4R */ #define NV_PFB_FBPA_0_CRC_ERROR_MAX_DELTA__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_MAX_DELTA_VALUE 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_ERROR_MAX_DELTA_VALUE_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0 0x009000D0 /* RW-4R */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1 0x009000D4 /* RW-4R */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0 0x009000D8 /* RW-4R */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1 0x009000DC /* RW-4R */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC 0x00900580 /* RW-4R */ #define NV_PFB_FBPA_0_CRC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_0_CRC_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CRC_ERROR_DURING_RETRY 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_DURING_RETRY_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_CRC_ERROR_DURING_RETRY_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_ERROR_DURING_RETRY_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_INTERRUPT 0x00900584 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_INTERRUPT__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_CNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_CNT_16384 0x00004000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_CNT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_CNT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_DELTA 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_DELTA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_MAX_DELTA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_ERR_ON_RETRY 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_ERR_ON_RETRY_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_CRC_INTERRUPT_EN_ERR_ON_RETRY_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_DEBUG 0x00900588 /* RW-4R */ #define NV_PFB_FBPA_0_CRC_DEBUG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_ERR 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_ERR 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_RPL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_RPL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP0_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_ERR 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_ERR 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_RPL 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_RPL 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_CRC_DEBUG_SUBP1_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_RD_BYTE(i) (0x00902400+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_RD_BYTE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_RD_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_RD_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_WR_BYTE(i) (0x00902420+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_WR_BYTE__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_WR_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_CRC_ERROR_COUNT_WR_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_DEBUG 0x00902440 /* RWI4R */ #define NV_PFB_FBPA_0_REPLAY_DEBUG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_MAXRETRY 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_MAXRETRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_SUBP0_SKIPCNT 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_SUBP0_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_SUBP1_SKIPCNT 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_REPLAY_DEBUG_SUBP1_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR(i) (0x009024D4+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_RR_FIFOERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_RR_FIFOERR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_1ST 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_1ST 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_1ST 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_1ST 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_2ND 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_2ND 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_2ND 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_2ND 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_RDAT3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_1ST 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_1ST 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_1ST 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_1ST 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_2ND 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_2ND 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_2ND 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_2ND 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_RR_FIFOERR_EDC3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_REFCTRL3 0x009024DC /* RW-4R */ #define NV_PFB_FBPA_0_REFCTRL3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR_SRC 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR_SRC_DRAMC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL3_PBR2ABR_SRC_PWRM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_THRESHOLD 20:17 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_THRESHOLD_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_SPEEDUP 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_SPEEDUP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFCTRL3_SOFTKILLPBR_SPEEDUP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_ISO_LATENCY 0x0090058C /* RW-4R */ #define NV_PFB_FBPA_0_ISO_LATENCY__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_ISO_LATENCY_MAX 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_ISO_LATENCY_MAX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_ISO_LATENCY_LAST 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_ISO_LATENCY_LAST_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_INTR_STATUS 0x00900398 /* R--4R */ #define NV_PFB_FBPA_0_INTR_STATUS__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP0 0:0 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP0 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP0 2:2 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP0 3:3 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP0 4:4 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP0 8:8 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP1 16:16 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_SEC_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP1 17:17 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_DED_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_OOR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_POISON_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP1 20:20 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_ADDRERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP1 24:24 /* R-IVF */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_INTR_STATUS_AERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_OOR 0x009003A8 /* RW-4R */ #define NV_PFB_FBPA_0_OOR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_OOR_COUNT_SUBP0 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_OOR_COUNT_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP0 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP0_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_OOR_COUNT_SUBP1 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_OOR_COUNT_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP1 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_OOR_RESET_COUNT_SUBP1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP0 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP1 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_OOR_INTR_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_0_OOR_INTR_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_OOR_INTR_ENABLE_OFF 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_OOR_INTR_ENABLE_ON 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_HBM_CFG0 0x0090038C /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CFG0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK_BANK 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK_BANK_8 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CFG0_DUAL_RANK_BANK_16 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_SCHED_PC_LIMIT 9:2 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_SCHED_PC_LIMIT_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CFG0_SCHED_PC_LIMIT_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_OVR 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_VAL 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID1_VAL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CFG0_SID1_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CFG0_SID1_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG 0x009003A0 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_ARB_CFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_SECCNT_ARB 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_SECCNT_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_SECCNT_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_MIN_BG_SECTORS 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_MIN_BG_SECTORS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_RESIDUAL_THRESHOLD 8:5 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG_RESIDUAL_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1 0x009003A4 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_RD_RANK_DURATION 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_RD_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_RD_RANK_MIN_STAY 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_RD_RANK_MIN_STAY_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_WR_RANK_DURATION 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_ARB_CFG1_WR_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR 0x009003AC /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_DQ(i) (0x00000000 + (i)) /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_DQ__SIZE_1 128 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_ECC(i) (0x00000090 + (i)) /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_ECC__SIZE_1 16 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_DBI(i) (0x00000080 + (i)) /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PIN_DBI__SIZE_1 16 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_PC 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_PC_PC0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CHAR_PC_PC1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CHAR_PC_PC01 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_DBI 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_DBI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CHAR_ECC 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x009003B0 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x009003B4 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x009003B8 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x009003BC /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x009003C0 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x009003C4 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x009003C8 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x009003CC /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI 0x009003D0 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC 0x009003D4 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MAX 0x009003D8 /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MAX__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MAX_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_MAX_V_INIT 0xFFFFFFFF /* RWI-V */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_THRESHOLD 0x009003DC /* RW-4R */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_THRESHOLD__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_THRESHOLD_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_HBM_CHAR_COUNTER_THRESHOLD_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_RR_CTRL 0x009003FC /* RW-4R */ #define NV_PFB_FBPA_0_RR_CTRL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_RR_CTRL_PC_NPC_GAP 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_RR_CTRL_PC_NPC_GAP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_RR_CTRL_RW_GAP 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_RR_CTRL_RW_GAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK 0x009008FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST 0x00900590 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BROADCAST__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_SDDR23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_DDR3 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MODE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MODE_LATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MODE_EARLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_EYE_MASK 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_EYE_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_EYE_MASK_LOWER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_EYE_MASK_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_EYE_MASK_UPPER 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GENERIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GENERIC2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_BGA136 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_SDDR3_BGA100 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_GT215_COMP 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR1 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_X8 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR_X8 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_SDDR4_BGA78 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_HBM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_SDDR4_3DS 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_USE_EXTENDED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_MODE 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_SUBP 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_GEARDOWN 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_GEARDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_2T_CMD_GEARDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_G5X_CMD_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_G5X_CMD_MODE_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_G5X_CMD_MODE_G5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_MODE 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL 22:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_LOW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_OB_FABRIC_DBI 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_OB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_OB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_IB_FABRIC_DBI 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_IB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_IB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT 29:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_LPDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_1 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_2 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_IC 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_4 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6X_BGA180_MODE_1 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_90D 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_270D 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI 0x00900594 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_ON 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_MODE_SSO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_OUT_MODE_LP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_IN_ON 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_IN_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG_DBI_IN_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CHANNELCFG 0x00900598 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CHANNELCFG__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO_CHANNELCFG_CHANNEL_ENABLE 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CHANNELCFG_CHANNEL_ENABLE_32_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CHANNELCFG_CHANNEL_ENABLE_64_BIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1 0x0090059C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_INTERP 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_INTERP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_INTERP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RCVR 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RCVR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RCVR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RX_CLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RX_CLK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BROADCAST1_POWER_EN_RX_CLK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5 0x00900604 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CONFIG5__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_CMD_PAD_DISABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_CMD_PAD_DISABLE_NOT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_CMD_PAD_DISABLE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V1P2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V1P8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V2P1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_VDDP_MODE_V2P4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_ATDAT_FORCE 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_ATDAT_FORCE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_ATDAT_FORCE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_PU40_MODE_CMD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_PU40_MODE_CMD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CONFIG5_PU40_MODE_CMD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SPARE 0x0090060C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE__PROD_C_DDR1 0x00300000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE__PROD_C_DDR2 0x00300000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE__PROD_C_DDR3 0x00300001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE__PROD_C_DDR4 0x80300001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE__PROD_C_DDR5 0x80300001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_DELAYED_CALDRV_SDDR 1:1 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE 4:4 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_FORCE_MA_SDR 7:7 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_FORCE_MA_SDR_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_FORCE_MA_SDR_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_PAD_CALIBRATION 11:11 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_PAD_CALIBRATION_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_PAD_CALIBRATION_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_SERIALIZER 12:12 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_SERIALIZER_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_SERIALIZER_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_EN 25:25 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_EN_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_EN_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB 26:26 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV 27:27 /* */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_0_FBIO_SPARE_VALUE_CLK_OBS_CLK_SEL 29:28 /* */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN 0x00900610 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN 0x00900614 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR 0x0090061C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_ASR__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_ASR_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR_VAUXC 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR_VCLAMP 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VAUXP 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VAUXC 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VCLAMP 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ASR_BRICK_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL 0x00900670 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_FILTER_BITS 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_FILTER_BITS_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_START_TRM 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_START_TRM_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_END_COUNT 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_END_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_LEGACY_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_LEGACY_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_IGNORE_START 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_CALIBRATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS 0x00900674 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS 0x00900678 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL 0x0090067C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DLCELL 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DLCELL 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_MDDLL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_WDQS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL 0x00900694 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP0_ADR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP0_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP1_ADR0 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP1_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL 0x00900698 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL 0x0090069C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL 0x009006A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL 0x009006A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL 0x009006A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL 0x009006AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL 0x009006B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL 0x009006B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL 0x009006B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL 0x009006BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1 0x00900ED8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1 0x00900EDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE 0x00900700 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_BYTE_VREF_MODE_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL 0x00900704 /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_IB 7:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_IB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_OB 15:8 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_OB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_DQDQS 23:16 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_DQDQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_QUSE 31:24 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_DDLL_QUSE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC 0x00900708 /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_MODE 1:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE 3:2 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_DAT 6:4 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_DAT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_DQS 10:8 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_VREF_DQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT 20:16 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1 0x0090070C /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE 31:24 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x00900710 /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x00900714 /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3 0x00900718 /* -W-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE 2:0 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE 5:3 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE 8:6 /* -WIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK 0x00900650 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CML_CLK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_PREDI 14:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_PREDI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK0_ON 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK0_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK0_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK1_ON 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK1_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK1_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK_RUN 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_CLK_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_POLARITY 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_POLARITY_NORMAL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK_POLARITY_INVERT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DELAY 0x0090065C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DELAY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DELAY_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DELAY_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DELAY_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DELAY_PRIV_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY 0x009008E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DELAY_CMD_PRIV_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER 0x009008E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER_PATTERN 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER_PATTERN_INIT 0x33330F0F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_QDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_DDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6x 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK 0x0090066C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CML_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_TX_DRVDN 19:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_TX_DRVUP 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_E_PU40 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_E_PU40_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_E_PU40_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_FREEZE 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL 0x00900504 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_FBIO_CAL_CFG_DRVDLY 31:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_CFG_DRVDLY_A 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB 0x00900508 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB__PRIV_LEVEL_MASK 0x00900168 /* */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_1CYCLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_2CYCLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_3CYCLE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_4CYCLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_SEL_TRNG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_SEL_CAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_TRNG_ARB_SKIP_CNT_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR 0x00900720 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVR_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF 0x00900724 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVF_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT 0x00900728 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_DRVT_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR 0x00900730 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_SLWR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS 0x00900738 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVR 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVF 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVF_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVF_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVF_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_BYP_CS_DRVF_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0 0x009007D0 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD0_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD0_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD0_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD1 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD1_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD1_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD1_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD2 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD2_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD2_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD2_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD3 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD3_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD3_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD3_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD4 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD4_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD4_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD4_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD5 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD5_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD5_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD5_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD6 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD6_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD6_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD6_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD7 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD7_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD7_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD7_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD8 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD8_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD8_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD8_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD9 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD9_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD9_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD9_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD10 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD10_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD10_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD10_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD11 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD11_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD11_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD11_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD12 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD12_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD12_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD12_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD13 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD13_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD13_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD13_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD14 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD14_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD14_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD14_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD15 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD15_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD15_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL0_CMD15_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1 0x009007D4 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD16 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD16_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD16_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD16_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD17 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD17_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD17_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD17_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD18 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD18_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD18_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD18_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD19 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD19_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD19_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD19_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD20 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD20_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD20_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD20_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD21 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD21_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD21_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD21_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD22 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD22_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD22_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD22_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD23 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD23_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD23_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD23_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD24 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD24_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD24_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD24_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD25 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD25_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD25_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD25_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD26 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD26_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD26_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD26_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD27 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD27_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD27_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD27_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD28 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD28_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD28_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD28_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD29 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD29_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD29_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD29_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD30 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD30_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD30_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD30_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD31 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD31_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD31_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL1_CMD31_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2 0x009007D8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD32 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD32_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD32_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD32_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD33 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD33_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD33_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD33_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD34 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD34_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD34_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD34_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD35 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD35_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD35_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD35_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD36 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD36_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD36_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD36_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD37 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD37_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD37_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD37_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD38 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD38_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD38_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD38_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD39 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD39_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD39_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD39_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD40 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD40_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD40_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD40_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD41 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD41_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD41_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD41_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD42 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD42_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD42_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD42_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD43 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD43_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD43_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD43_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD44 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD44_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD44_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD44_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD45 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD45_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD45_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD45_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD46 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD46_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD46_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD46_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD47 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD47_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD47_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL2_CMD47_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3 0x009007E8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD48 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD48_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD48_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD48_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD49 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD49_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD49_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD49_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD50 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD50_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD50_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD50_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD51 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD51_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD51_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD51_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD52 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD52_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD52_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD52_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD53 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD53_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD53_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD53_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD54 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD54_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD54_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD54_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD55 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD55_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD55_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_CAL_ADR_DRV_SEL3_CMD55_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CALCFG 0x009007E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CALCFG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CMD_STEP 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CMD_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CMD_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CK_STEP 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_CK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_WCK_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CALCFG_WCK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_WCK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CALCFG_BGCAL_FREEZE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CALCFG_BGCAL_FREEZE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x00901EC8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x00901ECC /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x00901ED0 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x00901ED4 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x00901ED8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x00901EDC /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x00901EE0 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x00901EE4 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x00901EE8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x00901EEC /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x00901EF0 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x00901EF4 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x00901EF8 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x00901EFC /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x00901F00 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x00901F04 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x00901F08 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x00901F0C /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x00901F10 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x00901F14 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x00901F18 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x00901F1C /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x00901F20 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x00901F24 /* RW-4R */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK 0x00901F28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DRVDN_BYP_SEL_INI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML 0x00901F34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_CLK_VML_SEL_VML 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK 0x00901F2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML 0x00901F38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_SEL_CML 0x0 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CAL_WCK_VML_SEL_VML 0x1 /* RWI-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG 0x00900000 /* RWE4R */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT__PROD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_0_PRI_FBPA_CG1 0x00900004 /* RWE4R */ #define NV_PFB_FBPA_0_PRI_FBPA_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_FBPA_0_PRI_FBPA_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_0_PRI_FBPA_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8 0x00900800 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG8__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU__PROD_C_DDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_ENABLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT 2:2 /* */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_CFG8_RFU_RDQS_RCVR_SEL_XOR 5:4 /* */ #define NV_PFB_FBPA_0_FBIO_CFG10 0x00900808 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG10__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_DQ 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_RDQS 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_RDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_RDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_WDQS 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_CMD 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPD_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_DQ 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_RDQS 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_RDQS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_RDQS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_WDQS 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WKPU_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_DQ_TERM_MODE 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_DQ_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_DQ_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_DQ_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_DQ_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_TERM_MODE 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WDQS_TERM_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_WDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_WDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_RDQS_DIFF_MODE 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_RDQS_DIFF_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_RDQS_DIFF_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_SRC_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_SRC_SEL_RDQS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG10_RDQS_SRC_SEL_WDQS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_INTERNAL_VREF 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_INTERNAL_VREF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG10_E_INTERNAL_VREF_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BRLSHFT 0x00900820 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BRLSHFT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BRLSHFT_CMD 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BRLSHFT_CMD_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD 0x00900824 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD__PRIV_LEVEL_MASK 0x0090086C /* */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CML_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CML_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CML_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_PWRD 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_TX_PWRD 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_ON 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CLK_TX_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CLK_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CLK_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCK_TX_PWRD 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCK_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCKB_TX_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCKB_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DIFFAMP_PWRD 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DIFFAMP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DIFFAMP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11 0x00900828 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG11__PRIV_LEVEL_MASK 0x0090086C /* */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_S_MACRO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_D_MACRO 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_S_PAD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_D_PAD 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11_LOOPBK_MODE_I_PAD 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG11_CK_DEEPLOOP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_CK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_E_LPBK_INTERFACE_MODE 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_E_LPBK_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_E_LP_MODE_CMD 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_E_LP_MODE_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_WCK_DEEPLOOP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_WCK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_VEND_ID_C0_LOAD_EN 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_VEND_ID_C0_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_VEND_ID_C1_LOAD_EN 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_VEND_ID_C1_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_PARALLEL_LPBK_MODE_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_PARALLEL_LPBK_MODE_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_CLAMP_VAL 23:23 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_CLAMP_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CFG11_CONFIG_CMD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG11_CONFIG_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12 0x0090082C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG12__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG12_PVT_CODE_BYTE_C0_RB 10:8 /* R--VF */ #define NV_PFB_FBPA_0_FBIO_CFG12_PVT_CODE_BYTE_C1_RB 13:11 /* R--VF */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_INTRP_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_INTRP_8UI_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_INTRP_8UI_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP16 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CYA_SELECT_NO_STEP 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_TX_EN_EARLY 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_TX_EN_EARLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_TAPERED_START 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_TAPERED_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_WCK_TAPERED_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CAP 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_INTERP_CAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_CMD_BR8_DELAY 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG12_CMD_BR8_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG12_CMD_BR8_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG12_CMD_BR8_DELAY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1 0x00900830 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_FBIO_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPRE_TWO 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPRE_TWO_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPRE_TWO_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPOST 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPREPOST_DQ_VALUE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPREPOST_DQ_VALUE_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WPREPOST_DQ_VALUE_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WDQS_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_WDQS_MODE_WDQS_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_WDQS_MODE_WDQS_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_HOLD_DQ 10:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_HOLD_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_SETUP_DQ 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_SETUP_DQ_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_SETUP_STR 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_EN_SETUP_STR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_CMD_BRLSHFT 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_CMD_BRLSHFT_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_CMD_BRLSHFT_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_ON 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_SHORT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_NORMAL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_LONG 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_QUSE_FORCE_HIGH 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_QUSE_FORCE_HIGH_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_QUSE_FORCE_HIGH_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_BIT2 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_EXTENDED_QUSE_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_PADMACRO_SYNC 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_PADMACRO_SYNC_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_PADMACRO_SYNC_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_RCV_CLOCKING 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_RCV_CLOCKING_STROBE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_RCV_CLOCKING_CONTINUOUS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_CLK_ASSERT 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_CLK_ASSERT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_TX_CLK_ASSERT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RUN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RESET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_PADMACRO_RESET 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_PADMACRO_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_INTERP_RESET 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_INTERP_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG1_DDLL_INIT 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG1_DDLL_INIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CFG1_DDLL_INIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SPARE2 0x00900834 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SPARE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SPARE2_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SPARE2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C0 0x00900838 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C0_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C0_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C1 0x0090083C /* R--4R */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C1_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VEND_ID_C1_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK 0x00900860 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_DLY_CK0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_DLY_CK0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_DLY_CK1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_DLY_CK1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMOS_CLK_SEL_CMOS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK 0x00900864 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK 0x00900868 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL 0x00900870 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_RCV_CTRL_LANE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG7 0x00900874 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG7__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG7_CMD_RCV_CTRL 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG7_CMD_RCV_CTRL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG7_CMD_OB_SYNC_DLY 30:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG7_CMD_OB_SYNC_DLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL 0x00900890 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL__PRIV_LEVEL_MASK 0x0090086C /* */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_OB_BYTE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_BYTE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_CMD 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WCK 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_TRAINING_PRIV 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_TRAINING_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_BLCG_BYTE 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF 21:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF 25:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL 0x00900894 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF 14:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_31 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF 19:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 29:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1 0x00900898 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CG 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_DQ_DISABLE_ASR 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_DQ_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_DISABLE_ASR 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_WCK_DISABLE_ASR 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_WCK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CK_DISABLE_ASR 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L 0x009008C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H 0x009008CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL 0x009008D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK0_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK0_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK0_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK0_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK1 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK1_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK1_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK1_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CLK_CTRL_CLK1_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM 0x009008D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM_BYTE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM_BYTE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM_CMD 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_LOOPBK_TRIM_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY 0x009008D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PARITY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE0 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE1 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE1 3:3 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE2 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE2 5:5 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE2_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE3 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE3 7:7 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE3_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE4 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE4 9:9 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE4_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE5 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE5 11:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE5_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE6 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE6 13:13 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE6_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE7 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ENABLE_LANE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE7 15:15 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_PARITY_ERROR_LANE7_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY 0x009008DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PARITY_ERR 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR 2:2 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PARITY_ERR 4:4 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR 5:5 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG 0x00900E00 /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_CFG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE_CML 8:8 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_ENABLE_CML_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_READY 16:16 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_LOCK 17:17 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSA 24:24 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSD 25:25 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_CML 26:26 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_CML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_4PHCML 27:27 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_4PHCML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_DLL 28:28 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_DLL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_600 29:29 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_600_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_600_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_PLL_600_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF 0x00900E04 /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_NDIV_INIT 0x00000014 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_NDIV_MIN 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_SEL_DIVBY2 28:28 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_SEL_DIVBY2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_SEL_DIVBY2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_COEFF_SEL_DIVBY2_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL 0x00900E08 /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_PLL_FREQLOCK 28:28 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_PLL_FREQLOCK_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_PLL_FREQLOCK_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_PLL_FREQLOCK_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_MON_TESTOUT 31:29 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_MON_TESTOUT_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_ENABLE_BG 22:22 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG2 0x00900E0C /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS 0x00900E14 /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_READY 0:0 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK 1:1 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK 2:2 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_READY 3:3 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK 4:4 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK 5:5 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_READY 6:6 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK 7:7 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK 8:8 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_READY 9:9 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK 10:10 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK 11:11 /* R-IUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_SETUP2 19:16 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_DUAL_STATUS_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3 0x00900E18 /* RW-4R */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DEBUG_DLL 7:0 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DEBUG_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_KCP_DLL 9:8 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_KCP_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DELAYGAIN 10:10 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DELAYGAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_BYPASS_ASYNC 12:12 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_BYPASS_ASYNC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DLL_ENABLE 14:14 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_DLL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_SEL_DLLCLK 15:15 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_SEL_DLLCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_TESTSEL 26:25 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_TESTSEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_SPEEDUP 28:28 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_SPEEDUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_TESTEN 29:29 /* RWIUF */ #define NV_PFB_FBPA_0_DRAMPLL_CFG3_TESTEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG 0x00900E20 /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_CFG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_SYNC_MODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENB_LCKDET_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_ENB_LCKDET_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_READY 16:16 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_LOCK 17:17 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSA 24:24 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSD 25:25 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_CML 26:26 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_4PHCML 27:27 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_DLL 28:28 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_PLL_600 29:29 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF 0x00900E24 /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_COEFF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_NDIV_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_NDIV_MIN 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL 0x00900E28 /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_MON_TESTOUT 31:29 /* R--UF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2 0x00900E2C /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SDM 8:8 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SSC 9:9 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SSC_BYP 10:10 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SSC_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SSC_BYP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SSC_BYP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER 11:11 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SDM_RESET 12:12 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER2 13:13 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER2_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SSD_EN_DITHER2_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_SSD0 0x00900E30 /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_SSD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_SSD0_SDM_SSC_STEP 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_SSD0_SDM_DIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_SSD0_SDM_DIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_SSD1 0x00900E34 /* RW-4R */ #define NV_PFB_FBPA_0_REFMPLL_SSD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_REFMPLL_SSD1_SDM_SSC_MAX 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_REFMPLL_SSD1_SDM_SSC_MIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_0_REFMPLL_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK 0x00902030 /* RW-4R */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x00902034 /* RW-4R */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_GSP_SEC2_IFF_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK 0x00902038 /* RW-4R */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_TRAINING_ADR(i) (0x00900900+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_ADR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_ADR__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_ADR_ROW 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADR_EXTBANK 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADR_EXTBANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADR_BANK 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD(i) (0x00900910+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_CMD__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_CMD__PRIV_LEVEL_MASK 0x00902038 /* */ #define NV_PFB_FBPA_0_TRAINING_CMD_ADR 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_WCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_WCK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_WCK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_RD 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_RD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_WR 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_WR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE_PRIME 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE_PRIME_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_QUSE_PRIME_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CHAR_ENGINE 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_CHAR_ENGINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CHAR_ENGINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_PERIODIC 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_RW_LEVEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_RW_LEVEL_BYTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_RW_LEVEL_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_STROBE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_STROBE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_STROBE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CONTROL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_CONTROL_TRIMMER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CONTROL_DLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CONTROL_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_CONTROL_DLCELL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CMD_STEP 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_STEP_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_TRAINING_CMD_GO 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CMD_GO_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_TRAINING_DP(i) (0x00900918+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_DP__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DP__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DP_LO 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DP_LO_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DP_HI 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DP_HI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD(i) (0x00900920+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_DBI 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_DBI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_EDC 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_EDC_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_SEL 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_SEL_RD 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_SEL_WR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_SEL_LEGACY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DP_CNTD_SEL_CHAR_ENGINE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL(i) (0x009009C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0(i) (0x00900938+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR4 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR4_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR5 23:20 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR5_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR6 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR6_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR7 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR7_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ0_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1(i) (0x00900940+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR8 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR8_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR9 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR9_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR10 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR10_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR11 15:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR11_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR12 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR12_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR13 23:20 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR13_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR14 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR14_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR15 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR15_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ1_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2(i) (0x00900948+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR16 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR16_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR17 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR17_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR18 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR18_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR19 15:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR19_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR20 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR20_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR21 23:20 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR21_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR22 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR22_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR23 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR23_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ2_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3(i) (0x00900950+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR24 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR24_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR25 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR25_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR26 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR26_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR27 15:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR27_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR28 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR28_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR29 23:20 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR29_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR30 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR30_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR31 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR31_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_DQ3_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0(i) (0x00900958+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_EDC_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR0 19:16 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR1 23:20 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR2 27:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR3 31:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC0_DBI_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1(i) (0x00900960+(i)*4) /* R--4A */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR0 9:8 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR0_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR1 11:10 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR1_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC0 13:12 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC0_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC0_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC0_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC1 15:14 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC1_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC1_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC1_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR2 25:24 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR2_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR3 27:26 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_ERR3_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC2 29:28 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC2_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC2_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC2_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC3 31:30 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC3_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC3_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_DEBUG_MISC1_WCK_EDC3_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR(i) (0x00900968+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ADR 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ADR_ACT_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ADR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_DP 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_DP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_DP_TRAIN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_DP_CHAR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ACT_ADR 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ACT_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATTERN_PTR_ACT_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TIMING 0x00900970 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_TIMING__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_TIMING_ADRTRM_SETTLE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING_ADRTRM_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING_ADRTRM_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TIMING_ADRTRM_FLUSH 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING_ADRTRM_FLUSH_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING_VREF_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING_VREF_SETTLE_INIT 0x0000006E /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING_INTRPLTR_SETTLE 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING_INTRPLTR_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING_INTRPLTR_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TIMING2 0x009009C8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_TIMING2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_TIMING2_PRIV_DELAY 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING2_PRIV_DELAY_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING2_APPLY_DELAY 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING2_APPLY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TIMING3 0x00902050 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_TIMING3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_TIMING3_TVREFD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TIMING3_TVREFD_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL 0x00902054 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_MIN_INIT 0x00000038 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_MAX_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_STATUS 0x00900974 /* R--4R */ #define NV_PFB_FBPA_0_TRAINING_STATUS__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP0_STATUS 1:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP0_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP0_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP0_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP0_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP1_STATUS 3:2 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP1_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP1_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP1_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_STATUS_SUBP1_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_0_TRAINING_CTRL 0x00900978 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FAST_UPDATES 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FAST_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FAST_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASR_FAST_EXIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASR_FAST_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASR_FAST_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_DELAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_DELAY_2UI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_DELAY_4UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASYNC_UPDATES 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASYNC_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_ASYNC_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DFE_OVERRIDE 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DFE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE_CLEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_EXTENDED_RW_OFFSET 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_EXTENDED_RW_OFFSET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_EXTENDED_RW_OFFSET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_G5X_EDC_TR_MODE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_G5X_EDC_TR_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_G5X_EDC_TR_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_VREF_TRAINING 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_VREF_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_VREF_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_TRAINING 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_TRIMMER_TRAINING 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_TRIMMER_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_TRIMMER_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_STOP_CLOCKS 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_STOP_CLOCKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_STOP_CLOCKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_EARLY_FLIP 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_EARLY_FLIP_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_EARLY_FLIP_DIABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_STALL_CMDQ 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_STALL_CMDQ_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_STALL_CMDQ_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_QUICK 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DOUBLE_CORS_RANGE 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DOUBLE_CORS_RANGE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_DOUBLE_CORS_RANGE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_RD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_WR 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_FIRST_PARTIAL_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_PADS 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_PADS_FOUR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_WCK_PADS_EIGHT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL 0x0090097C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_START_WAIT 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_START_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_START_EN_WAIT 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_START_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_START_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_FINISH_WAIT 26:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_FINISH_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_REFRESH 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_REFRESH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_REFRESH_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_WAIT_IDLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_WAIT_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_LEGACY_CTRL_WAIT_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2 0x00902040 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CTRL2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_SWEEP_PHASE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_SWEEP_PHASE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_SWEEP_PHASE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_USE_BL16 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_USE_BL16_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_USE_BL16_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_WR 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_SHIFT_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_WR 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_RD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_INV_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_RD 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_WR 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_PI_OFFSET_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_DCC 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_DCC_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_DCC_HOLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_DCC_TRACK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_QUICK_WCK 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_QUICK_WCK_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_QUICK_WCK_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_8UI_MODE_G6 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL2_WCK_8UI_MODE_G6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL 0x00902070 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_BS 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_BS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_BS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_CORS 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_CORS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALT_CORS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALF_FBPA 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALF_FBPA_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_HALF_FBPA_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_RX_CAPTURE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_RX_CAPTURE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_RX_CAPTURE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_BS_FOR_CA_TR 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_MISC_CTRL_BS_FOR_CA_TR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TAG 0x00900A00 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_TAG__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_TAG_TAG 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TAG_TAG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL_ALWAYS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_BYTE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_DOUBLE_BYTE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_DRAM 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TAG_FIRST_TAG 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TAG_FIRST_TAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TAG_FIRST_TAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_TAG_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_TAG_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_TAG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM 0x00900A04 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_PATRAM__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_CHAR_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_CHAR_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_CHAR_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_CHAR_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_CHAR_MAX_MAX 0x0000005F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_BURST_CNT 22:15 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_BURST_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_INV_EN 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_INV_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_INV_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_PATTERN_LEN 26:25 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS7 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS11 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS23 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_DUAL_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_DUAL_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_DUAL_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_ACCESS_UPPER32 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_ACCESS_UPPER32_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_ACCESS_UPPER32_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_USE_RESET_LAST 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_USE_RESET_LAST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_USE_RESET_LAST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_OVERRIDE_TRAINING 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_OVERRIDE_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_OVERRIDE_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT 0x00900AE0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_RD 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_WR 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_PERIODIC_RD 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_PERIODIC_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_PERIODIC_WR 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT_PERIODIC_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2 0x00900AE4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2_ADDR_START 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2_ADDR_START_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2_ADDR_END 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_SELECT2_ADDR_END_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER 0x00900A08 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MAX 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_THRESHOLD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x00900AC0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x00900AC8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x00900AD0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL 0x00900A0C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_MODE_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_MODE_SWEEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_SWEEP_START 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_SWEEP_START_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_SWEEP_START_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_START_COUNT 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_START_COUNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_START_COUNT_ACCUMULATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_REFRESH 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_AFTER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_ALWAYS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_NUM_BANKS 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_NUM_BANKS_1 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_NUM_BANKS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_FUNC_MTA 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_FUNC_MTA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_FUNC_MTA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_DBI_THRESHOLD 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_DBI_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_PATTERN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_DATA 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ(i) (0x00000001 + (i)) /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ__SIZE_1 31 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI0 0x00000020 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI1 0x00000021 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI2 0x00000022 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC0 0x00000024 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC3 0x00000027 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC0 0x00000028 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC1 0x00000029 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC2 0x0000002A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC3 0x0000002B /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_ALL 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST 0x00900A10 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST_COUNT_1BANK_LIMIT 0x00000100 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST_COUNT_2BANK_LIMIT 0x00000200 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BURST_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_TURN 0x00900A14 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_TURN__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_TURN_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_TURN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_TURN_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL 0x00900A18 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_MIN 11:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_MAX 23:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_INTRPLTR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_DDLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_TRIMMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_INTRPLTR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_TRIMMER 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_DDLL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_TRIMMER 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_DDLL 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_INTRPLTR 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL 0x00900AD8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_MIN 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_MAX 9:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_MAX_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_MIN 14:11 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_MIN_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_MAX 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_MAX_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_PREA 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_PREA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_PREA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_RANK 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_A_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_RANK 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_SET_B_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_REFA 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_REFA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL_REFA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2 0x00900ADC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_FOREVER 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL 0x009009CC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ADR_SETTING 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ADR_SETTING_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ADR_MAX 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ADR_MAX_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ENABLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_TADR_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL 0x009009D0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL 0x009009D4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_MIN_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL 0x00900984 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_X8_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_X8_MODE_BOTH 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_X8_MODE_RISING_ONLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_X8_MODE_FALLING_ONLY 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_MIRROR 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_MIRROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_MIRROR_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_MIRROR_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_MIRROR_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_REFRESH 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_REF_CNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_REF_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_1TCK 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_3TCK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_5TCK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_31TCK 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_SKIP_CNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL 0x00900988 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x009009D8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX_INIT 0x000000F0 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL 0x009009DC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_DDLL_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_TRIMMER_CTRL 0x009009E0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_TRIMMER_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_TRIMMER_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x0090098C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER 23:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x00900A1C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP 29:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_OPTIMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT 0x00900990 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL 0x009009F4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL 0x009009F8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_MIN_INIT 0x000000D8 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL 0x009009FC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_BURST_COUNT 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_QUSE_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL 0x00900AE8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_RPT_MODE 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_RPT_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL_RPT_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2 0x00900AEC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_BURST_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3 0x00900AFC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR 0x00900AF4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_MODE 2:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_MODE_SERIAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_MODE_PARALLEL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_MODE_STAGGER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PATTERN 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PATTERN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PATTERN_CUSTOM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DRAM_DEVICE 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X16 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X32 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PAGE_SELECT 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_0 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_1 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_2 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_3 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_RPT_ORDER 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_RPT_ORDER_MPR_RPT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_RPT_ORDER_RPT_MPR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA 0x00900AF8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR0_DEFAULT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR1_DEFAULT 0x00000033 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR2_DEFAULT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_CTRL_MPR_DATA_MPR3_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL 0x00900994 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL_CMD_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR5_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_DDR3_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR6X_MAX 0x0000000f /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL 0x00900998 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_MAX_INIT 0x00000035 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_STEP_LN 26:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x009009E4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD_INIT 0x00000013 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR_INIT 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL 0x0090099C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL 0x009009A0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL 0x009009E8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL 0x009009EC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL 0x009009A4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL 0x009009A8 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_AREA_BASED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_AREA_BASED_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_QUICK 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_VREF_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT 0x009009AC /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_TRIMMER 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_TRIMMER_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_ERR_LIMIT_TRIMMER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL 0x009009B0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_EN_AVG 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL_EN_AVG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL 0x009009F0 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2 0x009009B4 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3 0x00902048 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL 0x0090204C /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME 29:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL 0x00902044 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_AREA_BASED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x00900A20+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x00900A28+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x00900A30+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x00900A38+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x00900A40+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x00900A48+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x00900A50+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x00900A58+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x00900A60+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x00900A68+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x00900A70+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x00900A78+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x00900A80+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x00900A88+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC(i) (0x00900A90+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_IB_MISC_EDC3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x00900A98+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x00900AA0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x00900AA8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x00900AB0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC(i) (0x00900AB8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_RW_OFFSET_OB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_SEED(i) (0x00902000+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_SEED__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_SEED_VAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PATRAM_PRBS_SEED_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL 0x00902060 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_ADDR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_ABI 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_WCK 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_FULL_PERIODIC 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_PHASE 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_PHASE_FINE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_PHASE_CORS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_CTRL_PHASE_BS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_FULL 0x00902064 /* R--4R */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_FULL__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_FULL_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_FULL_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_PHASE 0x00902068 /* R--4R */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_PHASE__PRIV_LEVEL_MASK 0x00902030 /* */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_PHASE_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_TRAINING_PROFILE_PHASE_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL 0x00902074 /* RW-4R */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL__PRIV_LEVEL_MASK 0x00902034 /* */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_PRBS_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_PRBS_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_TRAINING_ARRAY_CTRL_PRBS_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_SW_CONFIG 0x00902078 /* RW-4R */ #define NV_PFB_FBPA_0_SW_CONFIG__PRIV_LEVEL_MASK 0x00902034 /* */ #define NV_PFB_FBPA_0_SW_CONFIG_PTRIM_OPT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_PTRIM_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_PTRIM_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_SELFREF_OPT 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_SELFREF_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_SELFREF_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_MSCG_OPT 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_MSCG_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_MSCG_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_GC6_HIB_OPT 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_GC6_HIB_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_GC6_HIB_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_PA_FALCON_OPT 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_PA_FALCON_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_PA_FALCON_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_NOISE_CFG1 0x0090207C /* RW-4R */ #define NV_PFB_FBPA_0_NOISE_CFG1__PRIV_LEVEL_MASK 0x00902034 /* */ #define NV_PFB_FBPA_0_NOISE_CFG1_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG1_TRAFFIC 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_TRAFFIC_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG1_TRAFFIC_MANUAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_NOISE_CFG1_MANUAL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_MANUAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG1_ACTIVE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG1_THROTTLE 11:4 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_THROTTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG1_BANK 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG1_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_NOISE_CFG2 0x00902080 /* RW-4R */ #define NV_PFB_FBPA_0_NOISE_CFG2__PRIV_LEVEL_MASK 0x00902034 /* */ #define NV_PFB_FBPA_0_NOISE_CFG2_BURST 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_NOISE_CFG2_BURST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK 0x00900B04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB 0x00900B14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK 0x00900B08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB 0x00900B18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL 0x00900EE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CTRL 0x00900B0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CTRL 0x00900B10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET 0x00900B00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_IB 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_IB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_OB 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_OB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_ADDR 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_WCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTRPLTR_OFFSET_WCK_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x00900B20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x00900B24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x00900B28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x00900B2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x00900B30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x00900B34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x00900B38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x00900B3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x00900B40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x00900B44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x00900B48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x00900B4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x00900B50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x00900B54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x00900B58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x00900B5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x00900B60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x00900B64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x00900B68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x00900B6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x00900B70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x00900B74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x00900B78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x00900B7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x00900BC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x00900BC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x00900BC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x00900BCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x00900BD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x00900BD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x00900BD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x00900BDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x00900BE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x00900BE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x00900BE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x00900BEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x00900BF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x00900BF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x00900BF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x00900BFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x00900C00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x00900C04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x00900C08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x00900C0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x00900C10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x00900C14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x00900C18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x00900C1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x00900C20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x00900C24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x00900C28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x00900C2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x00900C30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x00900C34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x00900C38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x00900C3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x00900C40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x00900C44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x00900C48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x00900C4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x00900C50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x00900C54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x00900C58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x00900C5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x00900C60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x00900C64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x00900C68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x00900C6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x00900C70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x00900C74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x00900C78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x00900C7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x00900CC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x00900CC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x00900CC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x00900CCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x00900CD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x00900CD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x00900CD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x00900CDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x00900CE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x00900CE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x00900CE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x00900CEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x00900CF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x00900CF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x00900CF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x00900CFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x00900D00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x00900D04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x00900D08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x00900D0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x00900D10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x00900D14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x00900D18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x00900D1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x00900D70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x00900D74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x00900D78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x00900D7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x00900D80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x00900D84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x00900D88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x00900D8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x00900D90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x00900D94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x00900D98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x00900D9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x00900DA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x00900DA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x00900DA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x00900DAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x00900DB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x00900DB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x00900EE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x00900EE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD 0x00900D28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DLCELL 0x0000000B /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL_RANK1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_LEG_TRIM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD 0x00900D2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL 0x00900D30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_TX_DCC_MODE 27:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_TX_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_PHASE0_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_PAD_CTRL_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL 0x00900D34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE 26:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE 30:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0 0x00900D38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2 0x00900D40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_VREF_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE 10:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TX_E_DCC 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1 0x00900DB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2 0x00900DBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1 0x00900DC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2 0x00900DC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1 0x00900DC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2 0x00900DCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1 0x00900DD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2 0x00900DD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1 0x00900DD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2 0x00900DDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1 0x00900DE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2 0x00900DE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1 0x00900DE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2 0x00900DEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1 0x00900DF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2 0x00900DF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x009005A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x009005A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x009005A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x009005AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x009005B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x009005B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x009005B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x009005BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x009005C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x009005C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x009005C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x009005CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x009005D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x009005D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x009005D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x009005DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x009005E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL 0x009005E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC 27:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC 0x00900D44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_CMD_CONFIG 13:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_CMD_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_DQ_CONFIG 23:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_DQ_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_MODE 28:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1 0x00900D48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC 7:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DFE_CTRL 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_DFE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_RFU 20:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL 0x00900EB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_RX_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL 0x00900EB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL 0x00900EB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_RX_SUBP0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_RX_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP0 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_RX_SUBP1 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_RX_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP1 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL 0x00900EBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL 0x00900ED0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL 0x00900EC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL_CLKDIST_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL_CLKDIST_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2 0x00900EC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_SPARE 4:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_IREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL 8:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_IREF_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CK_IREF_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_WCK_IREF_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_WCK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG 23:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3 0x00900EEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4 0x00900EF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5 0x00900EF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD 9:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD 11:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD 15:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD 17:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_SPARE 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_DQ_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_SPARE 21:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VTT_CNTL5_CMD_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL 0x00900EF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG 0x00900ECC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_CK 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_WCK 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_WCK_PATTERN_MASK 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_MISC_CONFIG_WCK_PATTERN_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2 0x00900ED4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_TX_DRVDN 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_TX_DRVUP 9:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_E_PU40 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_E_PU40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_FREEZE 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DELTA_DRVR 17:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DELTA_DRVF 21:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR 25:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF 29:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_FORCE_CAL_UPDATE 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CML_CLK2_FORCE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0 0x00901004 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_FBIO_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_LOOPBK_MODE 4:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_LOOPBK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_TX_EN_SETUP 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_TX_EN_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_BRLSHFT 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_BRLSHFT_1UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_DRAM_ECC 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_DRAM_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_DRAM_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_LEKAGE_STRENGTH 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG0_LEKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_1 0x00901008 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_1_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_1_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_2 0x0090100C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_2_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_SPARE_2_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL 0x00901010 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_OB_BYTE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_BYTE 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF 17:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL 0x00901014 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG 0x00901018 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_CLK_CNTRL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_NORMAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_FLIP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY 0x00901020 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR 5:5 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR 7:7 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR 9:9 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR 11:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR 13:13 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR 15:15 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY 0x00901024 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR 4:4 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x0090103C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x00901040 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x00901044 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x00901048 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x0090104C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x00901050 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x00901054 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x00901058 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x0090105C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x00901060 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x00901064 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x00901068 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x0090106C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x00901070 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x00901074 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x00901078 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x0090107C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x00901080 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x00901084 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x00901088 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x0090108C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x00901090 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x00901094 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x00901098 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x0090109C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x009010A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x003FFFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x009010A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x000FFFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x009010A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x009010AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x009010B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x009010B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x009010B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x009010BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x009010C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x009010C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x009010C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE 0x009010CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_TEMP 31:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG3_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG4_BRICK_SPARE 0x009010D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG4_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG4_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG4_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG5_BRICK_SPARE 0x009010D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG5_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG5_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG5_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x009010D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x009010DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x009010E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x009010E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x009010E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x009010EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x009010F0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x009010F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x009010F8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x009010FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x00901100 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x00901104 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x00901108 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x0090110C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x00901110 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x00901114 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x00901118 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x0090111C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x00901120 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x00901124 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x00901128 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x0090112C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x00901130 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x00901134 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x00901138 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x0090113C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x00901140 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x00901144 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x00901148 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x0090114C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x00901150 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x00901154 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL 0x00901158 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY 8:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT 14:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS 20:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_START_TRM 31:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL_START_TRM_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1 0x009011DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x00901160 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x00901164 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x00901168 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x0090116C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x00901170 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x00901174 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x00901178 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x0090117C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x00901180 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE_INIT 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x00901184 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x00901188 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x0090118C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x00901190 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x00901194 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x00901198 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x0090119C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x009011A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x009011A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG 0x009011A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_FREEZE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_CMD_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_CMD_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_SAMPLE_COUNT 6:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALCFG_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009011B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009011B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009011BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009011C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009011C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009011C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009011CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009011D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR 0x009011D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE 16:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x009011D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x009011FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x00901200 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x00901204 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x00901208 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x0090120C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x00901210 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x00901214 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x00901218 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG 0x0090121C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL 15:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0 0x00901224 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM 21:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1 0x00901228 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL 16:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE1 0x00901030 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE1_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE1_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE2 0x00901034 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE2_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE2_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE3 0x00901038 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE3_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_DONT_USE3_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x009012C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x009012C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x009012CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x009012D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG6_BRICK_SPARE 0x009012D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG6_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE 0x009012D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE 0x009012DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG9_BRICK_SPARE 0x009012F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG9_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE 0x009012E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE 0x009012E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x00901700 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x00901704 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x00901708 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x0090170C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x00901710 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x00901714 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x00901718 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x0090171C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x00901720 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x00901724 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x00901728 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x0090172C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x00901730 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x00901734 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x00901738 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x0090173C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x00901740 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x00901744 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x00901748 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x0090174C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x00901750 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x00901754 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x00901758 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x0090175C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x00901760 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x00901764 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x00901768 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x0090176C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x00901770 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x00901774 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x00901778 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x0090177C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x00901780 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x00901784 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x00901788 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x0090178C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x00901790 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x00901794 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x00901798 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x0090179C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x009017A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x009017A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x009017A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x009017AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x009017B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x009017B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x009017B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x009017BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x009017C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x009017C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x009017C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x009017CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x009017D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x009017D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x009017D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x009017DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x009017E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x009017E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x009017E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x009017EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x009017F0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x009017F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x009017F8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x009017FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x00901800 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x00901804 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x00901808 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x0090180C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x00901810 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x00901814 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x00901818 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x0090181C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x00901860 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x00901864 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x00901868 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x0090186C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x00901870 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x00901874 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x00901878 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x0090187C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x00901880 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x00901884 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x00901888 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x0090188C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x00901890 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x00901894 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x00901898 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x0090189C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x009018A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x009018A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x009018A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x009018AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x009018B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x009018B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x009018B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x009018BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x009018D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x009018D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x009018D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x009018DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x009018E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x009018E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x009018E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x009018EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x009018F0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x009018F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x009018F8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x009018FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x00901900 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x00901904 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x00901908 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x0090190C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x00901910 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x00901914 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x00901918 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x0090191C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x00901920 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x00901924 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x00901928 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x0090192C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x00901930 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x00901934 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x00901938 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x0090193C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x00901940 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x00901944 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x00901948 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x0090194C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x00901950 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x00901954 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x00901958 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x0090195C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x00901960 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x00901964 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x00901968 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x0090196C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x00901970 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x00901974 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x00901978 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x0090197C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x00901980 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x00901984 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x00901988 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x0090198C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x00902600 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x00902604 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x00902608 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x0090260C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x00902610 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x00902614 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x00902618 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x0090261C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x00902620 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x00902624 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x00902628 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x0090262C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x00902630 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x00902634 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x00902638 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x0090263C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x00902640 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x00902644 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x00902648 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x0090264C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x00902650 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x00902654 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x00902658 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x0090265C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x00902660 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x00902664 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x00902668 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x0090266C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x00902670 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x00902674 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x00902678 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x0090267C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x00902680 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x00902684 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x00902688 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x0090268C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x00902690 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x00902694 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x00902698 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x0090269C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x009026A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x009026A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x009026A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x009026AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x009026B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x009026B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x009026B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x009026BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x009026C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x009026C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x009026C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x009026CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x009026D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x009026D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x009026D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x009026DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x009026E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x009026E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x009026E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x009026EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x009026F0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x009026F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x009026F8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x009026FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x00902700 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x00902704 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x00902708 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x0090270C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x00902710 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x00902714 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x00902718 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x0090271C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x00902720 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x00902724 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x00902728 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x0090272C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x00902730 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x00902734 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x00902738 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x0090273C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x00902740 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x00902744 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x00902748 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x0090274C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x00902750 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x00902754 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x00902758 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x0090275C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x00902760 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x00902764 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x00902768 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x0090276C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x00902770 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x00902774 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x00902778 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x0090277C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT 0x009027A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x009027A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT 0x009027A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x009027AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT 0x009027B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_DDLLCAL_LT_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x00901990 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x00901994 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x00901998 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x0090199C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x009019A0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x009019A4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x009019A8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x009019AC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x009019B0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x009019B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x009019B8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x009019BC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x009019C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x009019C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x009019C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x009019CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x009019D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x009019D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x009019D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x009019DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x009019E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x009019E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x009019E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x009019EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x00901FC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x00901FC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x00901FC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x00901FCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x00901FD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x00901FD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x00901FD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x00901FDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x00901FE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x00901FE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x00901FE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x00901FEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x00901FF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x00901FF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x00901FF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x00901FFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x00901820 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x00901824 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x00901828 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x0090182C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x00901830 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x00901834 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x00901838 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x0090183C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL 0x00901A00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY 11:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_STARTVAL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_STARTVAL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SEL_ODD 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SEL_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SEL_VREFU 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_OFFSET_CAL_CTRL_SEL_VREFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_MISC_CTRL 0x00901A04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VREF_MISC_CTRL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x00901A10 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x00901A14 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x00901A18 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x00901A1C /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x00901A20 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x00901A24 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x00901A28 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x00901A2C /* R--4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x00901A30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x00901A34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x00901A38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x00901A3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x00901A40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x00901A44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x00901A48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x00901A4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x00901A50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x00901A54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x00901A58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x00901A5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x00901A60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x00901A64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x00901A68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x00901A6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x00901A70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x00901A74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x00901A78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x00901A7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x00901A80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x00901A84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x00901A88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x00901A8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00901A90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00901A94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00901A98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00901A9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00901AA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00901AA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00901AA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00901AAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00901AB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00901AB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00901AB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00901ABC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00901AC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00901AC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00901AC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00901ACC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00901AD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00901AD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00901AD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00901ADC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00901AE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00901AE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00901AE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00901AEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00901AF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00901AF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00901AF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00901AFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00901B00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00901B04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00901B08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00901B0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00901B10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00901B14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00901B18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00901B1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00901B20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00901B24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00901B28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00901B2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00901B30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00901B34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00901B38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00901B3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00901B40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00901B44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00901B48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00901B4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00901B50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00901B54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00901B58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00901B5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00901B60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00901B64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00901B68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00901B6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00901B70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00901B74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00901B78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00901B7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00901B80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00901B84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00901B88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00901B8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00901B90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00901B94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00901B98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00901B9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00901BA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00901BA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00901BA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00901BAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00901BB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00901BB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00901BB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00901BBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00901BC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00901BC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00901BC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00901BCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00901BD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00901BD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00901BD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00901BDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00901BE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00901BE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00901BE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00901BEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00901BF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00901BF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00901BF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00901BFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00901C00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00901C04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00901C08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00901C0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00901C10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00901C14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00901C18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00901C1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00901C20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00901C24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00901C28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00901C2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00901C30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00901C34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00901C38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00901C3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00901C40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00901C44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00901C48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00901C4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00901C50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00901C54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00901C58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00901C5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00901C60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00901C64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00901C68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00901C6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00901C70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00901C74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00901C78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00901C7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00901C80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00901C84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00901C88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00901C8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00901C90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00901C94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00901C98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00901C9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00901CA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00901CA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00901CA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00901CAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00901CB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00901CB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00901CB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00901CBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00901CC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00901CC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00901CC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00901CCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00901CD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00901CD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00901CD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00901CDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00901CE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00901CE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00901CE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00901CEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00901CF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00901CF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00901CF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00901CFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00901D00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00901D04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00901D08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00901D0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00901D10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00901D14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00901D18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00901D1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00901D20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00901D24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00901D28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00901D2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00901D30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00901D34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00901D38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00901D3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00901D40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00901D44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00901D48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00901D4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00901D50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00901D54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00901D58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00901D5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00901D60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00901D64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00901D68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00901D6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00901D70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00901D74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00901D78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00901D7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00901D80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00901D84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00901D88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00901D8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x00901DA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x00901DA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x00901DA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x00901DAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x00901DB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x00901DB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x00901DB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x00901DBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x00901DC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x00901DC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x00901DC8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x00901DCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x00901DD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x00901DD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x00901DD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x00901DDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x00901DE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x00901DE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x00901DE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x00901DEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x00901DF0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x00901DF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x00901DF8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x00901DFC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLLCAL 0x00901E00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLLCAL 0x00901E04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLLCAL 0x00901E08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLLCAL 0x00901E0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLLCAL 0x00901E10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLLCAL 0x00901E14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLLCAL 0x00901E18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLLCAL 0x00901E1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF 0x00901E20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLLCAL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF 0x00901E24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF 0x00901E28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF 0x00901E2C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF 0x00901E30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF 0x00901E34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF 0x00901E38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF 0x00901E3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF 0x00901E40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF 0x00901E44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1 0x00901E48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2 0x00901E4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1 0x00901E50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2 0x00901E54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1 0x00901E58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2 0x00901E5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1 0x00901E60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2 0x00901E64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1 0x00901E68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2 0x00901E6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1 0x00901E70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2 0x00901E74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1 0x00901E78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2 0x00901E7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1 0x00901E80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2 0x00901E84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU 0x00901E88 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU 0x00901E8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU 0x00901E90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU 0x00901E94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU 0x00901E98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU 0x00901E9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU 0x00901EA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU 0x00901EA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD 0x00901EA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD 0x00901EAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD 0x00901EB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD 0x00901EB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD 0x00901EB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD 0x00901EBC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD 0x00901EC0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD 0x00901EC4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT 0x00901F30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BG_VTT__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_TEMP_COEFF 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_TEMP_COEFF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_IBG_CNTL 4:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_BG_CNTL 8:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_LV_CDBVAUXC 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_LV_CDBVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_LIMITER 16:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_CDBVAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BG_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB 0x00901F4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB 0x00901F40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB 0x00901F3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB 0x00901F44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS 0x00901F48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SUBP0_CK 10:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SUBP1_CK 23:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1 0x00901F50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0 0x00902780 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1 0x00902784 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2 0x00902788 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3 0x0090278C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0 0x00902790 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1 0x00902794 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2 0x00902798 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3 0x0090279C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING 0x00901F54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_RD_GAIN 7:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_RD_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_WR_GAIN 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_WR_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET 20:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EDGE_BRLSHFT 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EDGE_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_CENTER_BRLSHFT 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_CENTER_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_BLOCK_COUNT 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_BLOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EN 27:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_HUNT_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_HUNT_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_USE_CENTER_ONLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_USE_CENTER_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_HALF_RATE_EDC 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_HALF_RATE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING 0x00901F58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_GAIN 6:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_ACCUM 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_ACCUM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN 10:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT 19:11 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW 20:20 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW 21:21 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF 28:22 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_VREF_EDGE_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_VREF_EDGE_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2 0x009027B4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_SHADOW_LOAD 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_SHADOW_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_SHADOW_SELECT 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_SHADOW_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_CDR_MASK 9:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING2_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1 0x009027B8 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFP_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFP_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFP_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFP_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFN_EVEN 23:16 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFN_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFN_ODD 31:24 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ1_VREFN_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2 0x009027BC /* R--4R */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x009027C8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x009027CC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x009027D0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x009027D4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x009027D8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x009027DC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x009027E0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x009027E4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x009027E8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x009027EC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x009027F0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x009027F4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x009027F8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x009027FC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x00902800 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x00902804 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG 0x00901F5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT 11:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW 13:13 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW 14:14 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW 15:15 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DQ_SEL 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DQ_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL 22:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DIR_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DIR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL 26:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW 27:27 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW 28:28 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1 0x00901F60 /* R--4R */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI 6:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI 13:7 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_DQ_PI 20:14 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_DQ_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT 26:21 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x00901F64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x00901F68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x00901F6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x00901F70 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x00901F74 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x00901F78 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x00901F7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x00901F80 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14 0x00901F84 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CFG14__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE1 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE2 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE3 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE4 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE5 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE6 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE7 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_EDC_PIN_STATE_BYTE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CFG14_FORCE_PIN_STATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CFG14_FORCE_PIN_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC 0x00901F8C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HSDAC__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_HSDAC_EN_X 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_EN_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SIGNAL_SEL_X 4:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SIGNAL_SEL_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_OFFSET_X 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_OFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SELECT_X 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SELECT_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_EN_Y 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_EN_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SIGNAL_SEL_Y 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SIGNAL_SEL_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_OFFSET_Y 26:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_OFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SELECT_Y 29:27 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HSDAC_SELECT_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0 0x009027C0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC0_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1 0x009027C4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_CMD_HSDAC1_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0 0x00901F90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1 0x00901F94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS 0x00901F98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_TERM 23:23 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_TERM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI 0x00901F9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_RX 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_TX 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_SPARE 31:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_INTERP_2UI_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x00901FA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x00901FA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x00901FA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x00901FAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x00901FB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x00901FB4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1 0x00901FB8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1__PRIV_LEVEL_MASK 0x009008FC /* */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_CDR_MASK 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS 15:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_SUPPORT 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_EDC_TRACKING1_LOCK_SUPPORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK 0x00903C7C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG 0x00903C90 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SYNCMODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SYNCMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SYNCMODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SYNCMODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_LCKDET 3:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_LCKDET_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_LCKDET_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE 4:4 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_PLL_LOCK 5:5 /* R--UF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_FSTLCK 6:6 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_IDDQ 7:7 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE_BG 8:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX 9:9 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_BYPASSPLL 10:10 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_BYPASSPLL_VCO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_BYPASSPLL_BYPASSCLK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO 11:11 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE 13:13 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL 0x00903C94 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF 0x00903C98 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_NDIV_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO 0x00903C9C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST 0x00903CA0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL 9:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL 12:10 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE 16:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RFU 24:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG 0x00903CA4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN 13:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK 20:14 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK 27:21 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG1 0x00903CA8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG1_TX_EN 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_CFG1_TX_EN_INIT 0x00FFD98A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD1 0x00903CAC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD1_TX 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD1_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD2 0x00903CB0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD2_RX 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_BRICK_TEST_PWRD2_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE 0x00903CCC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA 23:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG13_BRICK_SPARE 0x00903CD0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG13_BRICK_SPARE__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB 15:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG 0x00903CD4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF 5:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_INT_VREF 11:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_INT_VREF_INIT 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV 19:17 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE 30:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1 0x00903CD8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK 7:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK 14:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK 21:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK 28:22 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL 31:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2 0x00903CDC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT 0:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE 1:1 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE 3:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH 6:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW 10:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD 12:11 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST 15:13 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV 24:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV 26:25 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1 0x00903CE0 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREG14V_CTRL 5:4 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREG10V_CTRL 7:6 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG1_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0 0x00903CE4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER 5:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL 26:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1 0x00903CE8 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD 1:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL 6:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL 8:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF 11:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST 14:12 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_RFU 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_HBMCDB_CFG1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0 0x00903CEC /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL 4:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU_INIT 0x00000030 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG2 0x00903CF4 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG2_SETUP 27:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBMPLL_CFG2_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG 0x00903C00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN 0x00903C04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX 0x00903C08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL 0x00903C0C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB 0x00903C10 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_RISE_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_FALL_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_TERM 22:16 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2 0x00903C14 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_RISE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_FALL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_SPARE 15:15 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3 0x00903C18 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4 0x00903C1C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5 0x00903C20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x00903C30 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x00903C34 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x00903C38 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x00903C3C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x00903C40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x00903C44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x00903C48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x00903C4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x00903C50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x00903C54 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x00903C58 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x00903C5C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x00903C60 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x00903C64 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2 0x00903C68 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3 0x00903C6C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG 0x00903D00 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_SYNC_MODE 1:1 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX 3:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL 0x00903D04 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2 0x00903D08 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_SEL_TESTOUT 2:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_SETUP2 27:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_TESTMODE 28:28 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_REFMPLL_CFG2_TESTMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG 0x00903D20 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0 3:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4 4:4 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL 0x00903D24 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL 31:29 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2 0x00903D28 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2_SETUP2 11:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0 0x00903D40 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_LV_VAUXC 18:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_BW 22:19 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD 27:26 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST 30:28 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1 0x00903D44 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CMD_VTT_SPARE 17:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CMD_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_BYTE_VTT_SPARE 19:18 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_BYTE_VTT_SPARE_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VTT_SPARE 21:20 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_CDB_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL 29:22 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL 0x00903D48 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_BG_CNTL 3:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IBG_CNTL 5:4 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IRX_CNTL 7:6 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IRX_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IRX_SRC_SEL 10:8 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IRX_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEMP_COEF 13:11 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_CDB_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_CDB_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_SEL 20:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_E_RES_CAL_CODE_IN 21:21 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_E_RES_CAL_CODE_IN_BYP_SEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL 26:22 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IBG_SRC_SEL 29:27 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CDBCTRL_IBG_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV 0x00903D4C /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL 2:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_SPARE 10:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_PTRIM_OVRD 11:11 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_PTRIM_OVRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH 13:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_DRAMPLL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_ONESOURCE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_REFMPLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_DPD 16:16 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_DPD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_DPD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE 17:17 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL 18:18 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2 0x00903D50 /* RW-4R */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2__PRIV_LEVEL_MASK 0x00903C7C /* */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM 2:0 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM 5:3 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM 8:6 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_BGAP_TRIM 11:9 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_BGAP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_E_TRIM 12:12 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_E_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXC 16:13 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXC_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXP 20:17 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VAUXP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VCLAMP 24:21 /* RWIUF */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VCLAMP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_0_FBIO_VTT_CTRL2_CDB_VCLAMP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_1_CFG1 0x00904204 /* RW-4R */ #define NV_PFB_FBPA_1_CSTATUS 0x0090420C /* R--4R */ #define NV_PFB_FBPA_1_PRI_FBPA_CG 0x00904000 /* RWE4R */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL(i) (0x009049C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x00906030 /* */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_1_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009051B4 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009051B8 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009051BC /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009051C0 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009051C4 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009051C8 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009051CC /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009051D0 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBMPLL_COEFF 0x00907C98 /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO 0x00907C9C /* RW-4R */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00907C7C /* */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_1_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_CSTATUS 0x0090820C /* R--4R */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG 0x00908420 /* RW-4R */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x00908168 /* */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_2_PRI_FBPA_CG 0x00908000 /* RWE4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009091B4 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009091B8 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009091BC /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009091C0 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009091C4 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009091C8 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009091CC /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009091D0 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBMPLL_COEFF 0x0090BC98 /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO 0x0090BC9C /* RW-4R */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x0090BC7C /* */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_2_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_3_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_3_CSTATUS 0x0090C20C /* R--4R */ #define NV_PFB_FBPA_3_PRI_FBPA_CG 0x0090C000 /* RWE4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x0090D1B4 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x0090D1B8 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x0090D1BC /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x0090D1C0 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x0090D1C4 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x0090D1C8 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x0090D1CC /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x0090D1D0 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBMPLL_COEFF 0x0090FC98 /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO 0x0090FC9C /* RW-4R */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x0090FC7C /* */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_3_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_CSTATUS 0x0091020C /* R--4R */ #define NV_PFB_FBPA_4_PRI_FBPA_CG 0x00910000 /* RWE4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009111B4 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009111B8 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009111BC /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009111C0 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009111C4 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009111C8 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009111CC /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009111D0 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBMPLL_COEFF 0x00913C98 /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO 0x00913C9C /* RW-4R */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00913C7C /* */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_4_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_5_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_5_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_5_CSTATUS 0x0091420C /* R--4R */ #define NV_PFB_FBPA_5_PRI_FBPA_CG 0x00914000 /* RWE4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009151B4 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009151B8 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009151BC /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009151C0 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009151C4 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009151C8 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009151CC /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009151D0 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBMPLL_COEFF 0x00917C98 /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO 0x00917C9C /* RW-4R */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00917C7C /* */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_5_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK 0x00980168 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK 0x00980148 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK 0x0098014C /* RW-4R */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK 0x00980170 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_ecc" /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK 0x009801B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK 0x009801B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK 0x00982578 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK 0x0098000C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK 0x00982250 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK 0x0098086C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_SPARE 0x00980050 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SPARE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SPARE_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_INIT 0xFF001040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_OFIFO_OFFSET 5:0 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_OFIFO_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_CMDFF_DEPTH 12:8 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_CMDFF_DEPTH_INIT 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_CMDFF_DEPTH_MAX 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_CMDFF_DEPTH_SAFE 0x00000004 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_SYNC_PULSE_POLARITY 13:13 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_SYNC_PULSE_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_OFIFO_OFFSET_POLARITY 14:14 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_OFIFO_OFFSET_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_PDEN_OFFSET 19:16 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_PDEN_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_L2_CRC_MODE 20:20 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_L2_CRC_MODE_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_VS_DELAY 23:21 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_VS_DELAY_INIT 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BIT30 30:30 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BIT30_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BUG765178_TEST_MODE 31:31 /* ----F */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BUG765178_TEST_MODE_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BUG765178_TEST_MODE_SKIP 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE_BITS_BUG765178_TEST_MODE_RUN 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_SPARE2 0x009800CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_SPARE2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SPARE2_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SPARE2_BITS_INIT 0xFFFF0000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FALCON_MONITOR 0x00980054 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FALCON_MONITOR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FALCON_MONITOR_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FALCON_MONITOR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER 0x00980064 /* R--4R */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_DEV 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_ECO 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_MINOR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_MINOR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_MAJOR 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FALCON_CTRL_VER_MAJOR_INIT 0x00000004 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD 0x00980060 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CFG_PWRD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_80 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_120 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_RCVR_PWRD_DLY 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_RCVR_PWRD_DLY_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG_PWRD_BLCG_USE_TRAINING_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0 0x00980080 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DEBUG_0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_0_MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_MRS_256 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_MRS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PERIODIC_QRST 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PERIODIC_QRST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PERIODIC_QRST_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_SPARE0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_PIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_PIN_CMD 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_PIN_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_PIN_DEBUG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_MODE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_MODE_WRITE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_ODT_MODE_NOTREAD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_USE_CFG0_BL8_HBM 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_USE_CFG0_BL8_HBM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_USE_CFG0_BL8_HBM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BL16EDC_SET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BL16EDC_SET_EVEN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BL16EDC_SET_ODD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_WFT_IDLE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_WFT_IDLE_NEW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_WFT_IDLE_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FB_IDLE_NOPBR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FB_IDLE_NOPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FB_IDLE_NOPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HANDSHAKE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HANDSHAKE_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HANDSHAKE_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FORCE_FULL_MEMREF 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FORCE_FULL_MEMREF_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_FORCE_FULL_MEMREF_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_R2P_BL_ADJUST 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_R2P_BL_ADJUST_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_R2P_BL_ADJUST_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_POST_SP_TR 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_POST_SP_TR_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_POST_SP_TR_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_TOGGLE_FIX 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_TOGGLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_TOGGLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DISABLE_HWACPDIDLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_MODE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_MODE_SDR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_MODE_DDR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PRI_REG_UPDATE_EXT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PRI_REG_UPDATE_EXT_15 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_PRI_REG_UPDATE_EXT_31 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_REFCFG_REQ_PENDING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_REFCFG_REQ_PENDING_FIXED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_REFCFG_REQ_PENDING_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BECS_ACK 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BECS_ACK_LEVEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_BECS_ACK_PULSE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DRAM_ACK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DRAM_ACK_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_DRAM_ACK_IDLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_TREFI_UPDATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_0_TREFI_UPDATE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_0_TREFI_UPDATE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_1 0x00980084 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DEBUG_1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_1_L2_ECC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_1_L2_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_1_L2_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DEBUG_2 0x00982340 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_2_XBAR_ASR_OK 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_2_XBAR_ASR_OK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_2_XBAR_ASR_WAKEUP 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_2_XBAR_ASR_WAKEUP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_2_STOP_FB_REQ 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_2_STOP_FB_REQ_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_2_STOP_FB_ACK 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_2_STOP_FB_ACK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_SUBPIDLE(i) (0x00982344+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_DEBUG_SUBPIDLE__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_SUBPIDLE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_SUBPIDLE_IDLES 27:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_SUBPIDLE_IDLES_INIT 0x0FFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_PAIDLE 0x0098234C /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_PAIDLE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_PAIDLE_IDLES 21:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_PAIDLE_IDLES_INIT 0x003FFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0 0x00982350 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0_EN_COUNT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0_EN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0_CLR_COUNT 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_0_CLR_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1 0x00982354 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_1 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_2 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_3 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DEBUG_CTRL_1_SEL_3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_BASE 0x00982358 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_BASE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_BASE 0x0098235C /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_BASE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_0 0x00982360 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_0 0x00982364 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_1 0x00982368 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_1 0x0098236C /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_2 0x00982370 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_2 0x00982374 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_3 0x00982378 /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_LO_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_3 0x0098237C /* R--4R */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DEBUG_COUNT_HI_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP 0x009801DC /* R--4R */ #define NV_PFB_FBPA_MC_0_ROW_REMAP__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_ENABLE 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD(i) (0x009801F0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ENTRY_VLD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ENTRY_VLD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ROW 25:9 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ROW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_RD_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR(i) (0x009801F8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR__PRIV_LEVEL_MASK 0x0098000C /* */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_ROW 25:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ROW_REMAP_WR_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD 0x00980090 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TESTCMD__PRIV_LEVEL_MASK 0x0098014C /* */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LPDDR4_SELF_REF_ENTRY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LPDDR4_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CKE_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CS1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_CAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_HBM_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_WE_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_RES_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_4_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR6_SELF_REF_ENTRY1 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR6_SELF_REF_ENTRY2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_BANK_DDR6_SELF_REF_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR 25:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_ADR_UPPER_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_GO_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_HOLD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT 0x00980094 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT__PRIV_LEVEL_MASK 0x0098014C /* */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ADR_DRAM1 10:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ADR_DRAM1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DEBUG 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DEBUG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ODT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ODT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ODT_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_RW_CMD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_RW_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_MRS_CMD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_MRS_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DR_CMD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DR_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_4CK_CMD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_4CK_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_LAM_CMD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_LAM_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_CMD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_SID 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_SID_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1 0x00980154 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1__PRIV_LEVEL_MASK 0x0098014C /* */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_ENTRY 0x00018018 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_EXIT 0x00014014 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0 0x009800A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1 0x009800A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2 0x009800A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3 0x009800AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0 0x009800B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1 0x009800B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2 0x009800B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3 0x009800BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI 0x009800C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_DBI_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC 0x009800C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_ECC_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE 0x009800C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCK01 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCKB01 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCK23 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCKB23 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP0_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCK01 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCKB01 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCK23 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCKB23 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SWIZZLE_BYTE_SUBP1_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM 0x00980100 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PM__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC0 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT0 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT1 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ0 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ2 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC2 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ3 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ4 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ5 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC4 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT4 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT5 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ4 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ6 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRTYREQ7 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC6 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SLC7 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT6 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDAT7 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ6 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READREQ7 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_SUBP0 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_SUBP1 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_CH0_SUBP0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_CH0_SUBP1 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_CH1_SUBP0 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_ACT_CH1_SUBP1 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_BANK_ACT_SUBP0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_BANK_ACT_SUBP1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_NO_ACT_SUBP0 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_NO_ACT_SUBP1 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP0 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP1 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BANKQ_EMPTY_SUBP0 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BANKQ_EMPTY_SUBP1 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BA_OUTPUT 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BA_SIGS 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_CKG0 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_CKG1 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRARB_SUBP0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DIRARB_SUBP1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_BANKS_SUBP0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_BANKS_SUBP1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_EXTRA_SUBP0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_EXTRA_SUBP1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RWALL 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_SUBP0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_SUBP1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_CH0_SUBP0 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_CH0_SUBP1 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_CH1_SUBP0 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RW_CH1_SUBP1 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_SUBP0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_SUBP1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_CH0_SUBP0 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_CH0_SUBP1 0x00000043 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_CH1_SUBP0 0x00000044 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_CH1_SUBP1 0x00000045 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_CH0_SUBP0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_CH0_SUBP1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_CH1_SUBP0 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_CH1_SUBP1 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_PART2_SUBP0 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_PART2_SUBP1 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_PP_SUBP0 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_WAIT_PP_SUBP1 0x0000004D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ECC_CH0_SUBP0 0x0000004E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ECC_CH0_SUBP1 0x0000004F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ECC_CH1_SUBP0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ECC_CH1_SUBP1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_FT_IDLE_SUBP0 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_FT_IDLE_SUBP1 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_CH0_SUBP0 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_CH0_SUBP1 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_CH1_SUBP0 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_CH1_SUBP1 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SUBP0 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_IDLE_SUBP1 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INFLIGHT_READ_COUNT 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INFLIGHT_READ_COUNT_VC0 0x0000005C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INFLIGHT_READ_COUNT_VC1 0x0000005D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INFLIGHT_READ_COUNT_VC2 0x0000005E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_INFLIGHT_WRITE_COUNT 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_OUT_READS 0x00000060 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_OUT_WRITES 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_PENDING_REFRESH_SUBP0 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_PENDING_REFRESH_SUBP1 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_PART2_SUBP0 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_PART2_SUBP1 0x00000065 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_SUBP0 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_SUBP1 0x00000067 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP0 0x00000068 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP1 0x00000069 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP0 0x0000006A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP1 0x0000006B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP0 0x0000006C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP1 0x0000006D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READARB_SUBP0 0x0000006E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READARB_SUBP1 0x0000006F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_READARB_VC 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_REFSB_SUBP0 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_REFSB_SUBP1 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT0_PART2_SUBP0 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT0_PART2_SUBP1 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT0_SUBP0 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT0_SUBP1 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT1_PART2_SUBP0 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT1_PART2_SUBP1 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT1_SUBP0 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RFT1_SUBP1 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_STAT_CH0_SUBP0 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_STAT_CH0_SUBP1 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_STAT_CH1_SUBP0 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_STAT_CH1_SUBP1 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_SINGLE_PASS_SUBP0 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_SINGLE_PASS_SUBP1 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_SUBP01_TRAFFIC 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_SUBP01_TRAFFIC_CH0 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_SUBP01_TRAFFIC_CH1 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WFT0_SUBP0 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WFT0_SUBP1 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WFT1_SUBP0 0x00000088 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WFT1_SUBP1 0x00000089 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP0 0x0000008A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP1 0x0000008B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRBANKQ_SUBP0 0x0000008C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRBANKQ_SUBP1 0x0000008D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEARB_SUBP0 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEARB_SUBP1 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_UTIL_SUBP0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_UTIL_SUBP1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RCMD_CH0_SUBP0 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RCMD_CH0_SUBP1 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RCMD_CH1_SUBP0 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_DRAMC_RCMD_CH1_SUBP1 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_SUBP0 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_SUBP1 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_CH0_SUBP0 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_CH0_SUBP1 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_CH1_SUBP0 0x0000009A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BUCKET_CH1_SUBP1 0x0000009B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ISO_TRACKING0_SUBP0 0x0000009C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ISO_TRACKING0_SUBP1 0x0000009D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ISO_TRACKING1_SUBP0 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ISO_TRACKING1_SUBP1 0x0000009F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC0_SUBP0 0x000000A0 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC0_SUBP1 0x000000A1 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC1_SUBP0 0x000000A2 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC1_SUBP1 0x000000A3 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC2_SUBP0 0x000000A4 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_BW_TRACKING_VC2_SUBP1 0x000000A5 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG0 0x000000A6 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG1 0x000000A7 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG2 0x000000A8 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_WRITEPULL_REQ_FIFO_SG3 0x000000A9 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_RETURN_FIFO_SG0 0x000000AA /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_RETURN_FIFO_SG1 0x000000AB /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_RETURN_FIFO_SG2 0x000000AC /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_RR_RETURN_FIFO_SG3 0x000000AD /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR0_SUBP0 0x000000AE /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR0_SUBP1 0x000000AF /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR1_SUBP0 0x000000B0 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR1_SUBP1 0x000000B1 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR2_SUBP0 0x000000B2 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR2_SUBP1 0x000000B3 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR3_SUBP0 0x000000B4 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR3_SUBP1 0x000000B5 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR4_SUBP0 0x000000B6 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SELECT_ACPD_ASR4_SUBP1 0x000000B7 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP(i) (0x009801E0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_SUBP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_SUBP__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_SUBP_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_SUBP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_ACT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_ACT_CH0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_ACT_CH1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_BANK_ACT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_NO_ACT 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACTARB_NUM_RW_BANKS 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BANKQ_EMPTY 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DIRARB 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_CH0 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_CH1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_BANKS 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_EXTRA 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_RW 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_RW_CH0 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_RW_CH1 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_WAIT_CH0 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_WAIT_CH1 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_WAIT_PART2 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_WAIT_PP 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ECC_CH0 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ECC_CH1 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_FT_IDLE 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_IDLE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_IDLE_CH0 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_IDLE_CH1 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_PENDING_REFRESH 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RDBANKQ 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RDBANKQ_PART2 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RDBANKQ_VC0_REQ_FIFO 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RDBANKQ_VC1_REQ_FIFO 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RDBANKQ_VC2_REQ_FIFO 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_READARB 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_REFSB 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RFT0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RFT0_PART2 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RFT1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RFT1_PART2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RR_STAT_CH0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_RR_STAT_CH1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_SINGLE_PASS 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WFT0 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WFT1 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WRBANKQ 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WRBANKQ_REQ_FIFO 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WRITEARB 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_WRITEPULL_UTIL 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_RCMD_CH0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_DRAMC_RCMD_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BUCKET 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BUCKET_CH0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BUCKET_CH1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ISO_TRACKING0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ISO_TRACKING1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BW_TRACKING_VC0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BW_TRACKING_VC1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_BW_TRACKING_VC2 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACPD_ASR0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACPD_ASR1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACPD_ASR2 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACPD_ASR3 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_SUBP_SELECT_ACPD_ASR4 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE(i) (0x00980180+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_HI(i) (0x00982500+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_HI__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_HI__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_HI_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_WINDOW(i) (0x009801D0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_WINDOW__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_WINDOW__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_WINDOW_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_WINDOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_CTL 0x009801D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_CTL__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_CTL_INVERT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_CAPTURE_CTL_INVERT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET(i) (0x00982530+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_BUCKET__SIZE_1 11 /* */ #define NV_PFB_FBPA_MC_0_PM_BUCKET__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL 0x0098255C /* RW-4R */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE_RD_CMD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE_WR_CMD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE_COL_CMD 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE_ANY_CMD 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_BUCKET_CTL_TYPE_ISO_TRACKING 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_CTL 0x00982560 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PM_CTL__PRIV_LEVEL_MASK 0x009801B0 /* */ #define NV_PFB_FBPA_MC_0_PM_CTL_ISO_SUBID_MSB_INDEX 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_CTL_ISO_SUBID_MSB_INDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PM_CTL_ISO_SUBID_MSB_INDEX_MAX 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_REG_CTL 0x00982564 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REG_CTL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REG_CTL_FBIO_NOACK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REG_CTL_FBIO_NOACK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REG_CTL_FBIO_NOACK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_ASR_NUM(i) (0x00980110+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_ASR_NUM__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_NUM__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_NUM_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_ASR_NUM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_ASR_CYCCNT(i) (0x00980118+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_ASR_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_CYCCNT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_ASR_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_ASR_MAXCYC(i) (0x00980120+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_PM_ASR_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_MAXCYC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PM_ASR_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_PM_ASR_MINCYC(i) (0x00980128+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_PM_ASR_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_MINCYC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASR_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PM_ASR_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_CYCCNT(i) (0x00980130+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_CYCCNT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MAXCYC(i) (0x00980138+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MAXCYC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MINCYC(i) (0x00980140+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MINCYC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PM_ASRSTALL_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_0_ASRCTRL_NONISO 0x00980150 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASRCTRL_NONISO__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASRCTRL_NONISO_THRESHOLD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASRCTRL_NONISO_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL 0x00980160 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_10 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_11 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_12 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_13 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_14 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_15 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_PERIOD_16 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_EN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_CTRL_INTERVAL_TIMER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_FBPS 0x00980164 /* RW-4R */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_FBPS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_FBPS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_LTCS 0x0098016C /* RW-4R */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NUM_ACTIVE_LTCS_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE0 0x00980174 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPRE0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ0_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ1_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ2_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE0_DQ3_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE1 0x00980178 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPRE1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ4_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ5_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ6_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE1_DQ7_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE2 0x0098017C /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPRE2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPRE2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE2_DBI_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPRE2_TR_PATTERN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPRE2_TR_PATTERN_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST0 0x009801B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPOST0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ0_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ1_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ2_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST0_DQ3_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST1 0x009801BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPOST1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ4_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ5_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ6_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST1_DQ7_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_WPOST2 0x009801C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WPOST2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WPOST2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WPOST2_DBI_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0 0x00980200 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CFG0__PRIV_LEVEL_MASK 0x00982250 /* */ #define NV_PFB_FBPA_MC_0_CFG0_BL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_BL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_BL_BL4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_BL_BL8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_BL_BL16 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_EXTBANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_EXTBANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_EXTBANK_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_EXTBANK__PROD_C_SINGLE_SIDED_MEM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_EXTBANK__PROD_C_DUAL_SIDED_MEM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_X8 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_X8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_X8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_CA_RETURN_TO_ZERO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_CA_RETURN_TO_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_CA_RETURN_TO_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_HBM_CMD_PARITY_OVERRIDE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_HBM_CMD_PARITY_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_HBM_CMD_PARITY_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_RATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_RATE_HALF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_RATE_FULL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_GAPLESS_WTR 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_GAPLESS_WTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_GAPLESS_WTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACPD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACPD_NO_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACPD_ACTIVE_POWERDOWN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ATR__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_DATA_SCRAMBLE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_DATA_SCRAMBLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_DATA_SCRAMBLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_SYNC 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_LOW_POWER 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_LOW_POWER_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_LOW_POWER_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_ABI 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_BURST_LENGTH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_BURST_LENGTH_4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_BURST_LENGTH_8 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_DM_ON_ADR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_DM_ON_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_DM_ON_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_TIMING_UNIT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_TIMING_UNIT_DRAMCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_TIMING_UNIT_DRAMDIV2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_CMD_PARITY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_CMD_PARITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_CMD_PARITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_ODT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_CLAMSHELL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_CLAMSHELL_X32 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_CLAMSHELL_X16 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_EARLY_VALUE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_EARLY_VALUE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_EDC_EARLY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_BG_8 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_BG_8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_BG_8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_PRE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_PRE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_AUTO_PRE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_SAME_QUSE_TWO_RANKS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_SAME_QUSE_TWO_RANKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_SAME_QUSE_TWO_RANKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_RDEDC 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_RDEDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_RDEDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_WREDC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_WREDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_WREDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_REPLAY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_REPLAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_REPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_MS01_ECC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_MS01_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_MS01_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG0_DRAM_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1 0x00980204 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CFG1__PRIV_LEVEL_MASK 0x00980148 /* */ #define NV_PFB_FBPA_MC_0_CFG1_SUBP 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_SUBP_256B 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_SUBP_512B 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_SUBP_1KB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_SUBP_2KB 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_AP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A8 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A12 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_AP_A13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_STACK 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_STACK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_STACK_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_STACK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_COL_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_COL_15 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_ROWB_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_BANK 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_BANK_2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_BANK_3 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_BANK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_BG_8_OVR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_BG_8_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_BG_8_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_BG 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_ROW_BG 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_ROW_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_ROW_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CFG1_NUM_BANKS_PER_ROW_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CSTATUS 0x0098020C /* R--4R */ #define NV_PFB_FBPA_MC_0_CSTATUS__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_RAMAMOUNT 16:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_RAMAMOUNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CSTATUS_OVERRIDE 0x0098257C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CSTATUS_OVERRIDE__PRIV_LEVEL_MASK 0x00982578 /* */ #define NV_PFB_FBPA_MC_0_CSTATUS_OVERRIDE_RAMAMOUNT 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CSTATUS_OVERRIDE_RAMAMOUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL 0x00980210 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFCTRL__PRIV_LEVEL_MASK 0x00982250 /* */ #define NV_PFB_FBPA_MC_0_REFCTRL_PUT 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL_PUT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL_GET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL_GET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL_RESET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL_RESET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL_RESET_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFCTRL_VALID 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL_VALID_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL_VALID_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ 0x00980214 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ZQ__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ZQ_CL_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_CL_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_CS_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_CS_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_CL_PERIODIC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_CL_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_CL_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_CS_PERIODIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_CS_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_CS_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_CH 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_CH_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_CH_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_RANK 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_RANK_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_PERIODIC_RANK_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ZQ_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ZQ_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ZQ_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN 0x00980218 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PIN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PIN_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_DQM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_DQM_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_DQM_INACTIVE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_RESET 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_RESET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_CKE_POLARITY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_CKE_POLARITY_ACTIVE_HI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_CKE_POLARITY_ACTIVE_LO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_A0 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_A0_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_A0_LOW 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_A0_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_WDQS_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_WDQS_MODE_RETURN_TO_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_WDQS_MODE_RETURN_TO_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PIN_WDQS_MODE_FREERUNNING 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_PIN_DBI 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PIN_DBI_X8 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD 0x0098021C /* RW-4R */ #define NV_PFB_FBPA_MC_0_PAD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PAD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_CKE__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_CMD27 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_CMD27_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_CMD27_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_CMD28 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_CMD28_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_CMD28_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_CHANNEL_PULLDN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_CHANNEL_PULLDN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_CHANNEL_PULLDN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_INPUT_DRIVER_CTRL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_INPUT_DRIVER_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_INPUT_DRIVER_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PAD_DBI 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PAD_DBI_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PAD_DBI_OVERRIDE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING 0x009803F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING_ACT2PDEN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING_ACT2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING_ACT2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING_PCHG2PDEN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING_PCHG2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING_PCHG2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING_AR2PDEN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING_AR2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING_AR2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING_DQRQPOP 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING_DQRQPOP_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING_DQRQPOP_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING_NOP2MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING_NOP2MRS_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING_NOP2MRS_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0 0x00980220 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING0_RC 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RFC 22:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RFC_MAX 0x000003FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RAS 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RAS_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1 0x00980224 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2W__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2R 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING1_W2R_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2R_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2R_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2R__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2P 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING1_R2P_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2P_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_R2P__PROD_C_SAMSUNG_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2P 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING1_W2P_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2P_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING1_W2P__PROD_C_SAMSUNG_DDR3 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2 0x00980228 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING2_RD_RCD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING2_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING2_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_RD_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_RD_RCD__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WR_RCD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING2_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING2_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WR_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WR_RCD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_RRD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING2_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING2_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_RRD_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_RRD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV__PROD_C_WL1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV__PROD_C_WL6 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING2_WDV__PROD_C_SAMSUNG_DDR3 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3 0x0098022C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE__PROD_C_CL11 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QUSE__PROD_C_SAMSUNG_DDR3 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST__PROD_C_CL11 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QRST__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QSAFE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING3_QSAFE_17 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING3_QSAFE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_QSAFE_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV_60 0x0000003C /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV_27 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV_MIN 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV_MAX 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV__PROD_C_CL11 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING3_RDV__PROD_C_SAMSUNG_DDR3 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4 0x00980230 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2WR 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2WR_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2WR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2WR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2WR__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2RD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2RD_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2RD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2RD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEX2RD__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW_40 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_FAW__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_MSB 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING4_PDEN2PDEX_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING5 0x00980234 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING5_PCHG2PDEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING5_PCHG2PDEN_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING5_PCHG2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_PCHG2PDEN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_PCHG2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_RW2PDEN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING5_RW2PDEN_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING5_RW2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_RW2PDEN_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_RW2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_ACT2PDEN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING5_ACT2PDEN_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING5_ACT2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_ACT2PDEN_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_ACT2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_AR2PDEN 31:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING5_AR2PDEN_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING5_AR2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_AR2PDEN_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING5_AR2PDEN__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6 0x00980238 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING6_PPD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING6_PPD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING6_BUS_W2R 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING6_BUS_W2R_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING6_BUS_W2R_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_DRAMC 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_DRAMC_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_DRAMC_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO_70 0x00000046 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO_20 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING6_CMD2MCIDLE_FBIO_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING7 0x0098023C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING7_REXT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING7_REXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING7_WEXT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING7_WEXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING7_ATR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATR_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATRLEN 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING7_ATRLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATRLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING7_ATRLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8 0x00980240 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING8__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING8_ODT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING8_ODT_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING8_ODT_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_ODT_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_ODTLEN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING8_ODTLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_ODTLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING8_ODTLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_QPOP_OFFSET 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING8_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_QPOP_OFFSET_ELEVEN 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING8_QPOP_OFFSET_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_RPRE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING8_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING8_RPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_WPRE 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING8_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING8_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING8_WPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING9 0x00980244 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING9__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDL_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING9_CCDS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_ADR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_ADR_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_WCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_WCK_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_WREDC 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING9_QPOP_OFFSET_WREDC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10 0x00980248 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING10__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2TR 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2TR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_LTLTR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_LTLTR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_LTL7TR 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_LTL7TR_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_MRD 22:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_MRD_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS_MSB2 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS_MSB2_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_REFTR 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_REFTR_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_REFTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING10_REFTR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2TR_MSB 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2TR_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS_MSB 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING10_WCK2MRS_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11 0x0098024C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING11__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING11_ADZ 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING11_ADZ_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11_WTR_RCD 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING11_WTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11_WTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_WTR_RCD_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTR_RCD 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING11_LTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTR_RCD_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTRTR 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING11_LTRTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTRTR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11_LTRTR_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_KO 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING11_KO_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING11_KO_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING11_KO_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING12 0x00980250 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING12__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING12_RDCRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING12_RDCRC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING12_CKE 9:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING12_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING12_CKE_5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING12_CKSRE 13:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING12_CKSRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING12_CKSRE_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING12_LOCKPLL 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING12_LOCKPLL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING12_LOCKPLL_3000 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING12_LOCKPLL_MAX 0x00003FFF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13 0x00980254 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING13__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK_5 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK_MSB 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASREX2CLK_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD_MSB 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX_MSB 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD_120 0x00000078 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2NRD__PROD_C_SAMSUNG_DDR3 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX_5K 0x00001388 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX_MAX 0x0000FFFF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING13_ASR2ASREX__PROD_C_SAMSUNG_DDR3 0x00004E20 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING14 0x00980258 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING14__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING14_ZQCS 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING14_ZQCS_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING14_ZQCL 17:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING14_ZQCL_100 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING15 0x0098025C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING15__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING15_RDRET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING15_RDRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING15_WRRET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING15_WRRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING15_RDINTRP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING15_RDINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING15_WRINTRP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING15_WRINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING16 0x00980260 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING16__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING16_RDFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING16_RDFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING16_WRFLUSH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING16_WRFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING16_RP 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING16_RP_10 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING16_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING16_RP_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING16_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING16_WCK_QRST 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING16_WCK_QRST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING17 0x00980264 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING17__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING17_RDRET_PRE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING17_RDRET_PRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING17_WCK2RDWCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING17_WCK2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING17_MRS2RDWCK 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING17_MRS2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING18 0x00980268 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING18__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING18_WRCRCFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING18_WRCRCFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING18_REXT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING18_REXT_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING18_QUSE_SETTLE 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING18_QUSE_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING18_DLCELL_SETTLE 29:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING18_DLCELL_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING19 0x0098026C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING19__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING19_QRST_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING19_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING19_QRST_FLUSH 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING19_QRST_FLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING19_MPRR 16:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING19_MPRR_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING20 0x0098028C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING20__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING20_RD_REFRESH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING20_RD_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING20_WR_REFRESH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING20_WR_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21 0x00980390 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING21__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_FORCE_FULL 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_FORCE_FULL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_FORCE_FULL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DUAL_REQUEST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DUAL_REQUEST_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DUAL_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DELAYED_THRESHOLD 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DELAYED_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_FULL_REF_PERIOD 19:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_FULL_REF_PERIOD_INIT 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DISPATCH_PERIOD 31:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING21_REFSB_DISPATCH_PERIOD_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING22 0x00980394 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING22__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBA_INIT 0x00000032 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBR 17:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBR_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBA_MSB 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING22_RFCSBA_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23 0x0098039C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING23__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING23_CCDR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING23_CCDR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23_CCDR_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING23_RD_RANK_SEL_DELAY 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING23_RD_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_RANK_SEL_DELAY 17:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING23_WR_CCDS_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24 0x009803E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING24__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING24_RRDL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING24_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING24_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24_RRDL_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24_CCDMW 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING24_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING24_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24_CCDMW_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING24_LPDDR4_RDV_OFFSET 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING24_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING24_ABPA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING24_ABPA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING24_XS_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING24_XS_OFFSET_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING25 0x009803EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING25__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING25_ZQCAL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING25_ZQCAL_1_US 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING25_MRRW 21:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING25_MRRW_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING25_MRRWL 30:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING25_MRRWL_256 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING26 0x009824E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING26__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING26_RFC_DLR 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING26_RFC_DLR_58 0x0000003A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING26_RFC_DLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING26_RFC_DLR_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING27 0x009824E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING27__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING27_REFSR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING27_REFSR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING27_REFSR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING28 0x009824E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING28__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING28_WRIDON 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING28_WRIDON_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING28_WRIDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING28_WRIDOFF_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING28_NOP2QPOP 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING28_NOP2QPOP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING28_NOP2MRS 22:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING28_NOP2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING28_TKO2MRS 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING28_TKO2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING29 0x009824EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING29__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING29_TDCC1 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING29_TDCC1_INIT 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING29_TDCC2 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING29_TDCC2_INIT 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING30 0x009824FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING30__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_INIT 0x0000013C /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_GDDR6 0x0000013C /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_SDDR4 0x00000278 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_HBM2 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING30_FBIO_CKE_CKOFF_SKEW 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING30_FBIO_CKE_CKOFF_SKEW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TIMING31 0x009824F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TIMING31__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING31_XSMRS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TIMING31_XSMRS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_0 0x009824F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_POWER_0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRUP_RD_INTERP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRUP_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRDN_RD_INTERP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRDN_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRUP_WR_INTERP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRUP_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRDN_WR_INTERP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_0_OFFSET_PWRDN_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_1 0x009824F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_POWER_1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRUP_RCVR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRUP_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRDN_RCVR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRDN_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRUP_RX_CLK 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRUP_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRDN_RX_CLK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_POWER_1_OFFSET_PWRDN_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0 0x00982300 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_DELAY_REF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_DELAY_REF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_BLCG_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL0_BLCG_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1 0x00982304 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2 0x00982308 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3 0x0098230C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4 0x00982310 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5 0x00982314 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6 0x00982318 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7 0x0098231C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0 0x00982320 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_STALL_DELAY 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_STALL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_INV_BW_EVAL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_INV_BW_EVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_EN_WCKTR 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_EN_WCKTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_CHECK_DISPLAY_OK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL0_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1 0x00982324 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2 0x00982328 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3 0x0098232C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4 0x00982330 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5 0x00982334 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6 0x00982338 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7 0x0098233C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACPD_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL 0x00982444 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DQR_CTRL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_PERIOD 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_SET 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_SET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_CLR 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_CLR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC0_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC0_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC1_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_CTRL_EN_IC1_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP0 0x009824C0 /* R--4R */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP1 0x009824C4 /* R--4R */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC0_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP0 0x009824C8 /* R--4R */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP1 0x009824CC /* R--4R */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_DQ_IC1_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD 0x009824D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC0_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DQR_STATUS_VLD_IC1_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CONFIG0 0x00980290 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG0_RC 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RC_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RFC 16:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RFC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RAS 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RAS_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG0_RP_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RP_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_USE_TIMING_REGS 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG0_USE_TIMING_REGS_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_USE_TIMING_REGS_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG0_USE_TIMING_REGS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG0_USE_TIMING_REGS_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1 0x00980294 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG1_CL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG1_CL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG1_CL_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_CL_MAX 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WL 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG1_WL_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WL_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WL_MAX 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_RD_RCD 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG1_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG1_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_RD_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WR_RCD 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG1_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_WR_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_HBM_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_G6_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_G6_HS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_G6X_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG1_QPOP_OFFSET_G6X_HS 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2 0x00980298 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG2_RPRE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_RPRE_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WPRE 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WPRE_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_CDLR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_CDLR_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_CDLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_CDLR_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_WR_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WR_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_WR_MAX 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_W2R_BUS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_W2R_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_W2R_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_W2R_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_R2W_BUS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG2_R2W_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG2_R2W_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG2_R2W_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3 0x0098029C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEX_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEN2PDEX 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_FAW 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_FAW_40 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_FAW_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_AOND 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_AOND_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_AOND_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_AOND_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_AOND_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDL_MAX 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG3_CCDS_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4 0x009802A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO_1F 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO_MIN 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO_3_9_US 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_LO_7_8_US 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH 14:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_11 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_MAX 0x00000FFF /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_3_9_US 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH_7_8_US 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_REFRESH__PROD_C_SAMSUNG_DDR3 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_RRD 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG4_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG4_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_RRD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_DDR5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_DDR5X 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_DDR6 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_HBM 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_SDDR4 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY__PROD_C_LEGACY 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_IDLE_DELAY_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC 31:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_18 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_26 0x0000001A /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5X 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6X 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_HBM 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_SDDR4 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_LEGACY 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG5 0x009802A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG5_ADR_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_ADR_MIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRCRC 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRCRC_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRCRC_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRCRC_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG5_QSAFE_OFFSET 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_QSAFE_OFFSET_39 0x00000027 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_INTRP_MSB 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_INTRP_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_RDRET_OFFSET 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_RDRET_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRRET_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_WRRET_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG5_INTRP 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG5_INTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6 0x009802A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG6_RDFLUSH_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_RDFLUSH_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_WRFLUSH_OFFSET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_WRFLUSH_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG6_WDAT_LATENCY 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_WDAT_LATENCY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_PPD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_PPD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_SDDR4_RDV_OFFSET 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_SDDR4_RDV_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD_ADJUST 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD_ADJUST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG6_CMD_ADJUST_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG7 0x009802AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG7_ZQCS_INTERVAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG7_ZQCS_INTERVAL_64 0x0061A800 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG7_ZQCS_INTERVAL_128 0x00C35000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG8 0x009802CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG8__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG8_ATR_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG8_ATR_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG8_ATR_PADDING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG8_ATR_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG8_ODT_PADDING 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG8_ODT_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG8_WCK2PH 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG8_WCK2PH_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG8_MRSTWCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG8_MRSTWCK_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9 0x009802E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG9__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG9_QUSE_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_QUSE_OFFSET_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9_QUSE_DDLL_SETTLE 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_QUSE_DDLL_SETTLE_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9_REXT_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_REXT_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9_DLCELL_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_DLCELL_SETTLE_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9_QRST_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG9_MPRR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG9_MPRR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10 0x009802F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG10__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG10_RFC_MSB 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_RFC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_PDEN2PDEX_MSB 6:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_PDEN2PDEX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_RD_RCD_MSB 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_RD_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_WR_RCD_MSB 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_WR_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_SDDR4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_IDLE_DELAY_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG10_RDRET_OFFSET_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG10_RDRET_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11 0x009803E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG11__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG11_RRDL 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_RRDL_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_CCDMW 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_CCDMW_MAX 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_MTA 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_MTA_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_MTA_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_WPOST 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_LPDDR4_RDV_OFFSET 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_WEXT_OFFSET 22:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_WEXT_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_RPRE_TOGGLE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_RPRE_TOGGLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG11_RPRE_TOGGLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_RD_RANK_SEL_DELAY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_RD_RANK_SEL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG11_WR_RANK_SEL_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG11_WR_RANK_SEL_DELAY_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG12 0x0098015C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFIG12__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFIG12_BLDIV 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG12_BLDIV_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG12_ADR_TERM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG12_ADR_TERM_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG12_ADR_TERM_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFIG12_ADRTR_FIFO_MARGIN 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG12_ADRTR_FIFO_MARGIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG12_CABI_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFIG12_CABI_MODE_DC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFIG12_CABI_MODE_AC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN 0x009802B0 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RC 8:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RFC 22:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RFC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RAS 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING0_GEN_RAS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN 0x009802B4 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_R2W 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_R2W_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_W2R 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_R2P 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_R2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_W2P 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING1_GEN_W2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN 0x009802B8 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_RD_RCD 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_RD_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_WR_RCD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_WR_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_RRD 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_RRD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_WDV 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING2_GEN_WDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN 0x009802BC /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QUSE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QUSE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QRST 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QSAFE 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_QSAFE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_RDV 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING3_GEN_RDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN 0x009802C0 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEX2WR 5:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEX2WR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEX2RD 13:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEX2RD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEN2PDEX 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEN2PDEX_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_FAW 28:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_FAW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEN2PDEX_MSB 30:29 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING4_GEN_PDEN2PDEX_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN 0x009802C4 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_PCHG2PDEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_PCHG2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_RW2PDEN 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_RW2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_ACT2PDEN 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_ACT2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_AR2PDEN 31:23 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING5_GEN_AR2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN 0x009802C8 /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_PPD 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_PPD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_BUS_W2R 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_BUS_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_CMD2MCIDLE_DRAMC 21:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_CMD2MCIDLE_DRAMC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_CMD2MCIDLE_FBIO 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING6_GEN_CMD2MCIDLE_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN 0x009802D0 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_REXT 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_REXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_WEXT 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_WEXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_ATR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_ATR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_ATRLEN 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING7_GEN_ATRLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN 0x009802D4 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_ODT 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_ODT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_ODTLEN 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_ODTLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_QPOP_OFFSET 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_QPOP_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_RPRE 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_RPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_WPRE 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING8_GEN_WPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN 0x009802D8 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_CCDL 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_CCDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_CCDS 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_CCDS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_ADR 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_ADR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_WCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_WCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_WREDC 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING9_GEN_QPOP_OFFSET_WREDC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN 0x009802DC /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_RDRET 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_RDRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_WRRET 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_WRRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_RDINTRP 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_RDINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_WRINTRP 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING15_GEN_WRINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN 0x009802E0 /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_RDFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_RDFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_WRFLUSH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_WRFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_RP 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_RP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_WCK_QRST 26:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING16_GEN_WCK_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN 0x009802E4 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_RDRET_PRE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_RDRET_PRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_WCK2RDWCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_WCK2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_MRS2RDWCK 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING17_GEN_MRS2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN 0x009802EC /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_WRCRCFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_WRCRCFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_REXT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_REXT_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_QUSE_SETTLE 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_QUSE_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_DLCELL_SETTLE 29:21 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING18_GEN_DLCELL_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN 0x009802F0 /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_QRST_OFFSET 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_QRST_OFFSET_INIT 0x00000002 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_QRST_FLUSH 9:5 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_QRST_FLUSH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_MPRR 16:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_MPRR_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_REFSB_SUBP0 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_REFSB_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_REFSB_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING19_GEN_REFSB_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN 0x00980288 /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN_RD_REFRESH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN_RD_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN_WR_REFRESH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING20_GEN_WR_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN 0x009803F8 /* R--4R */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBA 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBA_INIT 0x00000032 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBR 17:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBR_INIT 0x00000020 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBA_MSB 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING22_GEN_RFCSBA_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN 0x009803E8 /* R-I4R */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_RRDL 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_RRDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_CCDMW 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_CCDMW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_LPDDR4_RDV_OFFSET 18:15 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_ABPA 25:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_ABPA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_XS_OFFSET 31:26 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TIMING24_GEN_XS_OFFSET_INIT 0x0000000A /* R-I-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET 0x00980158 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PTR_RESET__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PTR_RESET_TESTCMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PTR_RESET_TESTCMD_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_TESTCMD_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_WDATFIFO 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PTR_RESET_WDATFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_WDATFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_EDCFIFO 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PTR_RESET_EDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_EDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RRDATAFIFO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RRDATAFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RRDATAFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RREDCFIFO 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RREDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PTR_RESET_RREDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP 0x00980384 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_EN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_EN_ENABLE_LAT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_RES_THRES 15:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_RES_THRES_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_LAT_THRES 27:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_STALL_WKUP_LAT_THRES_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP 0x009802F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_CNT 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_CNT_5K 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_ENABLE_STD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_ENABLE_STRICT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_ENABLE_TIMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_EN_ENABLE_NISO 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_PIPE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ASR_WAKEUP_PIPE_16 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR 0x009802FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAM_ASR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRPD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRPD_NO_POWERDOWN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRPD_POWERDOWN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRCLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRCLK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ASRCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NOISO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NOISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NOISO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_PREA 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_PREA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_PREA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NO_WCKTR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NO_WCKTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_NO_WCKTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_REF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_REF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_REF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ACPD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ACPD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ACPD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ZQ 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ZQ_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ZQ_CL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_ZQ_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_CHECK_DISPLAY_OK 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAM_ASR_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS 0x00980300 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS__PRIV_LEVEL_MASK 0x00982250 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_HBM_RDBI 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_HBM_WDBI 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR5_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_ADR_GDDR6X_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS 0x00980304 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_ADR_RTT_NOM 10:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT 0x00980308 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS_EXT_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT 0x0098030C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS_EXT_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REF 0x00980310 /* -W-4R */ #define NV_PFB_FBPA_MC_0_REF__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REF_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_REF_CMD_REFRESH 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_REF_CMD_REFRESH_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_0_REF_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_REF_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_0_REF_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_REF_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_0_REF_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_REF_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_REF_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE 0x00980314 /* -W-4R */ #define NV_PFB_FBPA_MC_0_PRE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PRE_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_0_PRE_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_PRE_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_0_PRE_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_PRE_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_0_PRE_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_PRE_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_0_PRE_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_0_NOP 0x00980318 /* -W-4R */ #define NV_PFB_FBPA_MC_0_NOP__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_NOP_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_NOP_CMD_NOP 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_NOP_CMD_NOP_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_SELF_REF 0x0098031C /* RW-4R */ #define NV_PFB_FBPA_MC_0_SELF_REF__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_SELF_REF_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SELF_REF_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SELF_REF_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_SELF_REF_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SELF_REF_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_SELF_REF_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_SELF_REF_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_SELF_REF_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2 0x00980320 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_ADR_CWL 5:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_BA__PROD_C_SAMSUNG_DDR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3 0x00980324 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT 0x00980328 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS2_EXT_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT 0x0098032C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_EMRS3_EXT_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1 0x00980330 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_HBM_WR 4:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_HBM_DRV 7:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_NORMAL 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_FIXED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_40 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_48 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM 5:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_CKE_VAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_RDBI 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_RDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_RDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_MTA 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_MTA_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_MTA_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_WDBI 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_WDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_WDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_PAM4 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_PAM4_PAM4 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_PAM4_GDDR6 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_ABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR6X_CABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET 11:11 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_BA_MRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS1_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2 0x00980334 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_HBM_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_HBM_RL 7:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR5_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR5_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR5_DATA_WCK_TERM_OFFSET 8:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR5_ADDRESS_TERM_OFFSET 11:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF 7:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_ATCSR 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST 11:11 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_NO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_YES 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_BA_MRS 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS2_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3 0x00980338 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_16MS 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_8MS 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_HBM_RAS 5:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_DATA_TERM_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV 3:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING 4:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_RDQS 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_RDQS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_RDQS_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_CA_TERM_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_INFO_VENDOR_ID 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID1 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID2 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM 9:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING 9:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_1X 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_2X 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_ENABLED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_3 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_4 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_ON 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_BA_MRS 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS3_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4 0x0098033C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_BA_MRS 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5 0x00980340 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP1 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP1_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP1_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_PLL_BANDWIDTH 5:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR5_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_RAS_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_ADR_GDDR6X_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_DM 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_DM_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_DM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_WDBI 11:11 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_WDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_WDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RDBI 12:12 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_BA_MRS 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6 0x00980344 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREFD 3:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREFD_EXTERNAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREFD_INTERNAL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE23 7:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE01 11:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7 0x00980348 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_1DB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_2DB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_40 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_48 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_5 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_35 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_2 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_35 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_25 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DCC_HOLD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR5_DCC_RESET 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_DCC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_ADR_GDDR6X_DCC_HOLD 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_BA_MRS 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS7_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8 0x00980354 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_CL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR5_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM 1:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_80 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ 3:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_INV_READ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO 4:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO_RESET 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CA_TO_PROG 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_DIS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_EN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_REFPB 7:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_REFPB_PB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_REFPB_P2B 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6_CATH 3:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6_PLL_RANGE 4:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_ADR_GDDR6_MICRON_PLL_RANGE_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_BA_MRS 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS8_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9 0x00980358 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR5_PRE_EMPHASIS 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK 1:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDM 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDU 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ 6:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_TXEQ_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_ADR_GDDR6X_PIN_SUB_ADDRESS 11:7 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10 0x00982200 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET 3:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT 5:4 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT 7:6 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET_MSB 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM 11:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS10_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11 0x00982204 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS11_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12 0x00982208 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_LSB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_MSB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_PRBS 2:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_PRBS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_PRBS_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK 11:3 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS12_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13 0x0098220C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS13_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14 0x0098035C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR_MICRON_CORE_VOLTAGE 4:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_ADR_MICRON_SUBREG_SELECT 11:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15 0x0098034C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_HBM_IVREF 2:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREA 0:0 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREA_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREA_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREB 1:1 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREB_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_MREB_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_CADT 3:2 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_CADT_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_CADT_RISING 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_CADT_FALLING 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR6X_CADT_CABI 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0 8:8 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1 9:9 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING 10:10 /* ----F */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_BA_MRS 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS15_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16 0x00982210 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS16_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17 0x00982214 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS17_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18 0x00982218 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS18_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19 0x0098221C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS19_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20 0x00982220 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS20_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22 0x00982224 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS22_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23 0x00982228 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS23_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24 0x0098222C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS24_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25 0x00982230 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS25_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32 0x00982234 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS32_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40 0x00982238 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS40_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_MRR 0x0098223C /* RW-4R */ #define NV_PFB_FBPA_MC_0_MRR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_MRR_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MRR_CMD_MRR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MRR_CMD_MRR_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MRR_BA 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MRR_BA_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MRR_RANK 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MRR_RANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MRR_CH 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MRR_CH_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_VLD_SUBP0 10:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_VLD_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_SUBP0 18:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_VLD_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_VLD_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_SUBP1 27:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_MRR_GEN_DATA_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_MPC 0x00982240 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MPC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_MPC_ADR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MPC_ADR_NOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MPC_ADR_START_DQS_OSC 0x0000004b /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_ADR_STOP_DQS_OSC 0x0000004d /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MPC_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MPC_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MPC_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MPC_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MPC_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MPC_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_MPC_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC 0x00980350 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_BANK_SEQ 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_BANK_SEQ_INC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_BANK_SEQ_BG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_NO_TR_ACT_IN_TFAW_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_TR_RW_ALL_BANK 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_TR_RW_ALL_BANK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_TR_RW_ALL_BANK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_IDLE_ON_TR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_IDLE_ON_TR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_IDLE_ON_TR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ACT_HIGH_PRIORITY 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ACT_HIGH_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ACT_HIGH_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_HOLDOFF_WRACT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_HOLDOFF_WRACT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_HOLDOFF_WRACT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_WR_FEEDBACK 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_WR_FEEDBACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_WR_FEEDBACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BG_ENABLE_ON_CCD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BG_ENABLE_ON_CCD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_BG_ENABLE_ON_CCD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ENABLE_RRDL_COUNTER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ENABLE_RRDL_COUNTER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ENABLE_RRDL_COUNTER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_KILL_PEND_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_KILL_PEND_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_KILL_PEND_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_TR_SAFE_SCHED 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_TR_SAFE_SCHED_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ABPA_PER_RANK 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_ABPA_PER_RANK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_MAX_BANK_HITS 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_MAX_BANK_HITS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_MAX_BANK_HITS_MAX 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_PRIORITY 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_PRIORITY_HIGHEST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_PRIORITY_MEDIUM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_PRIORITY_LOWEST 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_GBL_RRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_GBL_RRD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_PBR_GBL_RRD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_CMDQ_ALWAYS_ON 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_CMDQ_ALWAYS_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_CMDQ_ALWAYS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_FORCE_G5_TO_G5X 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_FORCE_G5_TO_G5X_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MISC_DRAMC_FORCE_G5_TO_G5X_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_IC_CTRL 0x00980208 /* RW-4R */ #define NV_PFB_FBPA_MC_0_IC_CTRL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_DIRECTION_SYNC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_DIRECTION_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_DIRECTION_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_SP2DRAMC_FLOP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_IC_CTRL_SP2DRAMC_FLOP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_SP2DRAMC_FLOP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO 0x009823FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO_THRESHOLD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO_STALL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_STALL_CMD_FIFO_STALL_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0 0x00980360 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1 0x00980364 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0 0x00980368 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1 0x0098036C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS9_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0 0x00980370 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1 0x00980374 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS14_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT 0x00980378 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS4_EXT_BA_MRS4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT 0x0098037C /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS5_EXT_BA_MRS5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT 0x00980380 /* RW-4R */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_GENERIC_MRS6_EXT_BA_MRS6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1 0x00980280 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CG1__PRIV_LEVEL_MASK 0x009801B4 /* */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_TRAINING 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_TRAINING_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_TRAINING_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIV 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIV_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_REPLAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_REPLAY_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_REPLAY_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SS2PACMD1 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SS2PACMD1_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SS2PACMD1_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_FABSCAN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_FABSCAN_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_FABSCAN_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIVSYNC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIVSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PRIVSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_6_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_6_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAF2TSUBP 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAF2TSUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAF2TSUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_ILA 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_ILA_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_ILA_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAL 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAL_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_PAL_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_10 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_10_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_10_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_11 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_11_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_11_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_12 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_12_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_12_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_13 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_13_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_13_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_14 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_14_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_14_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_15_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_15_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_16 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_16_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_16_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_17 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_17_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_17_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_18 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_18_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_18_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_19 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_19_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_19_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_20 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_20_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_20_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_21 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_21_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_21_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_22 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_22_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_22_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_23 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_23_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_23_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_24 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_24_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_24_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_25 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_25_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_25_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_26 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_26_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_26_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_27 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_27_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_27_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_28 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_28_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_28_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_29 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_29_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_29_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_30 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_30_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_30_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_31 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_31_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_SPARE_31_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG 31:0 /* ----F */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG_DISABLED 0xFFFFFFFF /* ----V */ #define NV_PFB_FBPA_MC_0_CG1_SLCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_CG2 0x00980284 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CG2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FAB_INTFC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FAB_INTFC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FAB_INTFC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_SUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_SUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_MISC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_MISC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FABRIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_PRI_REG_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_PRI_REG_UPDATE_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_PRI_REG_UPDATE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_CMD_FABRIC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_CMD_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_CMD_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG 5:0 /* ----F */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG_DISABLED 0x0000003F /* ----V */ #define NV_PFB_FBPA_MC_0_CG2_FGCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG 0x00980400 /* RW-4R */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_CHAIN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_CHAIN_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_CHAIN_32 0x0000001f /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_CHAIN_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_LIST_SIZE 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_LIST_SIZE_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_MAX_LIST_SIZE_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_PAGE_SIZE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_PAGE_SIZE_1K 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_PAGE_SIZE_2K 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_SET_SWIZZLE 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG 0x00980410 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_8 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_EVICT_ON_CLEAN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_EVICT_ON_CLEAN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_EVICT_ON_CLEAN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_DISABLE 0x0000007f /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_SET_SWIZZLE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD_3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG 0x00980420 /* RW-4R */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG 0x00980430 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0 0x00980440 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_LATENCY_INTERVAL 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_LATENCY_INTERVAL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_LATENCY_INTERVAL_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LATENCY_OFFSET_F 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_READ_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_WRITE_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1 0x00980444 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_SNAPSHOT_ARB 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_SNAPSHOT_ARB_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_SNAPSHOT_ARB_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2 0x00980448 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_READ_SEC_THRESHOLD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_READ_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_READ_SEC_OFFSET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_READ_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_WRITE_SEC_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG2_WRITE_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3 0x0098046C /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_LATENCY_USES_LTCCLK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG3_LATENCY_USES_LTCCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4 0x009804BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4_READ_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4_READ_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4_WRITE_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG4_WRITE_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5 0x00982580 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6 0x00982584 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7 0x00982588 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG 0x00980450 /* RW-4R */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WRITEPULL_REQ 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WRITEPULL_REQ_IMM 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_WRITEPULL_REQ_WAIT_RWDIR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_USE_DRAMC_BUSY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_USE_DRAMC_BUSY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_USE_DRAMC_BUSY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_NOLIMIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_PRIORITY 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_PRIORITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_PRIORITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB_NOLIMIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_DELAY 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_DELAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_WRITE_ARB_CFG_CCDMW_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG 0x00980454 /* RW-4R */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_POLICY 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READ_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG 0x00980460 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_RD_SUBPACKETS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_RD_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_RESNAP_DURING_TURN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_RESNAP_DURING_TURN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_RESNAP_DURING_TURN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SNAP_BASED_ON_VC 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SNAP_BASED_ON_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SNAP_BASED_ON_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_WR_SUBPACKETS 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_WR_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_BGSEC 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_BGSEC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_BGSEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_BANKQ_ENTRIES 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_BANKQ_ENTRIES_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MAX_SKIP_COUNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MAX_SKIP_COUNT_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM_6 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_PER_VC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_PER_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_PER_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_MODE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG_SKIP_CNT_MODE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1 0x00980464 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_ACTARB_CMD_DELAY_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_ACTARB_FIFO_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG1_ACTARB_FIFO_DELAY_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2 0x00980468 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE 25:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE 30:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG3 0x009804C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG3_IC_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG3_IC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG3_IC_MODE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4 0x009804D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH 0x009804D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR5 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR5 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MIN 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_MIN_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FIFO_DEPTH_ASYNC_CMDQ_TYPE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW 0x009804D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_ACPD_ASR 0x00980458 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_ACPD_ASR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR 0x009804DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0 0x009804F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1 0x009804F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2 0x009804F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR 0x009804FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WR 0x009804E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_WR_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC0 0x009804E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC0_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC0_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1 0x009804E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_UTIL_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_ECC 0x0098045C /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_ECC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_ECC_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC1_ECC_UTIL_INIT 0x00000555 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC2 0x009804EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC2_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_VC2_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ACPD 0x009804B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ACPD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ACPD_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ACPD_UTIL_INIT 0x000000CC /* RWI-V */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ASR 0x0098044C /* RW-4R */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ASR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ASR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BW_TRACKER_ASR_UTIL_INIT 0x00000199 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL 0x00980470 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL__PRIV_LEVEL_MASK 0x00980170 /* */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_MASTER_EN 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_MASTER_EN_ENABLED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_MASTER_EN_DISABLED 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_INCLUDE_ADDR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_INCLUDE_ADDR_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_INCLUDE_ADDR_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL_OFF 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_WRITE_KILL_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_EN 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_SIDEBAND_EN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_SIDEBAND_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_SIDEBAND_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR_MODE 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_OFF 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR_MODE_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0 17:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR0_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_WRITE_KILL_PTR1_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL 0x00980474 /* RW-4R */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_SEC_INTR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_SEC_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_SEC_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_DED_INTR_EN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_DED_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_DED_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_POISON_INTR_EN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_POISON_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_POISON_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_ADDRERR_INTR_EN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_ADDRERR_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_0_ECC_INTR_CTRL_ADDRERR_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS(i) (0x00980478+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ECC_STATUS__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_INTR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_INTR 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_POISON_INTR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_POISON_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_POISON_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_POISON_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_INTR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_COUNTER_OVERFLOW 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_SEC_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_COUNTER_OVERFLOW 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_DED_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_0_ECC_SEC_COUNT(i) (0x00980480+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ECC_SEC_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_SEC_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_SEC_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_DED_COUNT(i) (0x00980488+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ECC_DED_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_DED_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_DED_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG(i) (0x00980490+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_0_ECC_DIAG__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_TYPE 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_TYPE_SEC 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_TYPE_DED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_TYPE_POISON 0x2 /* R---V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_DED 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_DED_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_SEC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_SEC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_POISON 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_POISON_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_SECBIT 16:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_DIAG_SECBIT_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR(i) (0x00980498+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR__PRIV_LEVEL_MASK 0x00980170 /* */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_COL 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_COL_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_PC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_PC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_ROW 26:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_ROW_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_BANK 30:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_BANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXTBANK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXTBANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXT(i) (0x009824B8+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXT__PRIV_LEVEL_MASK 0x00980170 /* */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXT_SID 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ERR_INJECTION_ADDR_EXT_SID_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR(i) (0x009804A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT(i) (0x009804A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2(i) (0x00982498+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED(i) (0x00982448+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_DED_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED(i) (0x00982450+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_DED_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_DED(i) (0x009824A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_DED_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_DED_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC(i) (0x00982458+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_SEC_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC(i) (0x00982460+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_SEC_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SEC(i) (0x009824A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SEC_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_SEC_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON(i) (0x00982468+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_POISON_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON(i) (0x00982470+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_POISON_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_POISON(i) (0x009824B0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_POISON_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT2_POISON_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR(i) (0x00982480+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_ADDRERR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR(i) (0x00982488+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_SID 22:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDR_EXT_ADDRERR_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_0_ECC_ADDRERR_COUNT(i) (0x00982490+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_ECC_ADDRERR_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_ECC_ADDRERR_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ECC_ADDRERR_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE 0x009804B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_OVERRIDE 4+4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_OVERRIDE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BANK_SWIZZLE_OVERRIDE_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION 0x009804B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR 10:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER 0x009804C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_READS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_READS_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_READS_24 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_READS_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_RW 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_RW_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_RW_28 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_LTC_BANDWIDTH_LIMITER_RW_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO 0x009804C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_INIT 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_INIT_VAL 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET 13:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_READSCHEDULE_FIFO 0x009804CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_READSCHEDULE_FIFO__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_READSCHEDULE_FIFO_DEPTH_LIMIT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_READSCHEDULE_FIFO_DEPTH_LIMIT_FULL 0x000001FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL 0x00980500 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE 5:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_MRS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_REFRESH 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_SELFREFRESH_ENTRY 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_POWERSTATE_EXIT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_POWERDOWN_ENTRY 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_PRECHARGE 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_PRECHARGE_ALL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_ACTIVATE 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_WRITE 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_WRITE_AUTOPRE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_WRITE_ANY 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_READ 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_READ_AUTOPRE 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_READ_ANY 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_CACHE_MGMT_OP_PENDING 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_LDFF 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_RDTR 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_WRTR 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_ZQCL 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_ZQCS 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_REPLAY 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_REPLAY_START 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_READ_TRAINING 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_WRITE_TRAINING 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_MRR 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_MPC 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_REFSB 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_STEP 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_SEQUENCE 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_ADR 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_WCK 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_RD 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_WR 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_QUSE 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_MODE 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_TRAINING_PERIODIC 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_CHAR_WRITE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_CHAR_READ 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_CHAR_ERROR 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_CHAR_ERROR_ANY 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_MASKED_PW 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_PAIRED_RW 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH0 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH0_SW 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_UNPAIRED_CH1_SW 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_EDC_RD_ERR 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_EDC_WR_ERR 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_STATE_DQR 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_BASE_DELAY 12:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_BASE_DELAY_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_BASE_DELAY_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_LENGTH 23:20 /* RWIUF */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_LENGTH_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_LENGTH_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_INV 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_INV_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_INV_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_EN 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRIGGER_CNTRL_TRIGGER_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAP0 0x0098050C /* R--4R */ #define NV_PFB_FBPA_MC_0_CAP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CAP0_FABRIC_PRESENT 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CAP0_FABRIC_PRESENT_YES 0x00000001 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CAP0_FABRIC_PRESENT_NO 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_CAP0_ECC_PRESENT 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CAP0_ECC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CAP0_ECC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CAP0_EDC_PRESENT 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CAP0_EDC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CAP0_EDC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CAP0_REPLAY_PRESENT 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CAP0_REPLAY_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CAP0_REPLAY_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_PARITY 0x00980510 /* RW-4R */ #define NV_PFB_FBPA_MC_0_PARITY__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_DATALO 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_DATALO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_DATAHI 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_DATAHI_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_CMD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_PARITY_IB_FABRIC_ERROR_CMD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_PARITY_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_PARITY_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PARITY_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00980554 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT0 0x00980514 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT0__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT0_INTERCEPT 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT0_INTERCEPT_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT0_1 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT0_1_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT0_2 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT0_2_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT1 0x00980518 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT1__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT1_3 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT1_3_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT1_4 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT1_4_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT1_5 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT1_5_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT2 0x0098051C /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT2__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT2_6 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT2_6_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT2_7 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT2_7_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT2_8 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT2_8_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT3 0x00980520 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT3__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT3_9 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT3_9_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT3_10 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT3_10_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT3_11 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT3_11_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT4 0x00980524 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT4__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT4_12 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT4_12_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT4_13 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT4_13_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT4_14 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT4_14_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT5 0x00980528 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA_WT5__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_WT5_15 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT5_15_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA_WT5_16 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_BA_WT5_16_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_BA 0x00980550 /* RW-4R */ #define NV_PFB_FBPA_MC_0_BA__PRIV_LEVEL_MASK 0x00980554 /* */ #define NV_PFB_FBPA_MC_0_BA_BLKACTIVITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_BA_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_BA_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_BA_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_RD 0x00980558 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_RD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_RD_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_RD_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_RD_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_RD_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_RD_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_WR 0x0098055C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_WR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_WR_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_WR_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_WR_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_WR_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_WR_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER 0x00980560 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_STATUS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_STATUS_NO_ERROR 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_STATUS_ERROR 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_NUM 6:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_NUM_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_MODE_CONTINUOUS 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_MODE_ONCE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_MASK_SUBP0 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_MASK_SUBP0_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_MASK_SUBP1 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_TRIGGER_BYTE_MASK_SUBP1_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DATA0 0x00980564 /* R--4R */ #define NV_PFB_FBPA_MC_0_CRC_DATA0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_DATA0_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_DATA0_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DATA1 0x00980568 /* R--4R */ #define NV_PFB_FBPA_MC_0_CRC_DATA1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_DATA1_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_DATA1_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DATA2 0x0098056C /* R--4R */ #define NV_PFB_FBPA_MC_0_CRC_DATA2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_DATA 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_EXPECTED_EDC 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_EXPECTED_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_ACTUAL_EDC 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_DATA2_ACTUAL_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE 0x00980570 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_LIMIT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_LIMIT_1000 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_EXCEEDED 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_EXCEEDED_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_EXCEEDED_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_EXCEEDED_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_TICK_CLOCK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_TICK_CLOCK_LTCCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_RATE_TICK_CLOCK_MEMREF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_TICK 0x00980574 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_TICK__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_TICK_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_TICK_VALUE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_TICK_VALUE_1US 0x000002EE /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_MAX_DELTA 0x00980578 /* R--4R */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_MAX_DELTA__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_MAX_DELTA_VALUE 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_MAX_DELTA_VALUE_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0 0x009800D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1 0x009800D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0 0x009800D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1 0x009800DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC 0x00980580 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_DURING_RETRY 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_DURING_RETRY_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_DURING_RETRY_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_DURING_RETRY_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT 0x00980584 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_CNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_CNT_16384 0x00004000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_CNT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_CNT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_DELTA 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_DELTA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_MAX_DELTA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_ERR_ON_RETRY 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_ERR_ON_RETRY_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_CRC_INTERRUPT_EN_ERR_ON_RETRY_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG 0x00980588 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_ERR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_ERR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_RPL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_RPL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP0_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_ERR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_ERR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_RPL 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_RPL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_CRC_DEBUG_SUBP1_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_RD_BYTE(i) (0x00982400+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_RD_BYTE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_RD_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_RD_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_WR_BYTE(i) (0x00982420+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_WR_BYTE__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_WR_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CRC_ERROR_COUNT_WR_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG 0x00982440 /* RWI4R */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_MAXRETRY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_MAXRETRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_SUBP0_SKIPCNT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_SUBP0_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_SUBP1_SKIPCNT 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_REPLAY_DEBUG_SUBP1_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR(i) (0x009824D4+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_1ST 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_1ST 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_1ST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_1ST 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_2ND 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_2ND 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_2ND 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_2ND 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_RDAT3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_1ST 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_1ST 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_1ST 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_1ST 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_2ND 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_2ND 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_2ND 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_2ND 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_RR_FIFOERR_EDC3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_REFCTRL3 0x009824DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFCTRL3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR_SRC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR_SRC_DRAMC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_PBR2ABR_SRC_PWRM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_THRESHOLD 20:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_THRESHOLD_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_SPEEDUP 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_SPEEDUP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFCTRL3_SOFTKILLPBR_SPEEDUP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY 0x0098058C /* RW-4R */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY_MAX 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY_MAX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY_LAST 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_ISO_LATENCY_LAST_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS 0x00980398 /* R--4R */ #define NV_PFB_FBPA_MC_0_INTR_STATUS__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP0 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP0 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP0 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP0 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP0 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP1 16:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_SEC_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP1 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_DED_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_OOR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_POISON_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP1 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_ADDRERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP1 24:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_INTR_STATUS_AERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_OOR 0x009803A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_OOR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_OOR_COUNT_SUBP0 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_OOR_COUNT_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP0_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_OOR_COUNT_SUBP1 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_OOR_COUNT_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP1 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_OOR_RESET_COUNT_SUBP1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP0 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP1 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_0_OOR_INTR_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_OOR_INTR_ENABLE_OFF 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_OOR_INTR_ENABLE_ON 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0 0x0098038C /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CFG0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK_BANK 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK_BANK_8 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_DUAL_RANK_BANK_16 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SCHED_PC_LIMIT 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SCHED_PC_LIMIT_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SCHED_PC_LIMIT_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_OVR 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_VAL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID1_VAL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID1_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CFG0_SID1_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG 0x009803A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_SECCNT_ARB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_SECCNT_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_SECCNT_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_MIN_BG_SECTORS 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_MIN_BG_SECTORS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_RESIDUAL_THRESHOLD 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG_RESIDUAL_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1 0x009803A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_RD_RANK_DURATION 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_RD_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_RD_RANK_MIN_STAY 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_RD_RANK_MIN_STAY_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_WR_RANK_DURATION 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_ARB_CFG1_WR_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR 0x009803AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_DQ(i) (0x00000000 + (i)) /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_DQ__SIZE_1 128 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_ECC(i) (0x00000090 + (i)) /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_ECC__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_DBI(i) (0x00000080 + (i)) /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PIN_DBI__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PC 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PC_PC0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PC_PC1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_PC_PC01 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_DBI 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_DBI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_ECC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x009803B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x009803B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x009803B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x009803BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x009803C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x009803C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x009803C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x009803CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI 0x009803D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC 0x009803D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MAX 0x009803D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MAX__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MAX_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_MAX_V_INIT 0xFFFFFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_THRESHOLD 0x009803DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_THRESHOLD__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_THRESHOLD_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_HBM_CHAR_COUNTER_THRESHOLD_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_RR_CTRL 0x009803FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_RR_CTRL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_RR_CTRL_PC_NPC_GAP 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_CTRL_PC_NPC_GAP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_RR_CTRL_RW_GAP 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_RR_CTRL_RW_GAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK 0x009808FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST 0x00980590 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_SDDR23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_DDR3 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MODE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MODE_LATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MODE_EARLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_EYE_MASK 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_EYE_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_EYE_MASK_LOWER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_EYE_MASK_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_EYE_MASK_UPPER 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GENERIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GENERIC2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_BGA136 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_SDDR3_BGA100 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_GT215_COMP 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR1 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_X8 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR_X8 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_SDDR4_BGA78 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_HBM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_SDDR4_3DS 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_USE_EXTENDED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_MODE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_SUBP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_GEARDOWN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_GEARDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_2T_CMD_GEARDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_G5X_CMD_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_G5X_CMD_MODE_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_G5X_CMD_MODE_G5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_MODE 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL 22:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_LOW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_PAM4_RX_RCV_SEL_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_OB_FABRIC_DBI 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_OB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_OB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_IB_FABRIC_DBI 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_IB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_IB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_LPDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_1 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_2 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_IC 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_4 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6X_BGA180_MODE_1 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_90D 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_270D 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI 0x00980594 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_ON 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_MODE_SSO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_OUT_MODE_LP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_IN_ON 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_IN_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG_DBI_IN_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CHANNELCFG 0x00980598 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CHANNELCFG__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CHANNELCFG_CHANNEL_ENABLE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CHANNELCFG_CHANNEL_ENABLE_32_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CHANNELCFG_CHANNEL_ENABLE_64_BIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1 0x0098059C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_INTERP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_INTERP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_INTERP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RCVR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RCVR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RCVR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RX_CLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RX_CLK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BROADCAST1_POWER_EN_RX_CLK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5 0x00980604 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_CMD_PAD_DISABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_CMD_PAD_DISABLE_NOT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_CMD_PAD_DISABLE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V1P2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V1P8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V2P1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_VDDP_MODE_V2P4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_ATDAT_FORCE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_ATDAT_FORCE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_ATDAT_FORCE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_PU40_MODE_CMD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_PU40_MODE_CMD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CONFIG5_PU40_MODE_CMD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE 0x0098060C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE__PROD_C_DDR1 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE__PROD_C_DDR2 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE__PROD_C_DDR3 0x00300001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE__PROD_C_DDR4 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE__PROD_C_DDR5 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_DELAYED_CALDRV_SDDR 1:1 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE 4:4 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_FORCE_MA_SDR 7:7 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_FORCE_MA_SDR_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_FORCE_MA_SDR_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_PAD_CALIBRATION 11:11 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_PAD_CALIBRATION_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_PAD_CALIBRATION_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_SERIALIZER 12:12 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_SERIALIZER_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_SERIALIZER_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_EN 25:25 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_EN_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_EN_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB 26:26 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV 27:27 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE_VALUE_CLK_OBS_CLK_SEL 29:28 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN 0x00980610 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN 0x00980614 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR 0x0098061C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_ASR__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VAUXC 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VCLAMP 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VAUXP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VAUXC 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VCLAMP 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ASR_BRICK_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL 0x00980670 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_FILTER_BITS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_FILTER_BITS_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_START_TRM 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_START_TRM_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_END_COUNT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_END_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_LEGACY_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_LEGACY_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_IGNORE_START 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_CALIBRATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS 0x00980674 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS 0x00980678 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL 0x0098067C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DLCELL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DLCELL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_MDDLL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_WDQS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL 0x00980694 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP0_ADR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP0_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP1_ADR0 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP1_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL 0x00980698 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL 0x0098069C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL 0x009806A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL 0x009806A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL 0x009806A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL 0x009806AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL 0x009806B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL 0x009806B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL 0x009806B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL 0x009806BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1 0x00980ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1 0x00980EDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE 0x00980700 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_BYTE_VREF_MODE_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL 0x00980704 /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_IB 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_IB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_OB 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_OB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_DQDQS 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_DQDQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_QUSE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_DDLL_QUSE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC 0x00980708 /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_MODE 1:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE 3:2 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_DAT 6:4 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_DAT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_DQS 10:8 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_VREF_DQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT 20:16 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1 0x0098070C /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x00980710 /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x00980714 /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3 0x00980718 /* -W-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE 2:0 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE 5:3 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE 8:6 /* -WIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK 0x00980650 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_PREDI 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_PREDI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK0_ON 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK0_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK0_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK1_ON 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK1_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK1_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK_RUN 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_CLK_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_POLARITY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_POLARITY_NORMAL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK_POLARITY_INVERT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY 0x0098065C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DELAY_PRIV_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY 0x009808E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DELAY_CMD_PRIV_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER 0x009808E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER_PATTERN 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER_PATTERN_INIT 0x33330F0F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_QDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_DDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6x 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK 0x0098066C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_TX_DRVDN 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_TX_DRVUP 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_E_PU40 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_E_PU40_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_E_PU40_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_FREEZE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL 0x00980504 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CFG_DRVDLY 31:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CFG_DRVDLY_A 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB 0x00980508 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB__PRIV_LEVEL_MASK 0x00980168 /* */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_1CYCLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_2CYCLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_3CYCLE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_4CYCLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_SEL_TRNG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_SEL_CAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_TRNG_ARB_SKIP_CNT_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR 0x00980720 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVR_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF 0x00980724 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVF_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT 0x00980728 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_DRVT_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR 0x00980730 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_SLWR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS 0x00980738 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVF 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVF_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVF_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVF_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_BYP_CS_DRVF_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0 0x009807D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD0_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD0_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD0_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD1_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD1_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD1_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD2_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD2_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD2_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD3_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD3_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD3_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD4_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD4_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD4_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD5_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD5_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD5_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD6_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD6_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD6_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD7_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD7_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD7_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD8_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD8_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD8_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD9_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD9_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD9_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD10_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD10_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD10_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD11_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD11_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD11_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD12_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD12_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD12_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD13_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD13_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD13_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD14_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD14_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD14_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD15_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD15_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL0_CMD15_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1 0x009807D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD16_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD16_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD16_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD17_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD17_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD17_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD18_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD18_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD18_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD19_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD19_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD19_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD20_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD20_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD20_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD21_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD21_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD21_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD22_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD22_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD22_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD23_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD23_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD23_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD24_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD24_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD24_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD25_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD25_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD25_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD26_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD26_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD26_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD27_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD27_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD27_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD28_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD28_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD28_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD29_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD29_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD29_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD30_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD30_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD30_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD31_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD31_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL1_CMD31_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2 0x009807D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD32 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD32_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD32_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD32_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD33 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD33_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD33_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD33_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD34 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD34_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD34_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD34_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD35 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD35_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD35_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD35_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD36 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD36_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD36_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD36_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD37 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD37_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD37_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD37_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD38 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD38_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD38_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD38_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD39 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD39_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD39_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD39_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD40 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD40_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD40_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD40_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD41 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD41_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD41_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD41_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD42 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD42_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD42_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD42_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD43 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD43_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD43_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD43_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD44 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD44_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD44_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD44_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD45 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD45_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD45_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD45_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD46 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD46_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD46_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD46_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD47 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD47_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD47_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL2_CMD47_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3 0x009807E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD48 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD48_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD48_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD48_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD49 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD49_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD49_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD49_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD50 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD50_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD50_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD50_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD51 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD51_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD51_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD51_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD52 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD52_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD52_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD52_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD53 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD53_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD53_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD53_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD54 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD54_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD54_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD54_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD55 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD55_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD55_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_CAL_ADR_DRV_SEL3_CMD55_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG 0x009807E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CMD_STEP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CMD_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CMD_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CK_STEP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_CK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_WCK_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_WCK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_WCK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_BGCAL_FREEZE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CALCFG_BGCAL_FREEZE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x00981EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x00981ECC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x00981ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x00981ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x00981ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x00981EDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x00981EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x00981EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x00981EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x00981EEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x00981EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x00981EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x00981EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x00981EFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x00981F00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x00981F04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x00981F08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x00981F0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x00981F10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x00981F14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x00981F18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x00981F1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x00981F20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x00981F24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK 0x00981F28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DRVDN_BYP_SEL_INI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML 0x00981F34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_CLK_VML_SEL_VML 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK 0x00981F2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML 0x00981F38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_SEL_CML 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CAL_WCK_VML_SEL_VML 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG 0x00980000 /* RWE4R */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_DLY_CNT__PROD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG1 0x00980004 /* RWE4R */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_0_PRI_FBPA_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8 0x00980800 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU__PROD_C_DDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_ENABLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT 2:2 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG8_RFU_RDQS_RCVR_SEL_XOR 5:4 /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10 0x00980808 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_DQ 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_RDQS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_RDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_RDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_WDQS 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_CMD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPD_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_DQ 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_RDQS 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_RDQS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_RDQS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_WDQS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WKPU_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_DQ_TERM_MODE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_DQ_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_DQ_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_DQ_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_DQ_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_TERM_MODE 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WDQS_TERM_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_WDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_RDQS_DIFF_MODE 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_RDQS_DIFF_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_RDQS_DIFF_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_SRC_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_SRC_SEL_RDQS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_RDQS_SRC_SEL_WDQS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_INTERNAL_VREF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_INTERNAL_VREF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG10_E_INTERNAL_VREF_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BRLSHFT 0x00980820 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BRLSHFT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BRLSHFT_CMD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BRLSHFT_CMD_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD 0x00980824 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD__PRIV_LEVEL_MASK 0x0098086C /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CML_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CML_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CML_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_PWRD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_TX_PWRD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_ON 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CLK_TX_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CLK_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CLK_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCK_TX_PWRD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCK_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCKB_TX_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCKB_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DIFFAMP_PWRD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DIFFAMP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DIFFAMP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11 0x00980828 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11__PRIV_LEVEL_MASK 0x0098086C /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_S_MACRO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_D_MACRO 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_S_PAD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_D_PAD 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_LOOPBK_MODE_I_PAD 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CK_DEEPLOOP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_E_LPBK_INTERFACE_MODE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_E_LPBK_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_E_LP_MODE_CMD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_E_LP_MODE_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_WCK_DEEPLOOP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_WCK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_VEND_ID_C0_LOAD_EN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_VEND_ID_C0_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_VEND_ID_C1_LOAD_EN 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_VEND_ID_C1_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_PARALLEL_LPBK_MODE_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_PARALLEL_LPBK_MODE_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CLAMP_VAL 23:23 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CLAMP_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CONFIG_CMD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG11_CONFIG_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12 0x0098082C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PVT_CODE_BYTE_C0_RB 10:8 /* R--VF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PVT_CODE_BYTE_C1_RB 13:11 /* R--VF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_INTRP_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_INTRP_8UI_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_INTRP_8UI_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP16 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_STEP1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CYA_SELECT_NO_STEP 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_TX_EN_EARLY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_TX_EN_EARLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_TAPERED_START 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_TAPERED_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_WCK_TAPERED_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CAP 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_INTERP_CAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_CMD_BR8_DELAY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_CMD_BR8_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_CMD_BR8_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG12_CMD_BR8_DELAY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1 0x00980830 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_FBIO_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPRE_TWO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPRE_TWO_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPRE_TWO_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPOST 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPREPOST_DQ_VALUE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPREPOST_DQ_VALUE_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WPREPOST_DQ_VALUE_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WDQS_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WDQS_MODE_WDQS_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_WDQS_MODE_WDQS_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_HOLD_DQ 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_HOLD_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_SETUP_DQ 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_SETUP_DQ_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_SETUP_STR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_EN_SETUP_STR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_CMD_BRLSHFT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_CMD_BRLSHFT_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_CMD_BRLSHFT_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_ON 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_SHORT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_NORMAL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_LONG 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_QUSE_FORCE_HIGH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_QUSE_FORCE_HIGH_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_QUSE_FORCE_HIGH_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_BIT2 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_EXTENDED_QUSE_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_PADMACRO_SYNC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_PADMACRO_SYNC_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_PADMACRO_SYNC_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_RCV_CLOCKING 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_RCV_CLOCKING_STROBE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_RCV_CLOCKING_CONTINUOUS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_CLK_ASSERT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_CLK_ASSERT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_TX_CLK_ASSERT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RUN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RESET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_PADMACRO_RESET 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_PADMACRO_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_INTERP_RESET 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_INTERP_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_DDLL_INIT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_DDLL_INIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG1_DDLL_INIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE2 0x00980834 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE2_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SPARE2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C0 0x00980838 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C0_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C0_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C1 0x0098083C /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C1_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VEND_ID_C1_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK 0x00980860 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_DLY_CK0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_DLY_CK0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_DLY_CK1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_DLY_CK1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMOS_CLK_SEL_CMOS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK 0x00980864 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK 0x00980868 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL 0x00980870 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_RCV_CTRL_LANE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7 0x00980874 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7_CMD_RCV_CTRL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7_CMD_RCV_CTRL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7_CMD_OB_SYNC_DLY 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG7_CMD_OB_SYNC_DLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL 0x00980890 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL__PRIV_LEVEL_MASK 0x0098086C /* */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_OB_BYTE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_BYTE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_CMD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WCK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_TRAINING_PRIV 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_TRAINING_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_BLCG_BYTE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL 0x00980894 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_31 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 29:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1 0x00980898 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CG 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_DQ_DISABLE_ASR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_DQ_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_DISABLE_ASR 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_WCK_DISABLE_ASR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_WCK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CK_DISABLE_ASR 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L 0x009808C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H 0x009808CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL 0x009808D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK0_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK0_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK0_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK0_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK1 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK1_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK1_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK1_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CLK_CTRL_CLK1_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM 0x009808D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM_BYTE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM_BYTE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM_CMD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_LOOPBK_TRIM_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY 0x009808D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE1 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE2 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE2 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE2_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE3 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE3 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE3_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE4 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE4 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE4_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE5 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE5 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE5_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE6 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE6 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE6_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE7 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ENABLE_LANE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE7 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_PARITY_ERROR_LANE7_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY 0x009808DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PARITY_ERR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PARITY_ERR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG 0x00980E00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE_CML 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_ENABLE_CML_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_READY 16:16 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_LOCK 17:17 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSA 24:24 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSD 25:25 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_CML 26:26 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_CML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_4PHCML 27:27 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_4PHCML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_DLL 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_DLL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_600 29:29 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_600_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_600_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_PLL_600_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF 0x00980E04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_NDIV_INIT 0x00000014 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_NDIV_MIN 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_SEL_DIVBY2 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_SEL_DIVBY2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_SEL_DIVBY2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_COEFF_SEL_DIVBY2_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL 0x00980E08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_PLL_FREQLOCK 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_PLL_FREQLOCK_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_PLL_FREQLOCK_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_PLL_FREQLOCK_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_MON_TESTOUT 31:29 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_MON_TESTOUT_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_ENABLE_BG 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG2 0x00980E0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS 0x00980E14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_READY 0:0 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK 1:1 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK 2:2 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_READY 3:3 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK 4:4 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK 5:5 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_READY 6:6 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK 7:7 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK 8:8 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_READY 9:9 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK 10:10 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK 11:11 /* R-IUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_SETUP2 19:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_DUAL_STATUS_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3 0x00980E18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DEBUG_DLL 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DEBUG_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_KCP_DLL 9:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_KCP_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DELAYGAIN 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DELAYGAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_BYPASS_ASYNC 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_BYPASS_ASYNC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DLL_ENABLE 14:14 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_DLL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_SEL_DLLCLK 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_SEL_DLLCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_TESTSEL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_TESTSEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_SPEEDUP 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_SPEEDUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_TESTEN 29:29 /* RWIUF */ #define NV_PFB_FBPA_MC_0_DRAMPLL_CFG3_TESTEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG 0x00980E20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_SYNC_MODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENB_LCKDET_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_ENB_LCKDET_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_READY 16:16 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_LOCK 17:17 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSA 24:24 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSD 25:25 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_CML 26:26 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_4PHCML 27:27 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_DLL 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_PLL_600 29:29 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF 0x00980E24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_NDIV_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_NDIV_MIN 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL 0x00980E28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_MON_TESTOUT 31:29 /* R--UF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2 0x00980E2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SDM 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SSC 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SSC_BYP 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SSC_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SSC_BYP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SSC_BYP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SDM_RESET 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER2 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER2_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SSD_EN_DITHER2_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0 0x00980E30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0_SDM_SSC_STEP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0_SDM_DIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD0_SDM_DIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1 0x00980E34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1_SDM_SSC_MAX 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1_SDM_SSC_MIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_REFMPLL_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK 0x00982030 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x00982034 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_GSP_SEC2_IFF_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK 0x00982038 /* RW-4R */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR(i) (0x00980900+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_ROW 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_EXTBANK 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_EXTBANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_BANK 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD(i) (0x00980910+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD__PRIV_LEVEL_MASK 0x00982038 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_ADR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WCK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WCK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WR 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE_PRIME 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE_PRIME_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_QUSE_PRIME_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CHAR_ENGINE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CHAR_ENGINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CHAR_ENGINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_PERIODIC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RW_LEVEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RW_LEVEL_BYTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_RW_LEVEL_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STROBE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STROBE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STROBE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CONTROL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CONTROL_TRIMMER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CONTROL_DLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CONTROL_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_CONTROL_DLCELL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STEP 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_STEP_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_GO 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CMD_GO_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_TRAINING_DP(i) (0x00980918+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DP__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_LO 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_LO_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_HI 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_HI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD(i) (0x00980920+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_DBI 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_DBI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_EDC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_EDC_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_SEL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_SEL_RD 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_SEL_WR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_SEL_LEGACY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DP_CNTD_SEL_CHAR_ENGINE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL(i) (0x009809C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0(i) (0x00980938+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR4 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR4_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR5 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR5_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR6 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR6_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR7 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR7_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ0_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1(i) (0x00980940+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR8 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR8_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR9 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR9_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR10 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR10_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR11 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR11_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR12 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR12_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR13 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR13_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR14 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR14_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR15 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR15_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ1_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2(i) (0x00980948+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR16 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR16_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR17 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR17_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR18 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR18_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR19 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR19_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR20 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR20_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR21 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR21_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR22 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR22_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR23 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR23_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ2_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3(i) (0x00980950+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR24 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR24_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR25 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR25_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR26 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR26_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR27 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR27_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR28 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR28_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR29 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR29_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR30 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR30_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR31 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR31_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_DQ3_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0(i) (0x00980958+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_EDC_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR0 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR1 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR2 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR3 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC0_DBI_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1(i) (0x00980960+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR0 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR0_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR1 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR1_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC0 13:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC0_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC0_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC0_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC1 15:14 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC1_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC1_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC1_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR2 25:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR2_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR3 27:26 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_ERR3_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC2 29:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC2_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC2_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC2_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC3 31:30 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC3_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC3_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_DEBUG_MISC1_WCK_EDC3_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR(i) (0x00980968+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ADR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ADR_ACT_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ADR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_DP 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_DP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_DP_TRAIN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_DP_CHAR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ACT_ADR 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ACT_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATTERN_PTR_ACT_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING 0x00980970 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_ADRTRM_SETTLE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_ADRTRM_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_ADRTRM_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_ADRTRM_FLUSH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_ADRTRM_FLUSH_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_VREF_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_VREF_SETTLE_INIT 0x0000006E /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_INTRPLTR_SETTLE 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_INTRPLTR_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING_INTRPLTR_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2 0x009809C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2_PRIV_DELAY 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2_PRIV_DELAY_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2_APPLY_DELAY 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING2_APPLY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING3 0x00982050 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING3_TVREFD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TIMING3_TVREFD_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL 0x00982054 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_MIN_INIT 0x00000038 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_MAX_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS 0x00980974 /* R--4R */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP0_STATUS 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP0_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP0_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP0_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP0_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP1_STATUS 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP1_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP1_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP1_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_STATUS_SUBP1_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL 0x00980978 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FAST_UPDATES 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FAST_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FAST_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASR_FAST_EXIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASR_FAST_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASR_FAST_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_DELAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_DELAY_2UI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_DELAY_4UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASYNC_UPDATES 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASYNC_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_ASYNC_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DFE_OVERRIDE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DFE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE_CLEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_EXTENDED_RW_OFFSET 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_EXTENDED_RW_OFFSET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_EXTENDED_RW_OFFSET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_G5X_EDC_TR_MODE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_G5X_EDC_TR_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_G5X_EDC_TR_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_VREF_TRAINING 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_VREF_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_VREF_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_TRAINING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_TRIMMER_TRAINING 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_TRIMMER_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_TRIMMER_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_STOP_CLOCKS 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_STOP_CLOCKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_STOP_CLOCKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_EARLY_FLIP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_EARLY_FLIP_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_EARLY_FLIP_DIABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_STALL_CMDQ 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_STALL_CMDQ_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_STALL_CMDQ_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_QUICK 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DOUBLE_CORS_RANGE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DOUBLE_CORS_RANGE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_DOUBLE_CORS_RANGE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_RD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_WR 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_FIRST_PARTIAL_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_PADS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_PADS_FOUR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_WCK_PADS_EIGHT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL 0x0098097C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_START_WAIT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_START_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_START_EN_WAIT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_START_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_START_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_FINISH_WAIT 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_FINISH_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_REFRESH 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_REFRESH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_REFRESH_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_WAIT_IDLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_WAIT_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_LEGACY_CTRL_WAIT_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2 0x00982040 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_SWEEP_PHASE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_SWEEP_PHASE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_SWEEP_PHASE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_USE_BL16 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_USE_BL16_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_USE_BL16_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_WR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_SHIFT_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_CORS_STEP_OVERRIDE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_WR 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_RD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_INV_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_RD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_WR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_PI_OFFSET_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_DCC 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_DCC_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_DCC_HOLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_DCC_TRACK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_QUICK_WCK 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_QUICK_WCK_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_QUICK_WCK_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_8UI_MODE_G6 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL2_WCK_8UI_MODE_G6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL 0x00982070 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_BS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_BS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_BS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_CORS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_CORS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALT_CORS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALF_FBPA 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALF_FBPA_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_HALF_FBPA_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_RX_CAPTURE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_RX_CAPTURE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_RX_CAPTURE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_BS_FOR_CA_TR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_MISC_CTRL_BS_FOR_CA_TR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG 0x00980A00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_TAG 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_TAG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL_ALWAYS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_BYTE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_DOUBLE_BYTE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_STORE_OPTIMAL_GREATER_DRAM 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_FIRST_TAG 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_FIRST_TAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_FIRST_TAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_TAG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM 0x00980A04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_CHAR_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_CHAR_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_CHAR_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_CHAR_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_CHAR_MAX_MAX 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_BURST_CNT 22:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_BURST_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_INV_EN 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_INV_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_INV_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_PATTERN_LEN 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS7 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS11 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS23 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_DUAL_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_DUAL_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_DUAL_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_ACCESS_UPPER32 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_ACCESS_UPPER32_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_ACCESS_UPPER32_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_USE_RESET_LAST 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_USE_RESET_LAST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_USE_RESET_LAST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_OVERRIDE_TRAINING 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_OVERRIDE_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_OVERRIDE_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT 0x00980AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_RD 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_WR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_PERIODIC_RD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_PERIODIC_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_PERIODIC_WR 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT_PERIODIC_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2 0x00980AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2_ADDR_START 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2_ADDR_START_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2_ADDR_END 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_SELECT2_ADDR_END_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER 0x00980A08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MAX 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_THRESHOLD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x00980AC0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x00980AC8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x00980AD0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL 0x00980A0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_MODE_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_MODE_SWEEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_SWEEP_START 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_SWEEP_START_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_SWEEP_START_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_START_COUNT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_START_COUNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_START_COUNT_ACCUMULATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_STOP_ON_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_REFRESH 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_AFTER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_ALWAYS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_NUM_BANKS 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_NUM_BANKS_1 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_NUM_BANKS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_FUNC_MTA 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_FUNC_MTA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_FUNC_MTA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_DBI_THRESHOLD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_DBI_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_PATTERN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_DATA 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ(i) (0x00000001 + (i)) /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ__SIZE_1 31 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI0 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI1 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI2 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC0 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC3 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC0 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC1 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC2 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC3 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_CTRL_ANALYSIS_PIN_ALL 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST 0x00980A10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST_COUNT_1BANK_LIMIT 0x00000100 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST_COUNT_2BANK_LIMIT 0x00000200 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BURST_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_TURN 0x00980A14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_TURN__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_TURN_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_TURN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_TURN_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL 0x00980A18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_MIN 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_MAX 23:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_INTRPLTR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_DDLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_TRIMMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_INTRPLTR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_TRIMMER 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_DDLL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_TRIMMER 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_DDLL 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_INTRPLTR 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL 0x00980AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_MIN 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_MAX 9:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_MAX_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_MIN 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_MIN_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_MAX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_MAX_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_PREA 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_PREA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_PREA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_RANK 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_A_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_RANK 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_SET_B_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_REFA 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_REFA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL_REFA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2 0x00980ADC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_FOREVER 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL 0x009809CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ADR_SETTING 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ADR_SETTING_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ADR_MAX 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ADR_MAX_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ENABLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_TADR_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL 0x009809D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL 0x009809D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_MIN_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL 0x00980984 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_X8_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_X8_MODE_BOTH 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_X8_MODE_RISING_ONLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_X8_MODE_FALLING_ONLY 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_MIRROR 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_MIRROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_MIRROR_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_MIRROR_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_MIRROR_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_REFRESH 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_REF_CNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_REF_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_1TCK 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_3TCK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_5TCK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_31TCK 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_SKIP_CNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL 0x00980988 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x009809D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX_INIT 0x000000F0 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL 0x009809DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_DDLL_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_TRIMMER_CTRL 0x009809E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_TRIMMER_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_TRIMMER_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x0098098C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x00980A1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_OPTIMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT 0x00980990 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_WCK_EDC_LIMIT_LATE_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL 0x009809F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL 0x009809F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_MIN_INIT 0x000000D8 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL 0x009809FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_BURST_COUNT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_QUSE_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL 0x00980AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_RPT_MODE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_RPT_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL_RPT_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2 0x00980AEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_BURST_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3 0x00980AFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR 0x00980AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_MODE 2:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_MODE_SERIAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_MODE_PARALLEL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_MODE_STAGGER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PATTERN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PATTERN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PATTERN_CUSTOM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DRAM_DEVICE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X16 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DRAM_DEVICE_X32 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PAGE_SELECT 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_0_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_1_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_2_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_READ_ADR_3_MPR3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_RPT_ORDER 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_RPT_ORDER_MPR_RPT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_RPT_ORDER_RPT_MPR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA 0x00980AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR0_DEFAULT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR1_DEFAULT 0x00000033 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR2_DEFAULT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_CTRL_MPR_DATA_MPR3_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL 0x00980994 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL_CMD_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR5_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_DDR3_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR6X_MAX 0x0000000f /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL 0x00980998 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_MAX_INIT 0x00000035 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_STEP_LN 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x009809E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD_INIT 0x00000013 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR_INIT 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL 0x0098099C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL 0x009809A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL 0x009809E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL 0x009809EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL 0x009809A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_TRIMMER_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL 0x009809A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_AREA_BASED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_AREA_BASED_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_QUICK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_VREF_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT 0x009809AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_TRIMMER 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_TRIMMER_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_ERR_LIMIT_TRIMMER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL 0x009809B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_EN_AVG 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL_EN_AVG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL 0x009809F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2 0x009809B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3 0x00982048 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL 0x0098204C /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL 0x00982044 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_AREA_BASED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x00980A20+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x00980A28+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x00980A30+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x00980A38+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x00980A40+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x00980A48+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x00980A50+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x00980A58+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x00980A60+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x00980A68+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x00980A70+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x00980A78+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x00980A80+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x00980A88+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC(i) (0x00980A90+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_IB_MISC_EDC3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x00980A98+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x00980AA0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x00980AA8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x00980AB0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC(i) (0x00980AB8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_RW_OFFSET_OB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_SEED(i) (0x00982000+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_SEED__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_SEED_VAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PATRAM_PRBS_SEED_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL 0x00982060 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_ADDR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_ABI 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_WCK 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_FULL_PERIODIC 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_PHASE 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_PHASE_FINE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_PHASE_CORS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_CTRL_PHASE_BS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_FULL 0x00982064 /* R--4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_FULL__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_FULL_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_FULL_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_PHASE 0x00982068 /* R--4R */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_PHASE__PRIV_LEVEL_MASK 0x00982030 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_PHASE_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_TRAINING_PROFILE_PHASE_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL 0x00982074 /* RW-4R */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL__PRIV_LEVEL_MASK 0x00982034 /* */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_PRBS_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_PRBS_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_TRAINING_ARRAY_CTRL_PRBS_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG 0x00982078 /* RW-4R */ #define NV_PFB_FBPA_MC_0_SW_CONFIG__PRIV_LEVEL_MASK 0x00982034 /* */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PTRIM_OPT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PTRIM_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PTRIM_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_SELFREF_OPT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_SELFREF_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_SELFREF_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_MSCG_OPT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_MSCG_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_MSCG_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_GC6_HIB_OPT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_GC6_HIB_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_GC6_HIB_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PA_FALCON_OPT 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PA_FALCON_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_PA_FALCON_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1 0x0098207C /* RW-4R */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1__PRIV_LEVEL_MASK 0x00982034 /* */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_TRAFFIC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_TRAFFIC_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_TRAFFIC_MANUAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_MANUAL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_MANUAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_ACTIVE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_THROTTLE 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_THROTTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_BANK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG1_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_NOISE_CFG2 0x00982080 /* RW-4R */ #define NV_PFB_FBPA_MC_0_NOISE_CFG2__PRIV_LEVEL_MASK 0x00982034 /* */ #define NV_PFB_FBPA_MC_0_NOISE_CFG2_BURST 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_NOISE_CFG2_BURST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK 0x00980B04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB 0x00980B14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK 0x00980B08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB 0x00980B18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL 0x00980EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CTRL 0x00980B0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CTRL 0x00980B10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET 0x00980B00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_IB 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_IB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_OB 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_OB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_ADDR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_WCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTRPLTR_OFFSET_WCK_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x00980B20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x00980B24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x00980B28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x00980B2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x00980B30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x00980B34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x00980B38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x00980B3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x00980B40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x00980B44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x00980B48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x00980B4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x00980B50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x00980B54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x00980B58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x00980B5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x00980B60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x00980B64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x00980B68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x00980B6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x00980B70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x00980B74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x00980B78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x00980B7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x00980BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x00980BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x00980BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x00980BCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x00980BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x00980BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x00980BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x00980BDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x00980BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x00980BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x00980BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x00980BEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x00980BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x00980BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x00980BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x00980BFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x00980C00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x00980C04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x00980C08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x00980C0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x00980C10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x00980C14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x00980C18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x00980C1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x00980C20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x00980C24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x00980C28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x00980C2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x00980C30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x00980C34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x00980C38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x00980C3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x00980C40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x00980C44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x00980C48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x00980C4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x00980C50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x00980C54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x00980C58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x00980C5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x00980C60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x00980C64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x00980C68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x00980C6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x00980C70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x00980C74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x00980C78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x00980C7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x00980CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x00980CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x00980CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x00980CCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x00980CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x00980CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x00980CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x00980CDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x00980CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x00980CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x00980CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x00980CEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x00980CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x00980CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x00980CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x00980CFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x00980D00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x00980D04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x00980D08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x00980D0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x00980D10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x00980D14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x00980D18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x00980D1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x00980D70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x00980D74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x00980D78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x00980D7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x00980D80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x00980D84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x00980D88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x00980D8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x00980D90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x00980D94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x00980D98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x00980D9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x00980DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x00980DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x00980DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x00980DAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x00980DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x00980DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x00980EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x00980EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD 0x00980D28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DLCELL 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL_RANK1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_LEG_TRIM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD 0x00980D2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL 0x00980D30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_TX_DCC_MODE 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_TX_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_PHASE0_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_PAD_CTRL_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL 0x00980D34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0 0x00980D38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2 0x00980D40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_VREF_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TX_E_DCC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1 0x00980DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2 0x00980DBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1 0x00980DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2 0x00980DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1 0x00980DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2 0x00980DCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1 0x00980DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2 0x00980DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1 0x00980DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2 0x00980DDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1 0x00980DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2 0x00980DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1 0x00980DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2 0x00980DEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1 0x00980DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2 0x00980DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x009805A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x009805A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x009805A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x009805AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x009805B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x009805B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x009805B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x009805BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x009805C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x009805C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x009805C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x009805CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x009805D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x009805D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x009805D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x009805DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x009805E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL 0x009805E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC 27:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC 0x00980D44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_CMD_CONFIG 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_CMD_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_DQ_CONFIG 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_DQ_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_MODE 28:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1 0x00980D48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DFE_CTRL 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_DFE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_RFU 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL 0x00980EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_RX_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL 0x00980EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL 0x00980EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_RX_SUBP0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_RX_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP0 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_RX_SUBP1 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_RX_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP1 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_SUBP1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL 0x00980EBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL 0x00980ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL 0x00980EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL_CLKDIST_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL_CLKDIST_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2 0x00980EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_SPARE 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_IREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_IREF_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CK_IREF_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_WCK_IREF_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_WCK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3 0x00980EEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4 0x00980EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5 0x00980EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_SPARE 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_DQ_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_SPARE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CNTL5_CMD_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL 0x00980EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG 0x00980ECC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_CK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_WCK 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_WCK_PATTERN_MASK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_MISC_CONFIG_WCK_PATTERN_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2 0x00980ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_TX_DRVDN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_TX_DRVUP 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_E_PU40 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_E_PU40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_FREEZE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DELTA_DRVR 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DELTA_DRVF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_FORCE_CAL_UPDATE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CML_CLK2_FORCE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0 0x00981004 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_FBIO_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_LOOPBK_MODE 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_LOOPBK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_TX_EN_SETUP 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_TX_EN_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_BRLSHFT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_BRLSHFT_1UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_DRAM_ECC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_DRAM_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_DRAM_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_LEKAGE_STRENGTH 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG0_LEKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_1 0x00981008 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_1_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_1_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_2 0x0098100C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_2_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_SPARE_2_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL 0x00981010 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_OB_BYTE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_BYTE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL 0x00981014 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG 0x00981018 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_CLK_CNTRL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_NORMAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_CLK_CNTRL_FLIP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY 0x00981020 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY 0x00981024 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x0098103C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x00981040 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x00981044 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x00981048 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x0098104C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x00981050 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x00981054 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x00981058 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x0098105C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x00981060 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x00981064 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x00981068 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x0098106C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x00981070 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x00981074 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x00981078 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x0098107C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x00981080 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x00981084 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x00981088 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x0098108C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x00981090 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x00981094 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x00981098 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x0098109C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x009810A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x003FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x009810A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x000FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x009810A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x009810AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x009810B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x009810B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x009810B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x009810BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x009810C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x009810C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x009810C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE 0x009810CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_TEMP 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG3_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG4_BRICK_SPARE 0x009810D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG4_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG4_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG4_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG5_BRICK_SPARE 0x009810D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG5_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG5_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG5_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x009810D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x009810DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x009810E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x009810E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x009810E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x009810EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x009810F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x009810F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x009810F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x009810FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x00981100 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x00981104 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x00981108 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x0098110C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x00981110 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x00981114 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x00981118 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x0098111C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x00981120 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x00981124 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x00981128 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x0098112C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x00981130 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x00981134 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x00981138 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x0098113C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x00981140 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x00981144 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x00981148 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x0098114C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x00981150 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x00981154 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL 0x00981158 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT 14:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_START_TRM 31:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL_START_TRM_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1 0x009811DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x00981160 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x00981164 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x00981168 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x0098116C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x00981170 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x00981174 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x00981178 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x0098117C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x00981180 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE_INIT 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x00981184 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x00981188 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x0098118C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x00981190 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x00981194 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x00981198 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x0098119C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x009811A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x009811A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG 0x009811A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_FREEZE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_CMD_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_CMD_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_SAMPLE_COUNT 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALCFG_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009811B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009811B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009811BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009811C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009811C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009811C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009811CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009811D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR 0x009811D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x009811D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x009811FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x00981200 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x00981204 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x00981208 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x0098120C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x00981210 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x00981214 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x00981218 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG 0x0098121C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL 15:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0 0x00981224 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM 21:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1 0x00981228 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE1 0x00981030 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE1_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE1_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE2 0x00981034 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE2_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE2_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE3 0x00981038 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE3_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_DONT_USE3_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x009812C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x009812C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x009812CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x009812D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG6_BRICK_SPARE 0x009812D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG6_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE 0x009812D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE 0x009812DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG9_BRICK_SPARE 0x009812F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG9_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE 0x009812E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE 0x009812E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x00981700 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x00981704 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x00981708 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x0098170C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x00981710 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x00981714 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x00981718 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x0098171C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x00981720 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x00981724 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x00981728 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x0098172C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x00981730 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x00981734 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x00981738 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x0098173C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x00981740 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x00981744 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x00981748 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x0098174C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x00981750 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x00981754 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x00981758 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x0098175C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x00981760 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x00981764 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x00981768 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x0098176C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x00981770 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x00981774 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x00981778 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x0098177C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x00981780 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x00981784 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x00981788 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x0098178C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x00981790 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x00981794 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x00981798 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x0098179C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x009817A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x009817A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x009817A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x009817AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x009817B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x009817B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x009817B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x009817BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x009817C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x009817C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x009817C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x009817CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x009817D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x009817D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x009817D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x009817DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x009817E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x009817E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x009817E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x009817EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x009817F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x009817F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x009817F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x009817FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x00981800 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x00981804 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x00981808 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x0098180C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x00981810 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x00981814 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x00981818 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x0098181C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x00981860 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x00981864 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x00981868 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x0098186C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x00981870 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x00981874 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x00981878 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x0098187C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x00981880 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x00981884 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x00981888 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x0098188C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x00981890 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x00981894 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x00981898 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x0098189C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x009818A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x009818A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x009818A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x009818AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x009818B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x009818B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x009818B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x009818BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x009818D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x009818D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x009818D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x009818DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x009818E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x009818E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x009818E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x009818EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x009818F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x009818F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x009818F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x009818FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x00981900 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x00981904 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x00981908 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x0098190C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x00981910 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x00981914 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x00981918 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x0098191C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x00981920 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x00981924 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x00981928 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x0098192C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x00981930 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x00981934 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x00981938 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x0098193C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x00981940 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x00981944 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x00981948 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x0098194C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x00981950 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x00981954 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x00981958 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x0098195C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x00981960 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x00981964 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x00981968 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x0098196C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x00981970 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x00981974 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x00981978 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x0098197C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x00981980 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x00981984 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x00981988 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x0098198C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x00982600 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x00982604 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x00982608 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x0098260C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x00982610 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x00982614 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x00982618 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x0098261C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x00982620 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x00982624 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x00982628 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x0098262C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x00982630 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x00982634 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x00982638 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x0098263C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x00982640 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x00982644 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x00982648 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x0098264C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x00982650 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x00982654 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x00982658 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x0098265C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x00982660 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x00982664 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x00982668 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x0098266C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x00982670 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x00982674 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x00982678 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x0098267C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x00982680 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x00982684 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x00982688 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x0098268C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x00982690 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x00982694 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x00982698 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x0098269C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x009826A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x009826A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x009826A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x009826AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x009826B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x009826B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x009826B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x009826BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x009826C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x009826C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x009826C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x009826CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x009826D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x009826D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x009826D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x009826DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x009826E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x009826E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x009826E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x009826EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x009826F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x009826F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x009826F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x009826FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x00982700 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x00982704 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x00982708 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x0098270C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x00982710 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x00982714 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x00982718 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x0098271C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x00982720 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x00982724 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x00982728 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x0098272C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x00982730 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x00982734 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x00982738 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x0098273C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x00982740 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x00982744 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x00982748 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x0098274C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x00982750 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x00982754 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x00982758 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x0098275C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x00982760 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x00982764 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x00982768 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x0098276C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x00982770 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x00982774 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x00982778 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x0098277C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT 0x009827A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x009827A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT 0x009827A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x009827AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT 0x009827B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_DDLLCAL_LT_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x00981990 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x00981994 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x00981998 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x0098199C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x009819A0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x009819A4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x009819A8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x009819AC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x009819B0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x009819B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x009819B8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x009819BC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x009819C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x009819C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x009819C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x009819CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x009819D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x009819D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x009819D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x009819DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x009819E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x009819E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x009819E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x009819EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x00981FC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x00981FC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x00981FC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x00981FCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x00981FD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x00981FD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x00981FD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x00981FDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x00981FE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x00981FE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x00981FE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x00981FEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x00981FF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x00981FF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x00981FF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x00981FFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x00981820 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x00981824 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x00981828 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x0098182C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x00981830 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x00981834 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x00981838 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x0098183C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL 0x00981A00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_STARTVAL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_STARTVAL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SEL_ODD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SEL_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SEL_VREFU 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_OFFSET_CAL_CTRL_SEL_VREFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_MISC_CTRL 0x00981A04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_MISC_CTRL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x00981A10 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x00981A14 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x00981A18 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x00981A1C /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x00981A20 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x00981A24 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x00981A28 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x00981A2C /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x00981A30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x00981A34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x00981A38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x00981A3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x00981A40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x00981A44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x00981A48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x00981A4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x00981A50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x00981A54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x00981A58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x00981A5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x00981A60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x00981A64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x00981A68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x00981A6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x00981A70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x00981A74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x00981A78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x00981A7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x00981A80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x00981A84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x00981A88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x00981A8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00981A90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00981A94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00981A98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00981A9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00981AA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00981AA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00981AA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00981AAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00981AB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00981AB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00981AB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00981ABC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00981AC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00981AC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00981AC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00981ACC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00981AD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00981AD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00981AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00981ADC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00981AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00981AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00981AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00981AEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00981AF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00981AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00981AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00981AFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00981B00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00981B04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00981B08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00981B0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00981B10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00981B14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00981B18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00981B1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00981B20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00981B24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00981B28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00981B2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00981B30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00981B34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00981B38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00981B3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00981B40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00981B44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00981B48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00981B4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00981B50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00981B54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00981B58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00981B5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00981B60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00981B64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00981B68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00981B6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00981B70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00981B74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00981B78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00981B7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00981B80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00981B84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00981B88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00981B8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00981B90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00981B94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00981B98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00981B9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00981BA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00981BA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00981BA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00981BAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00981BB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00981BB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00981BB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00981BBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00981BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00981BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00981BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00981BCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00981BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00981BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00981BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00981BDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00981BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00981BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00981BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00981BEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00981BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00981BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00981BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00981BFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00981C00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00981C04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00981C08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00981C0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00981C10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00981C14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00981C18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00981C1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00981C20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00981C24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00981C28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00981C2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00981C30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00981C34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00981C38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00981C3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00981C40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00981C44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00981C48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00981C4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00981C50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00981C54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00981C58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00981C5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00981C60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00981C64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00981C68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00981C6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00981C70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00981C74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00981C78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00981C7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00981C80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00981C84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00981C88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00981C8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00981C90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00981C94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00981C98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00981C9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00981CA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00981CA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00981CA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00981CAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00981CB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00981CB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00981CB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00981CBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00981CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00981CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00981CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00981CCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00981CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00981CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00981CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00981CDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00981CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00981CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00981CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00981CEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00981CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00981CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00981CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00981CFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00981D00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00981D04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00981D08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00981D0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00981D10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00981D14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00981D18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00981D1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00981D20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00981D24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00981D28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00981D2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00981D30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00981D34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00981D38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00981D3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00981D40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00981D44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00981D48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00981D4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00981D50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00981D54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00981D58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00981D5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00981D60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00981D64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00981D68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00981D6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00981D70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00981D74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00981D78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00981D7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00981D80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00981D84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00981D88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00981D8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x00981DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x00981DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x00981DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x00981DAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x00981DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x00981DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x00981DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x00981DBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x00981DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x00981DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x00981DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x00981DCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x00981DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x00981DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x00981DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x00981DDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x00981DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x00981DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x00981DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x00981DEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x00981DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x00981DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x00981DF8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x00981DFC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLLCAL 0x00981E00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLLCAL 0x00981E04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLLCAL 0x00981E08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLLCAL 0x00981E0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLLCAL 0x00981E10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLLCAL 0x00981E14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLLCAL 0x00981E18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLLCAL 0x00981E1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF 0x00981E20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLLCAL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF 0x00981E24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF 0x00981E28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF 0x00981E2C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF 0x00981E30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF 0x00981E34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF 0x00981E38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF 0x00981E3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF 0x00981E40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF 0x00981E44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1 0x00981E48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2 0x00981E4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1 0x00981E50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2 0x00981E54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1 0x00981E58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2 0x00981E5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1 0x00981E60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2 0x00981E64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1 0x00981E68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2 0x00981E6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1 0x00981E70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2 0x00981E74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1 0x00981E78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2 0x00981E7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1 0x00981E80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2 0x00981E84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU 0x00981E88 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU 0x00981E8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU 0x00981E90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU 0x00981E94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU 0x00981E98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU 0x00981E9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU 0x00981EA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU 0x00981EA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD 0x00981EA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD 0x00981EAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD 0x00981EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD 0x00981EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD 0x00981EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD 0x00981EBC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD 0x00981EC0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD 0x00981EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT 0x00981F30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_TEMP_COEFF 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_TEMP_COEFF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_IBG_CNTL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_BG_CNTL 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_LV_CDBVAUXC 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_LV_CDBVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_LIMITER 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_CDBVAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BG_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB 0x00981F4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB 0x00981F40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB 0x00981F3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB 0x00981F44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS 0x00981F48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SUBP0_CK 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SUBP1_CK 23:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1 0x00981F50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0 0x00982780 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1 0x00982784 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2 0x00982788 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3 0x0098278C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0 0x00982790 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1 0x00982794 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2 0x00982798 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3 0x0098279C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING 0x00981F54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_RD_GAIN 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_RD_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_WR_GAIN 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_WR_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EDGE_BRLSHFT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EDGE_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_CENTER_BRLSHFT 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_CENTER_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_BLOCK_COUNT 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_BLOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EN 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_HUNT_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_HUNT_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_USE_CENTER_ONLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_USE_CENTER_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_HALF_RATE_EDC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_HALF_RATE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING 0x00981F58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_GAIN 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_ACCUM 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_ACCUM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT 19:11 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW 21:21 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF 28:22 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_VREF_EDGE_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_VREF_EDGE_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2 0x009827B4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_SHADOW_LOAD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_SHADOW_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_SHADOW_SELECT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_SHADOW_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_CDR_MASK 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING2_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1 0x009827B8 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFP_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFP_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFP_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFP_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFN_EVEN 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFN_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFN_ODD 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ1_VREFN_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2 0x009827BC /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x009827C8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x009827CC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x009827D0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x009827D4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x009827D8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x009827DC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x009827E0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x009827E4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x009827E8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x009827EC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x009827F0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x009827F4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x009827F8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x009827FC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x00982800 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x00982804 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG 0x00981F5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT 11:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW 14:14 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DQ_SEL 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DQ_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DIR_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DIR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW 27:27 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW 28:28 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1 0x00981F60 /* R--4R */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI 13:7 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_DQ_PI 20:14 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_DQ_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT 26:21 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x00981F64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x00981F68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x00981F6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x00981F70 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x00981F74 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x00981F78 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x00981F7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x00981F80 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14 0x00981F84 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE1 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE2 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE3 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE4 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE5 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE7 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_EDC_PIN_STATE_BYTE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_FORCE_PIN_STATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CFG14_FORCE_PIN_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC 0x00981F8C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_EN_X 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_EN_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SIGNAL_SEL_X 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SIGNAL_SEL_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_OFFSET_X 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_OFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SELECT_X 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SELECT_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_EN_Y 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_EN_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SIGNAL_SEL_Y 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SIGNAL_SEL_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_OFFSET_Y 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_OFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SELECT_Y 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HSDAC_SELECT_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0 0x009827C0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC0_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1 0x009827C4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_CMD_HSDAC1_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0 0x00981F90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1 0x00981F94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS 0x00981F98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_TERM 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_TERM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI 0x00981F9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_RX 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_TX 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_SPARE 31:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_INTERP_2UI_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x00981FA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x00981FA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x00981FA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x00981FAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x00981FB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x00981FB4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1 0x00981FB8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1__PRIV_LEVEL_MASK 0x009808FC /* */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_CDR_MASK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_SUPPORT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_EDC_TRACKING1_LOCK_SUPPORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK 0x00983C7C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_0_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG 0x00983C90 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SYNCMODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SYNCMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SYNCMODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SYNCMODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_LCKDET 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_LCKDET_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_LCKDET_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_PLL_LOCK 5:5 /* R--UF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_FSTLCK 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_IDDQ 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE_BG 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_BYPASSPLL 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_BYPASSPLL_VCO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_BYPASSPLL_BYPASSCLK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL 0x00983C94 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF 0x00983C98 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_NDIV_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO 0x00983C9C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST 0x00983CA0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RFU 24:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG 0x00983CA4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK 27:21 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG1 0x00983CA8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG1_TX_EN 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_CFG1_TX_EN_INIT 0x00FFD98A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD1 0x00983CAC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD1_TX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD1_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD2 0x00983CB0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD2_RX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_BRICK_TEST_PWRD2_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE 0x00983CCC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG13_BRICK_SPARE 0x00983CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG13_BRICK_SPARE__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG 0x00983CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_INT_VREF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_INT_VREF_INIT 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1 0x00983CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK 7:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK 28:22 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2 0x00983CDC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW 10:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD 12:11 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1 0x00983CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREG14V_CTRL 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREG10V_CTRL 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG1_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0 0x00983CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1 0x00983CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL 6:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_RFU 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_HBMCDB_CFG1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0 0x00983CEC /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU_INIT 0x00000030 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG2 0x00983CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG2_SETUP 27:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBMPLL_CFG2_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG 0x00983C00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN 0x00983C04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX 0x00983C08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL 0x00983C0C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB 0x00983C10 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_RISE_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_FALL_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_TERM 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2 0x00983C14 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_RISE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_FALL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_SPARE 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3 0x00983C18 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4 0x00983C1C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5 0x00983C20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x00983C30 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x00983C34 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x00983C38 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x00983C3C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x00983C40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x00983C44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x00983C48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x00983C4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x00983C50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x00983C54 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x00983C58 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x00983C5C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x00983C60 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x00983C64 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2 0x00983C68 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3 0x00983C6C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG 0x00983D00 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_SYNC_MODE 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL 0x00983D04 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2 0x00983D08 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_SEL_TESTOUT 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_SETUP2 27:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_TESTMODE 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_REFMPLL_CFG2_TESTMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG 0x00983D20 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_CLAMP_P0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL 0x00983D24 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL 31:29 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2 0x00983D28 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2_SETUP2 11:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0 0x00983D40 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_LV_VAUXC 18:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_BW 22:19 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST 30:28 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1 0x00983D44 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CMD_VTT_SPARE 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CMD_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_BYTE_VTT_SPARE 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_BYTE_VTT_SPARE_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VTT_SPARE 21:20 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_CDB_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL 29:22 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL 0x00983D48 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_BG_CNTL 3:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IBG_CNTL 5:4 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IRX_CNTL 7:6 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IRX_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IRX_SRC_SEL 10:8 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IRX_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEMP_COEF 13:11 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_CDB_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_CDB_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_SEL 20:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_E_RES_CAL_CODE_IN 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_E_RES_CAL_CODE_IN_BYP_SEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL 26:22 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IBG_SRC_SEL 29:27 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CDBCTRL_IBG_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV 0x00983D4C /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_SPARE 10:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_PTRIM_OVRD 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_PTRIM_OVRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH 13:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_DRAMPLL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_ONESOURCE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_MODE_SWITCH_REFMPLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_DPD 16:16 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_DPD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_DPD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE 17:17 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL 18:18 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2 0x00983D50 /* RW-4R */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2__PRIV_LEVEL_MASK 0x00983C7C /* */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM 5:3 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM 8:6 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_BGAP_TRIM 11:9 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_BGAP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_E_TRIM 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_E_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXC 16:13 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXC_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXP 20:17 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VAUXP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VCLAMP 24:21 /* RWIUF */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VCLAMP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_0_FBIO_VTT_CTRL2_CDB_VCLAMP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK 0x00984168 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK 0x00984148 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK 0x0098414C /* RW-4R */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK 0x00984170 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_ecc" /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK 0x009841B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK 0x009841B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK 0x00986578 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK 0x0098400C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK 0x00986250 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK 0x0098486C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_SPARE 0x00984050 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SPARE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SPARE_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_INIT 0xFF001040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_OFIFO_OFFSET 5:0 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_OFIFO_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_CMDFF_DEPTH 12:8 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_CMDFF_DEPTH_INIT 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_CMDFF_DEPTH_MAX 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_CMDFF_DEPTH_SAFE 0x00000004 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_SYNC_PULSE_POLARITY 13:13 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_SYNC_PULSE_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_OFIFO_OFFSET_POLARITY 14:14 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_OFIFO_OFFSET_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_PDEN_OFFSET 19:16 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_PDEN_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_L2_CRC_MODE 20:20 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_L2_CRC_MODE_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_VS_DELAY 23:21 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_VS_DELAY_INIT 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BIT30 30:30 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BIT30_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BUG765178_TEST_MODE 31:31 /* ----F */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BUG765178_TEST_MODE_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BUG765178_TEST_MODE_SKIP 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE_BITS_BUG765178_TEST_MODE_RUN 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_SPARE2 0x009840CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_SPARE2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SPARE2_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SPARE2_BITS_INIT 0xFFFF0000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FALCON_MONITOR 0x00984054 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FALCON_MONITOR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FALCON_MONITOR_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FALCON_MONITOR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER 0x00984064 /* R--4R */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_DEV 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_ECO 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_MINOR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_MINOR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_MAJOR 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FALCON_CTRL_VER_MAJOR_INIT 0x00000004 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD 0x00984060 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CFG_PWRD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_80 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_120 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_RCVR_PWRD_DLY 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_RCVR_PWRD_DLY_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_BLCG_USE_TRAINING_IDLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_BLCG_USE_TRAINING_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG_PWRD_BLCG_USE_TRAINING_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0 0x00984080 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DEBUG_0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_0_MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_MRS_256 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_MRS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PERIODIC_QRST 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PERIODIC_QRST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PERIODIC_QRST_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_SPARE0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_PIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_PIN_CMD 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_PIN_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_PIN_DEBUG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_MODE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_MODE_WRITE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_ODT_MODE_NOTREAD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_USE_CFG0_BL8_HBM 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_USE_CFG0_BL8_HBM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_USE_CFG0_BL8_HBM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BL16EDC_SET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BL16EDC_SET_EVEN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BL16EDC_SET_ODD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_WFT_IDLE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_WFT_IDLE_NEW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_WFT_IDLE_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FB_IDLE_NOPBR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FB_IDLE_NOPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FB_IDLE_NOPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HANDSHAKE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HANDSHAKE_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HANDSHAKE_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FORCE_FULL_MEMREF 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FORCE_FULL_MEMREF_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_FORCE_FULL_MEMREF_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_R2P_BL_ADJUST 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_R2P_BL_ADJUST_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_R2P_BL_ADJUST_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_POST_SP_TR 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_POST_SP_TR_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_POST_SP_TR_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_TOGGLE_FIX 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_TOGGLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_TOGGLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HWACPDIDLE_FIX 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HWACPDIDLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DISABLE_HWACPDIDLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_MODE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_MODE_SDR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_MODE_DDR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PRI_REG_UPDATE_EXT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PRI_REG_UPDATE_EXT_15 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_PRI_REG_UPDATE_EXT_31 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_REFCFG_REQ_PENDING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_REFCFG_REQ_PENDING_FIXED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_REFCFG_REQ_PENDING_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BECS_ACK 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BECS_ACK_LEVEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_BECS_ACK_PULSE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DRAM_ACK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DRAM_ACK_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_DRAM_ACK_IDLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_TREFI_UPDATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_0_TREFI_UPDATE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_0_TREFI_UPDATE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_1 0x00984084 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DEBUG_1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_1_L2_ECC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_1_L2_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_1_L2_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DEBUG_2 0x00986340 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_2_XBAR_ASR_OK 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_2_XBAR_ASR_OK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_2_XBAR_ASR_WAKEUP 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_2_XBAR_ASR_WAKEUP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_2_STOP_FB_REQ 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_2_STOP_FB_REQ_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_2_STOP_FB_ACK 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_2_STOP_FB_ACK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_SUBPIDLE(i) (0x00986344+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_DEBUG_SUBPIDLE__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_SUBPIDLE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_SUBPIDLE_IDLES 27:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_SUBPIDLE_IDLES_INIT 0x0FFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_PAIDLE 0x0098634C /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_PAIDLE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_PAIDLE_IDLES 21:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_PAIDLE_IDLES_INIT 0x003FFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0 0x00986350 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0_EN_COUNT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0_EN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0_CLR_COUNT 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_0_CLR_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1 0x00986354 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_1 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_2 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_3 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DEBUG_CTRL_1_SEL_3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_BASE 0x00986358 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_BASE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_BASE 0x0098635C /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_BASE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_0 0x00986360 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_0 0x00986364 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_1 0x00986368 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_1 0x0098636C /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_2 0x00986370 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_2 0x00986374 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_3 0x00986378 /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_LO_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_3 0x0098637C /* R--4R */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DEBUG_COUNT_HI_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP 0x009841DC /* R--4R */ #define NV_PFB_FBPA_MC_1_ROW_REMAP__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_ENABLE 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD(i) (0x009841F0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ENTRY_VLD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ENTRY_VLD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ROW 25:9 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ROW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_RD_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR(i) (0x009841F8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR__PRIV_LEVEL_MASK 0x0098400C /* */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_ROW 25:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ROW_REMAP_WR_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD 0x00984090 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TESTCMD__PRIV_LEVEL_MASK 0x0098414C /* */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LPDDR4_SELF_REF_ENTRY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LPDDR4_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CKE_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CS1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_CAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_HBM_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_WE_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_RES_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_4_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR6_SELF_REF_ENTRY1 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR6_SELF_REF_ENTRY2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_BANK_DDR6_SELF_REF_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR 25:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_ADR_UPPER_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_GO_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_HOLD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT 0x00984094 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT__PRIV_LEVEL_MASK 0x0098414C /* */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ADR_DRAM1 10:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ADR_DRAM1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DEBUG 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DEBUG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ODT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ODT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ODT_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_RW_CMD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_RW_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_MRS_CMD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_MRS_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DR_CMD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DR_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_4CK_CMD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_4CK_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_LAM_CMD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_LAM_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_CMD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_SID 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_SID_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1 0x00984154 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1__PRIV_LEVEL_MASK 0x0098414C /* */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_ENTRY 0x00018018 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_EXIT 0x00014014 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0 0x009840A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1 0x009840A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2 0x009840A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3 0x009840AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0 0x009840B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1 0x009840B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2 0x009840B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3 0x009840BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI 0x009840C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_DBI_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC 0x009840C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_ECC_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE 0x009840C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCK01 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCKB01 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCK23 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCKB23 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP0_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCK01 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCKB01 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCK23 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCKB23 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SWIZZLE_BYTE_SUBP1_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM 0x00984100 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PM__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC0 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT0 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT1 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ0 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ2 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC2 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ3 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ4 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ5 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC4 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT4 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT5 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ4 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ6 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRTYREQ7 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC6 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SLC7 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT6 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDAT7 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ6 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READREQ7 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_SUBP0 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_SUBP1 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_CH0_SUBP0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_CH0_SUBP1 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_CH1_SUBP0 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_ACT_CH1_SUBP1 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_BANK_ACT_SUBP0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_BANK_ACT_SUBP1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_NO_ACT_SUBP0 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_NO_ACT_SUBP1 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP0 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP1 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BANKQ_EMPTY_SUBP0 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BANKQ_EMPTY_SUBP1 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BA_OUTPUT 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BA_SIGS 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_CKG0 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_CKG1 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRARB_SUBP0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DIRARB_SUBP1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_BANKS_SUBP0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_BANKS_SUBP1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_EXTRA_SUBP0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_EXTRA_SUBP1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RWALL 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_SUBP0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_SUBP1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_CH0_SUBP0 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_CH0_SUBP1 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_CH1_SUBP0 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RW_CH1_SUBP1 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_SUBP0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_SUBP1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_CH0_SUBP0 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_CH0_SUBP1 0x00000043 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_CH1_SUBP0 0x00000044 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_CH1_SUBP1 0x00000045 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_CH0_SUBP0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_CH0_SUBP1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_CH1_SUBP0 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_CH1_SUBP1 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_PART2_SUBP0 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_PART2_SUBP1 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_PP_SUBP0 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_WAIT_PP_SUBP1 0x0000004D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ECC_CH0_SUBP0 0x0000004E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ECC_CH0_SUBP1 0x0000004F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ECC_CH1_SUBP0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ECC_CH1_SUBP1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_FT_IDLE_SUBP0 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_FT_IDLE_SUBP1 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_CH0_SUBP0 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_CH0_SUBP1 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_CH1_SUBP0 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_CH1_SUBP1 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SUBP0 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_IDLE_SUBP1 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INFLIGHT_READ_COUNT 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INFLIGHT_READ_COUNT_VC0 0x0000005C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INFLIGHT_READ_COUNT_VC1 0x0000005D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INFLIGHT_READ_COUNT_VC2 0x0000005E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_INFLIGHT_WRITE_COUNT 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_OUT_READS 0x00000060 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_OUT_WRITES 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_PENDING_REFRESH_SUBP0 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_PENDING_REFRESH_SUBP1 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_PART2_SUBP0 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_PART2_SUBP1 0x00000065 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_SUBP0 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_SUBP1 0x00000067 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP0 0x00000068 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP1 0x00000069 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP0 0x0000006A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP1 0x0000006B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP0 0x0000006C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP1 0x0000006D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READARB_SUBP0 0x0000006E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READARB_SUBP1 0x0000006F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_READARB_VC 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_REFSB_SUBP0 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_REFSB_SUBP1 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT0_PART2_SUBP0 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT0_PART2_SUBP1 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT0_SUBP0 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT0_SUBP1 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT1_PART2_SUBP0 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT1_PART2_SUBP1 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT1_SUBP0 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RFT1_SUBP1 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_STAT_CH0_SUBP0 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_STAT_CH0_SUBP1 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_STAT_CH1_SUBP0 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_STAT_CH1_SUBP1 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_SINGLE_PASS_SUBP0 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_SINGLE_PASS_SUBP1 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_SUBP01_TRAFFIC 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_SUBP01_TRAFFIC_CH0 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_SUBP01_TRAFFIC_CH1 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WFT0_SUBP0 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WFT0_SUBP1 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WFT1_SUBP0 0x00000088 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WFT1_SUBP1 0x00000089 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP0 0x0000008A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP1 0x0000008B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRBANKQ_SUBP0 0x0000008C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRBANKQ_SUBP1 0x0000008D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEARB_SUBP0 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEARB_SUBP1 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_UTIL_SUBP0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_UTIL_SUBP1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RCMD_CH0_SUBP0 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RCMD_CH0_SUBP1 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RCMD_CH1_SUBP0 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_DRAMC_RCMD_CH1_SUBP1 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_SUBP0 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_SUBP1 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_CH0_SUBP0 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_CH0_SUBP1 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_CH1_SUBP0 0x0000009A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BUCKET_CH1_SUBP1 0x0000009B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ISO_TRACKING0_SUBP0 0x0000009C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ISO_TRACKING0_SUBP1 0x0000009D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ISO_TRACKING1_SUBP0 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ISO_TRACKING1_SUBP1 0x0000009F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC0_SUBP0 0x000000A0 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC0_SUBP1 0x000000A1 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC1_SUBP0 0x000000A2 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC1_SUBP1 0x000000A3 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC2_SUBP0 0x000000A4 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_BW_TRACKING_VC2_SUBP1 0x000000A5 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_REQ_FIFO_SG0 0x000000A6 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_REQ_FIFO_SG1 0x000000A7 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_REQ_FIFO_SG2 0x000000A8 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_WRITEPULL_REQ_FIFO_SG3 0x000000A9 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_RETURN_FIFO_SG0 0x000000AA /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_RETURN_FIFO_SG1 0x000000AB /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_RETURN_FIFO_SG2 0x000000AC /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_RR_RETURN_FIFO_SG3 0x000000AD /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR0_SUBP0 0x000000AE /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR0_SUBP1 0x000000AF /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR1_SUBP0 0x000000B0 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR1_SUBP1 0x000000B1 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR2_SUBP0 0x000000B2 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR2_SUBP1 0x000000B3 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR3_SUBP0 0x000000B4 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR3_SUBP1 0x000000B5 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR4_SUBP0 0x000000B6 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SELECT_ACPD_ASR4_SUBP1 0x000000B7 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP(i) (0x009841E0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_SUBP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_SUBP__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_SUBP_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_SUBP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_ACT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_ACT_CH0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_ACT_CH1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_BANK_ACT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_NO_ACT 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACTARB_NUM_RW_BANKS 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BANKQ_EMPTY 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DIRARB 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_CH0 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_CH1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_BANKS 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_EXTRA 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_RW 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_RW_CH0 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_RW_CH1 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_WAIT_CH0 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_WAIT_CH1 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_WAIT_PART2 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_WAIT_PP 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ECC_CH0 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ECC_CH1 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_FT_IDLE 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_IDLE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_IDLE_CH0 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_IDLE_CH1 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_PENDING_REFRESH 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RDBANKQ 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RDBANKQ_PART2 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RDBANKQ_VC0_REQ_FIFO 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RDBANKQ_VC1_REQ_FIFO 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RDBANKQ_VC2_REQ_FIFO 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_READARB 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_REFSB 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RFT0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RFT0_PART2 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RFT1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RFT1_PART2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RR_STAT_CH0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_RR_STAT_CH1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_SINGLE_PASS 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WFT0 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WFT1 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WRBANKQ 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WRBANKQ_REQ_FIFO 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WRITEARB 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_WRITEPULL_UTIL 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_RCMD_CH0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_DRAMC_RCMD_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BUCKET 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BUCKET_CH0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BUCKET_CH1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ISO_TRACKING0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ISO_TRACKING1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BW_TRACKING_VC0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BW_TRACKING_VC1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_BW_TRACKING_VC2 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACPD_ASR0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACPD_ASR1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACPD_ASR2 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACPD_ASR3 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_SUBP_SELECT_ACPD_ASR4 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE(i) (0x00984180+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_HI(i) (0x00986500+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_HI__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_HI__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_HI_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_WINDOW(i) (0x009841D0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_WINDOW__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_WINDOW__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_WINDOW_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_WINDOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_CTL 0x009841D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_CTL__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_CTL_INVERT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_CAPTURE_CTL_INVERT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET(i) (0x00986530+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_BUCKET__SIZE_1 11 /* */ #define NV_PFB_FBPA_MC_1_PM_BUCKET__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL 0x0098655C /* RW-4R */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE_RD_CMD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE_WR_CMD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE_COL_CMD 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE_ANY_CMD 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_BUCKET_CTL_TYPE_ISO_TRACKING 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_CTL 0x00986560 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PM_CTL__PRIV_LEVEL_MASK 0x009841B0 /* */ #define NV_PFB_FBPA_MC_1_PM_CTL_ISO_SUBID_MSB_INDEX 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_CTL_ISO_SUBID_MSB_INDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PM_CTL_ISO_SUBID_MSB_INDEX_MAX 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_REG_CTL 0x00986564 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REG_CTL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REG_CTL_FBIO_NOACK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REG_CTL_FBIO_NOACK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REG_CTL_FBIO_NOACK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_ASR_NUM(i) (0x00984110+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_ASR_NUM__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_NUM__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_NUM_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_ASR_NUM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_ASR_CYCCNT(i) (0x00984118+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_ASR_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_CYCCNT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_ASR_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_ASR_MAXCYC(i) (0x00984120+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_PM_ASR_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_MAXCYC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PM_ASR_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_PM_ASR_MINCYC(i) (0x00984128+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_PM_ASR_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_MINCYC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASR_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PM_ASR_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_CYCCNT(i) (0x00984130+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_CYCCNT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MAXCYC(i) (0x00984138+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MAXCYC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MINCYC(i) (0x00984140+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MINCYC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PM_ASRSTALL_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_1_ASRCTRL_NONISO 0x00984150 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASRCTRL_NONISO__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASRCTRL_NONISO_THRESHOLD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASRCTRL_NONISO_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL 0x00984160 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_10 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_11 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_12 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_13 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_14 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_15 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_PERIOD_16 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_EN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_CTRL_INTERVAL_TIMER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_FBPS 0x00984164 /* RW-4R */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_FBPS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_FBPS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_LTCS 0x0098416C /* RW-4R */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NUM_ACTIVE_LTCS_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE0 0x00984174 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPRE0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ0_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ1_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ2_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE0_DQ3_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE1 0x00984178 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPRE1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ4_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ5_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ6_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE1_DQ7_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE2 0x0098417C /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPRE2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPRE2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE2_DBI_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPRE2_TR_PATTERN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPRE2_TR_PATTERN_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST0 0x009841B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPOST0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ0_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ1_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ2_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST0_DQ3_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST1 0x009841BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPOST1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ4_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ5_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ6_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST1_DQ7_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_WPOST2 0x009841C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WPOST2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WPOST2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WPOST2_DBI_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0 0x00984200 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CFG0__PRIV_LEVEL_MASK 0x00986250 /* */ #define NV_PFB_FBPA_MC_1_CFG0_BL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_BL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_BL_BL4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_BL_BL8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_BL_BL16 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_EXTBANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_EXTBANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_EXTBANK_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_EXTBANK__PROD_C_SINGLE_SIDED_MEM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_EXTBANK__PROD_C_DUAL_SIDED_MEM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_X8 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_X8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_X8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_CA_RETURN_TO_ZERO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_CA_RETURN_TO_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_CA_RETURN_TO_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_HBM_CMD_PARITY_OVERRIDE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_HBM_CMD_PARITY_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_HBM_CMD_PARITY_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_RATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_RATE_HALF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_RATE_FULL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_GAPLESS_WTR 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_GAPLESS_WTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_GAPLESS_WTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACPD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACPD_NO_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACPD_ACTIVE_POWERDOWN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ATR__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_DATA_SCRAMBLE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_DATA_SCRAMBLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_DATA_SCRAMBLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_SYNC 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_LOW_POWER 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_LOW_POWER_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_LOW_POWER_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_ABI 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_BURST_LENGTH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_BURST_LENGTH_4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_BURST_LENGTH_8 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_DM_ON_ADR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_DM_ON_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_DM_ON_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_TIMING_UNIT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_TIMING_UNIT_DRAMCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_TIMING_UNIT_DRAMDIV2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_CMD_PARITY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_CMD_PARITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_CMD_PARITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_ODT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_CLAMSHELL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_CLAMSHELL_X32 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_CLAMSHELL_X16 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_EARLY_VALUE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_EARLY_VALUE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_EDC_EARLY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_BG_8 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_BG_8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_BG_8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_PRE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_PRE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_AUTO_PRE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_SAME_QUSE_TWO_RANKS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_SAME_QUSE_TWO_RANKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_SAME_QUSE_TWO_RANKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_RDEDC 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_RDEDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_RDEDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_WREDC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_WREDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_WREDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_REPLAY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_REPLAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_REPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_MS01_ECC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_MS01_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_MS01_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG0_DRAM_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1 0x00984204 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CFG1__PRIV_LEVEL_MASK 0x00984148 /* */ #define NV_PFB_FBPA_MC_1_CFG1_SUBP 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_SUBP_256B 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_SUBP_512B 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_SUBP_1KB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_SUBP_2KB 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_AP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A8 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A12 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_AP_A13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_STACK 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_STACK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_STACK_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_STACK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_COL_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_COL_15 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_ROWB_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_BANK 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_BANK_2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_BANK_3 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_BANK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_BG_8_OVR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_BG_8_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_BG_8_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_BG 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_ROW_BG 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_ROW_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_ROW_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CFG1_NUM_BANKS_PER_ROW_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CSTATUS 0x0098420C /* R--4R */ #define NV_PFB_FBPA_MC_1_CSTATUS__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_RAMAMOUNT 16:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_RAMAMOUNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CSTATUS_OVERRIDE 0x0098657C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CSTATUS_OVERRIDE__PRIV_LEVEL_MASK 0x00986578 /* */ #define NV_PFB_FBPA_MC_1_CSTATUS_OVERRIDE_RAMAMOUNT 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CSTATUS_OVERRIDE_RAMAMOUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL 0x00984210 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFCTRL__PRIV_LEVEL_MASK 0x00986250 /* */ #define NV_PFB_FBPA_MC_1_REFCTRL_PUT 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL_PUT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL_GET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL_GET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL_RESET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL_RESET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL_RESET_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFCTRL_VALID 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL_VALID_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL_VALID_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ 0x00984214 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ZQ__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ZQ_CL_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_CL_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_CS_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_CS_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_CL_PERIODIC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_CL_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_CL_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_CS_PERIODIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_CS_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_CS_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_CH 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_CH_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_CH_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_RANK 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_RANK_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_PERIODIC_RANK_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ZQ_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ZQ_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ZQ_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN 0x00984218 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PIN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PIN_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_DQM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_DQM_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_DQM_INACTIVE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_RESET 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_RESET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_CKE_POLARITY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_CKE_POLARITY_ACTIVE_HI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_CKE_POLARITY_ACTIVE_LO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_A0 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_A0_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_A0_LOW 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_A0_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_WDQS_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_WDQS_MODE_RETURN_TO_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_WDQS_MODE_RETURN_TO_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PIN_WDQS_MODE_FREERUNNING 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_PIN_DBI 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PIN_DBI_X8 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD 0x0098421C /* RW-4R */ #define NV_PFB_FBPA_MC_1_PAD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PAD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_CKE__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_CMD27 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_CMD27_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_CMD27_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_CMD28 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_CMD28_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_CMD28_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_CHANNEL_PULLDN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_CHANNEL_PULLDN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_CHANNEL_PULLDN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_INPUT_DRIVER_CTRL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_INPUT_DRIVER_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_INPUT_DRIVER_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PAD_DBI 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PAD_DBI_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PAD_DBI_OVERRIDE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING 0x009843F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING_ACT2PDEN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING_ACT2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING_ACT2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING_PCHG2PDEN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING_PCHG2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING_PCHG2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING_AR2PDEN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING_AR2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING_AR2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING_DQRQPOP 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING_DQRQPOP_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING_DQRQPOP_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING_NOP2MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING_NOP2MRS_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING_NOP2MRS_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0 0x00984220 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING0_RC 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RFC 22:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RFC_MAX 0x000003FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RAS 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RAS_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1 0x00984224 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2W__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2R 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING1_W2R_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2R_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2R_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2R__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2P 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING1_R2P_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2P_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_R2P__PROD_C_SAMSUNG_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2P 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING1_W2P_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2P_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING1_W2P__PROD_C_SAMSUNG_DDR3 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2 0x00984228 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING2_RD_RCD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING2_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING2_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_RD_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_RD_RCD__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WR_RCD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING2_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING2_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WR_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WR_RCD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_RRD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING2_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING2_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_RRD_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_RRD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV__PROD_C_WL1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV__PROD_C_WL6 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING2_WDV__PROD_C_SAMSUNG_DDR3 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3 0x0098422C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE__PROD_C_CL11 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QUSE__PROD_C_SAMSUNG_DDR3 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST__PROD_C_CL11 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QRST__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QSAFE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING3_QSAFE_17 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING3_QSAFE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_QSAFE_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV_60 0x0000003C /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV_27 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV_MIN 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV_MAX 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV__PROD_C_CL11 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING3_RDV__PROD_C_SAMSUNG_DDR3 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4 0x00984230 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2WR 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2WR_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2WR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2WR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2WR__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2RD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2RD_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2RD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2RD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEX2RD__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW_40 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_FAW__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_MSB 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING4_PDEN2PDEX_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING5 0x00984234 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING5_PCHG2PDEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING5_PCHG2PDEN_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING5_PCHG2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_PCHG2PDEN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_PCHG2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_RW2PDEN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING5_RW2PDEN_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING5_RW2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_RW2PDEN_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_RW2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_ACT2PDEN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING5_ACT2PDEN_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING5_ACT2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_ACT2PDEN_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_ACT2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_AR2PDEN 31:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING5_AR2PDEN_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING5_AR2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_AR2PDEN_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING5_AR2PDEN__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6 0x00984238 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING6_PPD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING6_PPD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING6_BUS_W2R 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING6_BUS_W2R_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING6_BUS_W2R_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_DRAMC 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_DRAMC_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_DRAMC_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO_70 0x00000046 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO_20 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING6_CMD2MCIDLE_FBIO_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING7 0x0098423C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING7_REXT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING7_REXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING7_WEXT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING7_WEXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING7_ATR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATR_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATRLEN 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING7_ATRLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATRLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING7_ATRLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8 0x00984240 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING8__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING8_ODT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING8_ODT_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING8_ODT_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_ODT_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_ODTLEN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING8_ODTLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_ODTLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING8_ODTLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_QPOP_OFFSET 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING8_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_QPOP_OFFSET_ELEVEN 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING8_QPOP_OFFSET_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_RPRE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING8_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING8_RPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_WPRE 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING8_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING8_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING8_WPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING9 0x00984244 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING9__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDL_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING9_CCDS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_ADR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_ADR_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_WCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_WCK_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_WREDC 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING9_QPOP_OFFSET_WREDC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10 0x00984248 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING10__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2TR 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2TR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_LTLTR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_LTLTR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_LTL7TR 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_LTL7TR_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_MRD 22:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_MRD_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS_MSB2 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS_MSB2_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_REFTR 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_REFTR_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_REFTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING10_REFTR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2TR_MSB 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2TR_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS_MSB 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING10_WCK2MRS_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11 0x0098424C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING11__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING11_ADZ 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING11_ADZ_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11_WTR_RCD 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING11_WTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11_WTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_WTR_RCD_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTR_RCD 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING11_LTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTR_RCD_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTRTR 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING11_LTRTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTRTR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11_LTRTR_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_KO 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING11_KO_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING11_KO_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING11_KO_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING12 0x00984250 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING12__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING12_RDCRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING12_RDCRC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING12_CKE 9:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING12_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING12_CKE_5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING12_CKSRE 13:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING12_CKSRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING12_CKSRE_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING12_LOCKPLL 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING12_LOCKPLL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING12_LOCKPLL_3000 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING12_LOCKPLL_MAX 0x00003FFF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13 0x00984254 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING13__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK_5 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK_MSB 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASREX2CLK_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD_MSB 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX_MSB 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD_120 0x00000078 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2NRD__PROD_C_SAMSUNG_DDR3 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX_5K 0x00001388 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX_MAX 0x0000FFFF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING13_ASR2ASREX__PROD_C_SAMSUNG_DDR3 0x00004E20 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING14 0x00984258 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING14__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING14_ZQCS 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING14_ZQCS_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING14_ZQCL 17:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING14_ZQCL_100 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING15 0x0098425C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING15__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING15_RDRET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING15_RDRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING15_WRRET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING15_WRRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING15_RDINTRP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING15_RDINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING15_WRINTRP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING15_WRINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING16 0x00984260 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING16__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING16_RDFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING16_RDFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING16_WRFLUSH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING16_WRFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING16_RP 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING16_RP_10 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING16_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING16_RP_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING16_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING16_WCK_QRST 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING16_WCK_QRST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING17 0x00984264 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING17__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING17_RDRET_PRE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING17_RDRET_PRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING17_WCK2RDWCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING17_WCK2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING17_MRS2RDWCK 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING17_MRS2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING18 0x00984268 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING18__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING18_WRCRCFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING18_WRCRCFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING18_REXT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING18_REXT_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING18_QUSE_SETTLE 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING18_QUSE_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING18_DLCELL_SETTLE 29:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING18_DLCELL_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING19 0x0098426C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING19__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING19_QRST_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING19_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING19_QRST_FLUSH 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING19_QRST_FLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING19_MPRR 16:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING19_MPRR_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING20 0x0098428C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING20__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING20_RD_REFRESH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING20_RD_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING20_WR_REFRESH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING20_WR_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21 0x00984390 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING21__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_FORCE_FULL 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_FORCE_FULL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_FORCE_FULL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DUAL_REQUEST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DUAL_REQUEST_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DUAL_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DELAYED_THRESHOLD 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DELAYED_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_FULL_REF_PERIOD 19:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_FULL_REF_PERIOD_INIT 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DISPATCH_PERIOD 31:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING21_REFSB_DISPATCH_PERIOD_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING22 0x00984394 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING22__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBA_INIT 0x00000032 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBR 17:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBR_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBA_MSB 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING22_RFCSBA_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23 0x0098439C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING23__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING23_CCDR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING23_CCDR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23_CCDR_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING23_RD_RANK_SEL_DELAY 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING23_RD_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_RANK_SEL_DELAY 17:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING23_WR_CCDS_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24 0x009843E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING24__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING24_RRDL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING24_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING24_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24_RRDL_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24_CCDMW 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING24_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING24_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24_CCDMW_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING24_LPDDR4_RDV_OFFSET 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING24_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING24_ABPA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING24_ABPA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING24_XS_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING24_XS_OFFSET_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING25 0x009843EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING25__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING25_ZQCAL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING25_ZQCAL_1_US 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING25_MRRW 21:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING25_MRRW_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING25_MRRWL 30:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING25_MRRWL_256 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING26 0x009864E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING26__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING26_RFC_DLR 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING26_RFC_DLR_58 0x0000003A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING26_RFC_DLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING26_RFC_DLR_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING27 0x009864E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING27__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING27_REFSR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING27_REFSR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING27_REFSR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING28 0x009864E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING28__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING28_WRIDON 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING28_WRIDON_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING28_WRIDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING28_WRIDOFF_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING28_NOP2QPOP 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING28_NOP2QPOP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING28_NOP2MRS 22:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING28_NOP2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING28_TKO2MRS 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING28_TKO2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING29 0x009864EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING29__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING29_TDCC1 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING29_TDCC1_INIT 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING29_TDCC2 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING29_TDCC2_INIT 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING30 0x009864FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING30__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING30_FB_FBIO_DRAM_IDLE_DELAY 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_INIT 0x0000013C /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_GDDR6 0x0000013C /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_SDDR4 0x00000278 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_HBM2 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING30_FBIO_CKE_CKOFF_SKEW 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING30_FBIO_CKE_CKOFF_SKEW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TIMING31 0x009864F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TIMING31__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING31_XSMRS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TIMING31_XSMRS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_0 0x009864F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_POWER_0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRUP_RD_INTERP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRUP_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRDN_RD_INTERP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRDN_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRUP_WR_INTERP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRUP_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRDN_WR_INTERP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_0_OFFSET_PWRDN_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_1 0x009864F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_POWER_1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRUP_RCVR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRUP_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRDN_RCVR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRDN_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRUP_RX_CLK 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRUP_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRDN_RX_CLK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_POWER_1_OFFSET_PWRDN_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0 0x00986300 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_DELAY_REF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_DELAY_REF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_BLCG_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL0_BLCG_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1 0x00986304 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2 0x00986308 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3 0x0098630C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4 0x00986310 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5 0x00986314 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6 0x00986318 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7 0x0098631C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0 0x00986320 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_STALL_DELAY 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_STALL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_INV_BW_EVAL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_INV_BW_EVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_EN_WCKTR 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_EN_WCKTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_CHECK_DISPLAY_OK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL0_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1 0x00986324 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2 0x00986328 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3 0x0098632C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4 0x00986330 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5 0x00986334 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6 0x00986338 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7 0x0098633C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACPD_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL 0x00986444 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DQR_CTRL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_PERIOD 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_SET 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_SET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_CLR 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_CLR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC0_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC0_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC1_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_CTRL_EN_IC1_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP0 0x009864C0 /* R--4R */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP1 0x009864C4 /* R--4R */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC0_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP0 0x009864C8 /* R--4R */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP1 0x009864CC /* R--4R */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_DQ_IC1_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD 0x009864D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC0_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DQR_STATUS_VLD_IC1_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CONFIG0 0x00984290 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG0_RC 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RC_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RFC 16:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RFC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RAS 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RAS_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG0_RP_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RP_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_USE_TIMING_REGS 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG0_USE_TIMING_REGS_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_USE_TIMING_REGS_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG0_USE_TIMING_REGS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG0_USE_TIMING_REGS_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1 0x00984294 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG1_CL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG1_CL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG1_CL_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_CL_MAX 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WL 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG1_WL_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WL_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WL_MAX 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_RD_RCD 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG1_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG1_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_RD_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WR_RCD 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG1_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_WR_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_HBM_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_G6_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_G6_HS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_G6X_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG1_QPOP_OFFSET_G6X_HS 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2 0x00984298 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG2_RPRE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_RPRE_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WPRE 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WPRE_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_CDLR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_CDLR_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_CDLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_CDLR_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_WR_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WR_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_WR_MAX 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_W2R_BUS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_W2R_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_W2R_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_W2R_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_R2W_BUS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG2_R2W_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG2_R2W_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG2_R2W_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3 0x0098429C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEX_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEN2PDEX 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_FAW 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_FAW_40 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_FAW_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_AOND 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_AOND_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_AOND_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_AOND_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_AOND_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDL_MAX 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG3_CCDS_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4 0x009842A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO_1F 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO_MIN 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO_3_9_US 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_LO_7_8_US 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH 14:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_11 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_MAX 0x00000FFF /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_3_9_US 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH_7_8_US 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_REFRESH__PROD_C_SAMSUNG_DDR3 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_RRD 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG4_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG4_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_RRD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_DDR5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_DDR5X 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_DDR6 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_HBM 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_SDDR4 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY__PROD_C_LEGACY 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_IDLE_DELAY_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC 31:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_18 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_26 0x0000001A /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5X 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6X 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_HBM 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_SDDR4 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_LEGACY 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG5 0x009842A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG5_ADR_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_ADR_MIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRCRC 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRCRC_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRCRC_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRCRC_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG5_QSAFE_OFFSET 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_QSAFE_OFFSET_39 0x00000027 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_INTRP_MSB 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_INTRP_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_RDRET_OFFSET 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_RDRET_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRRET_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_WRRET_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG5_INTRP 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG5_INTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6 0x009842A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG6_RDFLUSH_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_RDFLUSH_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_WRFLUSH_OFFSET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_WRFLUSH_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG6_WDAT_LATENCY 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_WDAT_LATENCY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_PPD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_PPD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_SDDR4_RDV_OFFSET 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_SDDR4_RDV_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD_ADJUST 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD_ADJUST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG6_CMD_ADJUST_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG7 0x009842AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG7_ZQCS_INTERVAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG7_ZQCS_INTERVAL_64 0x0061A800 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG7_ZQCS_INTERVAL_128 0x00C35000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG8 0x009842CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG8__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG8_ATR_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG8_ATR_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG8_ATR_PADDING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG8_ATR_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG8_ODT_PADDING 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG8_ODT_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG8_WCK2PH 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG8_WCK2PH_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG8_MRSTWCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG8_MRSTWCK_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9 0x009842E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG9__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG9_QUSE_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_QUSE_OFFSET_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9_QUSE_DDLL_SETTLE 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_QUSE_DDLL_SETTLE_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9_REXT_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_REXT_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9_DLCELL_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_DLCELL_SETTLE_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9_QRST_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG9_MPRR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG9_MPRR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10 0x009842F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG10__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG10_RFC_MSB 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_RFC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_PDEN2PDEX_MSB 6:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_PDEN2PDEX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_RD_RCD_MSB 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_RD_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_WR_RCD_MSB 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_WR_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_SDDR4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_IDLE_DELAY_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG10_RDRET_OFFSET_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG10_RDRET_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11 0x009843E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG11__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG11_RRDL 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_RRDL_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_CCDMW 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_CCDMW_MAX 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_MTA 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_MTA_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_MTA_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_WPOST 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_LPDDR4_RDV_OFFSET 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_WEXT_OFFSET 22:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_WEXT_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_RPRE_TOGGLE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_RPRE_TOGGLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG11_RPRE_TOGGLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_RD_RANK_SEL_DELAY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_RD_RANK_SEL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG11_WR_RANK_SEL_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG11_WR_RANK_SEL_DELAY_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG12 0x0098415C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFIG12__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFIG12_BLDIV 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG12_BLDIV_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG12_ADR_TERM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG12_ADR_TERM_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG12_ADR_TERM_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFIG12_ADRTR_FIFO_MARGIN 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG12_ADRTR_FIFO_MARGIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG12_CABI_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFIG12_CABI_MODE_DC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFIG12_CABI_MODE_AC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN 0x009842B0 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RC 8:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RFC 22:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RFC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RAS 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING0_GEN_RAS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN 0x009842B4 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_R2W 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_R2W_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_W2R 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_R2P 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_R2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_W2P 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING1_GEN_W2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN 0x009842B8 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_RD_RCD 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_RD_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_WR_RCD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_WR_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_RRD 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_RRD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_WDV 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING2_GEN_WDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN 0x009842BC /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QUSE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QUSE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QRST 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QSAFE 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_QSAFE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_RDV 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING3_GEN_RDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN 0x009842C0 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEX2WR 5:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEX2WR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEX2RD 13:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEX2RD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEN2PDEX 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEN2PDEX_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_FAW 28:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_FAW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEN2PDEX_MSB 30:29 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING4_GEN_PDEN2PDEX_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN 0x009842C4 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_PCHG2PDEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_PCHG2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_RW2PDEN 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_RW2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_ACT2PDEN 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_ACT2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_AR2PDEN 31:23 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING5_GEN_AR2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN 0x009842C8 /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_PPD 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_PPD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_BUS_W2R 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_BUS_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_CMD2MCIDLE_DRAMC 21:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_CMD2MCIDLE_DRAMC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_CMD2MCIDLE_FBIO 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING6_GEN_CMD2MCIDLE_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN 0x009842D0 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_REXT 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_REXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_WEXT 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_WEXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_ATR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_ATR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_ATRLEN 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING7_GEN_ATRLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN 0x009842D4 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_ODT 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_ODT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_ODTLEN 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_ODTLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_QPOP_OFFSET 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_QPOP_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_RPRE 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_RPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_WPRE 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING8_GEN_WPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN 0x009842D8 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_CCDL 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_CCDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_CCDS 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_CCDS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_ADR 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_ADR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_WCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_WCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_WREDC 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING9_GEN_QPOP_OFFSET_WREDC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN 0x009842DC /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_RDRET 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_RDRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_WRRET 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_WRRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_RDINTRP 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_RDINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_WRINTRP 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING15_GEN_WRINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN 0x009842E0 /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_RDFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_RDFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_WRFLUSH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_WRFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_RP 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_RP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_WCK_QRST 26:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING16_GEN_WCK_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN 0x009842E4 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_RDRET_PRE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_RDRET_PRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_WCK2RDWCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_WCK2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_MRS2RDWCK 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING17_GEN_MRS2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN 0x009842EC /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_WRCRCFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_WRCRCFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_REXT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_REXT_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_QUSE_SETTLE 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_QUSE_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_DLCELL_SETTLE 29:21 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING18_GEN_DLCELL_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN 0x009842F0 /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_QRST_OFFSET 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_QRST_OFFSET_INIT 0x00000002 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_QRST_FLUSH 9:5 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_QRST_FLUSH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_MPRR 16:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_MPRR_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_REFSB_SUBP0 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_REFSB_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_REFSB_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING19_GEN_REFSB_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN 0x00984288 /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN_RD_REFRESH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN_RD_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN_WR_REFRESH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING20_GEN_WR_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN 0x009843F8 /* R--4R */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBA 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBA_INIT 0x00000032 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBR 17:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBR_INIT 0x00000020 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBA_MSB 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING22_GEN_RFCSBA_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN 0x009843E8 /* R-I4R */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_RRDL 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_RRDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_CCDMW 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_CCDMW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_LPDDR4_RDV_OFFSET 18:15 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_ABPA 25:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_ABPA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_XS_OFFSET 31:26 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TIMING24_GEN_XS_OFFSET_INIT 0x0000000A /* R-I-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET 0x00984158 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PTR_RESET__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PTR_RESET_TESTCMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PTR_RESET_TESTCMD_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_TESTCMD_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_WDATFIFO 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PTR_RESET_WDATFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_WDATFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_EDCFIFO 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PTR_RESET_EDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_EDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RRDATAFIFO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RRDATAFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RRDATAFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RREDCFIFO 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RREDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PTR_RESET_RREDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP 0x00984384 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_EN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_EN_ENABLE_LAT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_RES_THRES 15:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_RES_THRES_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_LAT_THRES 27:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_STALL_WKUP_LAT_THRES_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP 0x009842F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_CNT 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_CNT_5K 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_ENABLE_STD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_ENABLE_STRICT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_ENABLE_TIMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_EN_ENABLE_NISO 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_PIPE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ASR_WAKEUP_PIPE_16 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR 0x009842FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAM_ASR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRPD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRPD_NO_POWERDOWN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRPD_POWERDOWN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRCLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRCLK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ASRCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NOISO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NOISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NOISO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_PREA 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_PREA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_PREA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NO_WCKTR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NO_WCKTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_NO_WCKTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_REF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_REF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_REF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ACPD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ACPD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ACPD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ZQ 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ZQ_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ZQ_CL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_ZQ_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_CHECK_DISPLAY_OK 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAM_ASR_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS 0x00984300 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS__PRIV_LEVEL_MASK 0x00986250 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_HBM_RDBI 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_HBM_WDBI 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR5_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_ADR_GDDR6X_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS 0x00984304 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_ADR_RTT_NOM 10:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT 0x00984308 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS_EXT_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT 0x0098430C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS_EXT_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REF 0x00984310 /* -W-4R */ #define NV_PFB_FBPA_MC_1_REF__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REF_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_REF_CMD_REFRESH 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_REF_CMD_REFRESH_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_1_REF_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_REF_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_1_REF_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_REF_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_1_REF_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_REF_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_REF_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE 0x00984314 /* -W-4R */ #define NV_PFB_FBPA_MC_1_PRE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PRE_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_1_PRE_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_PRE_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_1_PRE_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_PRE_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_1_PRE_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_PRE_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_1_PRE_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_1_NOP 0x00984318 /* -W-4R */ #define NV_PFB_FBPA_MC_1_NOP__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_NOP_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_NOP_CMD_NOP 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_NOP_CMD_NOP_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_SELF_REF 0x0098431C /* RW-4R */ #define NV_PFB_FBPA_MC_1_SELF_REF__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_SELF_REF_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SELF_REF_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SELF_REF_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_SELF_REF_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SELF_REF_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_SELF_REF_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_SELF_REF_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_SELF_REF_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2 0x00984320 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_ADR_CWL 5:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_BA__PROD_C_SAMSUNG_DDR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3 0x00984324 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT 0x00984328 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS2_EXT_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT 0x0098432C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_EMRS3_EXT_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1 0x00984330 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_HBM_WR 4:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_HBM_DRV 7:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_NORMAL 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_FIXED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_40 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_48 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM 5:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_CKE_VAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_RDBI 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_RDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_RDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_MTA 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_MTA_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_MTA_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_WDBI 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_WDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_WDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_PAM4 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_PAM4_PAM4 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_PAM4_GDDR6 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_ABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR6X_CABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL_RESET 11:11 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_BA_MRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS1_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2 0x00984334 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_HBM_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_HBM_RL 7:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR5_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR5_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR5_DATA_WCK_TERM_OFFSET 8:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR5_ADDRESS_TERM_OFFSET 11:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_SELF_REF 7:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_ATCSR 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST 11:11 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_NO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_YES 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_BA_MRS 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS2_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3 0x00984338 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_16MS 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_8MS 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_HBM_RAS 5:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK01_INV 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_DATA_TERM_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK23_INV 3:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING 4:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_RDQS 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_RDQS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_RDQS_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_CA_TERM_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_INFO_VENDOR_ID 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID1 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID2 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK_TERM 9:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING 9:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_1X 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_2X 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_ENABLED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_3 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_4 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_ON 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_BA_MRS 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS3_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4 0x0098433C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_EDC13_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_BA_MRS 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5 0x00984340 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP1 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP1_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP1_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_PLL_BANDWIDTH 5:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR5_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_RAS_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_ADR_GDDR6X_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_DM 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_DM_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_DM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_WDBI 11:11 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_WDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_WDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RDBI 12:12 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_BA_MRS 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6 0x00984344 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_WCKPIN 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREFD 3:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREFD_EXTERNAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREFD_INTERNAL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE23 7:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE01 11:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7 0x00984348 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK_AP 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_1DB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_2DB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_40 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_48 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_5 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_35 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_2 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_35 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_25 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DCC_HOLD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR5_DCC_RESET 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_DCC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_ADR_GDDR6X_DCC_HOLD 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_BA_MRS 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS7_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8 0x00984354 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_CL_EHF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_CL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_CL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_WR_EHF 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR5_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TERM 1:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_80 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_INV_READ 3:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_INV_READ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_INV_READ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TO 4:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TO_RESET 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CA_TO_PROG 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_DIS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_EN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_REFPB 7:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_REFPB_PB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_REFPB_P2B 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_RL_EHF 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_WR_EHF 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6_CATH 3:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6_PLL_RANGE 4:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_ADR_GDDR6_MICRON_PLL_RANGE_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_BA_MRS 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS8_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9 0x00984358 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR5_PRE_EMPHASIS 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_RX_MASK 1:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDM 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDU 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_TXEQ 6:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_TXEQ_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_TXEQ_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_ADR_GDDR6X_PIN_SUB_ADDRESS 11:7 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10 0x00986200 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET 3:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT 5:4 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT 7:6 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK2CK 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET_MSB 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM 11:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS10_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11 0x00986204 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS11_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12 0x00986208 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_LSB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_MSB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_PRBS 2:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_PRBS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_PRBS_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK 11:3 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS12_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13 0x0098620C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS13_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14 0x0098435C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR_MICRON_CORE_VOLTAGE 4:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_ADR_MICRON_SUBREG_SELECT 11:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15 0x0098434C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_HBM_IVREF 2:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREA 0:0 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREA_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREA_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREB 1:1 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREB_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_MREB_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_CADT 3:2 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_CADT_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_CADT_RISING 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_CADT_FALLING 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR6X_CADT_CABI 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF0 8:8 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF1 9:9 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING 10:10 /* ----F */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_BA_MRS 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS15_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16 0x00986210 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS16_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17 0x00986214 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS17_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18 0x00986218 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS18_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19 0x0098621C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS19_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20 0x00986220 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS20_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22 0x00986224 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS22_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23 0x00986228 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS23_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24 0x0098622C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS24_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25 0x00986230 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS25_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32 0x00986234 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS32_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40 0x00986238 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS40_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_MRR 0x0098623C /* RW-4R */ #define NV_PFB_FBPA_MC_1_MRR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_MRR_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MRR_CMD_MRR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MRR_CMD_MRR_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MRR_BA 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MRR_BA_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MRR_RANK 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MRR_RANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MRR_CH 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MRR_CH_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_VLD_SUBP0 10:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_VLD_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_SUBP0 18:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_VLD_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_VLD_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_SUBP1 27:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_MRR_GEN_DATA_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_MPC 0x00986240 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MPC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_MPC_ADR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MPC_ADR_NOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MPC_ADR_START_DQS_OSC 0x0000004b /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_ADR_STOP_DQS_OSC 0x0000004d /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MPC_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MPC_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MPC_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MPC_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MPC_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MPC_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_MPC_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC 0x00984350 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_BANK_SEQ 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_BANK_SEQ_INC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_BANK_SEQ_BG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_NO_TR_ACT_IN_TFAW 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_NO_TR_ACT_IN_TFAW_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_NO_TR_ACT_IN_TFAW_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_TR_RW_ALL_BANK 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_TR_RW_ALL_BANK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_TR_RW_ALL_BANK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_IDLE_ON_TR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_IDLE_ON_TR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_IDLE_ON_TR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ACT_HIGH_PRIORITY 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ACT_HIGH_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ACT_HIGH_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_HOLDOFF_WRACT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_HOLDOFF_WRACT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_HOLDOFF_WRACT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_WR_FEEDBACK 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_WR_FEEDBACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_WR_FEEDBACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BG_ENABLE_ON_CCD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BG_ENABLE_ON_CCD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_BG_ENABLE_ON_CCD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ENABLE_RRDL_COUNTER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ENABLE_RRDL_COUNTER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ENABLE_RRDL_COUNTER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_KILL_PEND_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_KILL_PEND_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_KILL_PEND_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_TR_SAFE_SCHED 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_TR_SAFE_SCHED_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ABPA_PER_RANK 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_ABPA_PER_RANK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_MAX_BANK_HITS 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_MAX_BANK_HITS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_MAX_BANK_HITS_MAX 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_PRIORITY 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_PRIORITY_HIGHEST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_PRIORITY_MEDIUM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_PRIORITY_LOWEST 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_GBL_RRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_GBL_RRD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_PBR_GBL_RRD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_CMDQ_ALWAYS_ON 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_CMDQ_ALWAYS_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_CMDQ_ALWAYS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_FORCE_G5_TO_G5X 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_FORCE_G5_TO_G5X_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MISC_DRAMC_FORCE_G5_TO_G5X_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_IC_CTRL 0x00984208 /* RW-4R */ #define NV_PFB_FBPA_MC_1_IC_CTRL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_DIRECTION_SYNC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_DIRECTION_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_DIRECTION_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_SP2DRAMC_FLOP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_IC_CTRL_SP2DRAMC_FLOP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_SP2DRAMC_FLOP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO 0x009863FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO_THRESHOLD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO_STALL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_STALL_CMD_FIFO_STALL_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0 0x00984360 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1 0x00984364 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0 0x00984368 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1 0x0098436C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS9_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0 0x00984370 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1 0x00984374 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS14_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT 0x00984378 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS4_EXT_BA_MRS4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT 0x0098437C /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS5_EXT_BA_MRS5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT 0x00984380 /* RW-4R */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_GENERIC_MRS6_EXT_BA_MRS6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1 0x00984280 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CG1__PRIV_LEVEL_MASK 0x009841B4 /* */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_TRAINING 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_TRAINING_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_TRAINING_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIV 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIV_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_REPLAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_REPLAY_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_REPLAY_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SS2PACMD1 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SS2PACMD1_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SS2PACMD1_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_FABSCAN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_FABSCAN_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_FABSCAN_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIVSYNC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIVSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PRIVSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_6_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_6_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAF2TSUBP 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAF2TSUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAF2TSUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_ILA 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_ILA_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_ILA_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAL 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAL_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_PAL_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_10 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_10_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_10_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_11 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_11_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_11_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_12 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_12_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_12_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_13 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_13_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_13_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_14 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_14_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_14_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_15_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_15_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_16 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_16_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_16_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_17 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_17_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_17_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_18 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_18_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_18_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_19 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_19_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_19_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_20 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_20_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_20_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_21 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_21_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_21_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_22 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_22_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_22_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_23 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_23_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_23_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_24 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_24_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_24_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_25 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_25_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_25_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_26 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_26_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_26_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_27 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_27_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_27_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_28 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_28_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_28_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_29 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_29_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_29_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_30 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_30_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_30_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_31 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_31_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_SPARE_31_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG 31:0 /* ----F */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG_DISABLED 0xFFFFFFFF /* ----V */ #define NV_PFB_FBPA_MC_1_CG1_SLCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_CG2 0x00984284 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CG2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FAB_INTFC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FAB_INTFC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FAB_INTFC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_SUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_SUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_MISC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_MISC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FABRIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_PRI_REG_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_PRI_REG_UPDATE_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_PRI_REG_UPDATE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_CMD_FABRIC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_CMD_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_CMD_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG 5:0 /* ----F */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG_DISABLED 0x0000003F /* ----V */ #define NV_PFB_FBPA_MC_1_CG2_FGCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG 0x00984400 /* RW-4R */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_CHAIN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_CHAIN_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_CHAIN_32 0x0000001f /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_CHAIN_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_LIST_SIZE 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_LIST_SIZE_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_MAX_LIST_SIZE_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_PAGE_SIZE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_PAGE_SIZE_1K 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_PAGE_SIZE_2K 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_SET_SWIZZLE 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG 0x00984410 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_8 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_EVICT_ON_CLEAN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_EVICT_ON_CLEAN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_EVICT_ON_CLEAN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_BANKQ 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_DISABLE 0x0000007f /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_SET_SWIZZLE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD_3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG 0x00984420 /* RW-4R */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG 0x00984430 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0 0x00984440 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_LATENCY_INTERVAL 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_LATENCY_INTERVAL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_LATENCY_INTERVAL_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LATENCY_OFFSET 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LATENCY_OFFSET_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LATENCY_OFFSET_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LATENCY_OFFSET_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LATENCY_OFFSET_F 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_READ_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_WRITE_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1 0x00984444 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_SNAPSHOT_ARB 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_SNAPSHOT_ARB_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_SNAPSHOT_ARB_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_BLOCKS_SPSM 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2 0x00984448 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_READ_SEC_THRESHOLD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_READ_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_READ_SEC_OFFSET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_READ_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_WRITE_SEC_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG2_WRITE_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3 0x0098446C /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_LATENCY_USES_LTCCLK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG3_LATENCY_USES_LTCCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4 0x009844BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4_READ_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4_READ_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4_WRITE_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG4_WRITE_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5 0x00986580 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6 0x00986584 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7 0x00986588 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG 0x00984450 /* RW-4R */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WRITEPULL_REQ 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WRITEPULL_REQ_IMM 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_WRITEPULL_REQ_WAIT_RWDIR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_USE_DRAMC_BUSY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_USE_DRAMC_BUSY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_USE_DRAMC_BUSY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CMD_FIFO_DEPTH 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CMD_FIFO_DEPTH_NOLIMIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_POLICY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_PRIORITY 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_PRIORITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_PRIORITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB_NOLIMIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_DELAY 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_DELAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_WRITE_ARB_CFG_CCDMW_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG 0x00984454 /* RW-4R */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_POLICY 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_LEVEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_COMBINE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READ_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG 0x00984460 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_RD_SUBPACKETS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_RD_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_RESNAP_DURING_TURN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_RESNAP_DURING_TURN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_RESNAP_DURING_TURN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SNAP_BASED_ON_VC 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SNAP_BASED_ON_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SNAP_BASED_ON_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_WR_SUBPACKETS 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_WR_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_BGSEC 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_BGSEC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_BGSEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_BANKQ_ENTRIES 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_BANKQ_ENTRIES_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MAX_SKIP_COUNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MAX_SKIP_COUNT_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM_6 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_PER_VC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_PER_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_PER_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_MODE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG_SKIP_CNT_MODE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1 0x00984464 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_ACTARB_CMD_DELAY 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_ACTARB_CMD_DELAY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_ACTARB_CMD_DELAY_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_HOLDOFF 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_HOLDOFF 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_ACTARB_FIFO_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG1_ACTARB_FIFO_DELAY_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2 0x00984468 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE 25:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE 30:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG3 0x009844C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG3_IC_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG3_IC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG3_IC_MODE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4 0x009844D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH 0x009844D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR5 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR5 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MIN 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_MIN_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_TYPE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_TYPE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FIFO_DEPTH_ASYNC_CMDQ_TYPE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW 0x009844D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_ACPD_ASR 0x00984458 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_ACPD_ASR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR 0x009844DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0 0x009844F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1 0x009844F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2 0x009844F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR 0x009844FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WR 0x009844E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_WR_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC0 0x009844E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC0_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC0_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1 0x009844E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_UTIL_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_ECC 0x0098445C /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_ECC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_ECC_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC1_ECC_UTIL_INIT 0x00000555 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC2 0x009844EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC2_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_VC2_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ACPD 0x009844B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ACPD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ACPD_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ACPD_UTIL_INIT 0x000000CC /* RWI-V */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ASR 0x0098444C /* RW-4R */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ASR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ASR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BW_TRACKER_ASR_UTIL_INIT 0x00000199 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL 0x00984470 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL__PRIV_LEVEL_MASK 0x00984170 /* */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_MASTER_EN 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_MASTER_EN_ENABLED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_MASTER_EN_DISABLED 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_INCLUDE_ADDR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_INCLUDE_ADDR_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_INCLUDE_ADDR_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL_OFF 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_WRITE_KILL_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_EN 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_SIDEBAND_EN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_SIDEBAND_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_SIDEBAND_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR_MODE 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR_MODE_OFF 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR_MODE_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR_MODE_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0 17:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR0_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_WRITE_KILL_PTR1_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL 0x00984474 /* RW-4R */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_SEC_INTR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_SEC_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_SEC_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_DED_INTR_EN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_DED_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_DED_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_POISON_INTR_EN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_POISON_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_POISON_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_ADDRERR_INTR_EN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_ADDRERR_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_1_ECC_INTR_CTRL_ADDRERR_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS(i) (0x00984478+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ECC_STATUS__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_INTR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_INTR 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_POISON_INTR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_POISON_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_POISON_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_POISON_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_INTR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_COUNTER_OVERFLOW 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_SEC_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_COUNTER_OVERFLOW 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_DED_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_1_ECC_SEC_COUNT(i) (0x00984480+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ECC_SEC_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_SEC_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_SEC_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_DED_COUNT(i) (0x00984488+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ECC_DED_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_DED_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_DED_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG(i) (0x00984490+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_1_ECC_DIAG__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_TYPE 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_TYPE_SEC 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_TYPE_DED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_TYPE_POISON 0x2 /* R---V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_DED 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_DED_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_SEC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_SEC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_POISON 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_POISON_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_SECBIT 16:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_DIAG_SECBIT_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR(i) (0x00984498+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR__PRIV_LEVEL_MASK 0x00984170 /* */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_COL 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_COL_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_PC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_PC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_ROW 26:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_ROW_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_BANK 30:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_BANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXTBANK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXTBANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXT(i) (0x009864B8+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXT__PRIV_LEVEL_MASK 0x00984170 /* */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXT_SID 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ERR_INJECTION_ADDR_EXT_SID_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR(i) (0x009844A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT(i) (0x009844A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2(i) (0x00986498+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED(i) (0x00986448+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_DED_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED(i) (0x00986450+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_DED_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_DED(i) (0x009864A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_DED_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_DED_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC(i) (0x00986458+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_SEC_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC(i) (0x00986460+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_SEC_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SEC(i) (0x009864A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SEC_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_SEC_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON(i) (0x00986468+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_POISON_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON(i) (0x00986470+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_POISON_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_POISON(i) (0x009864B0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_POISON_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT2_POISON_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR(i) (0x00986480+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_ADDRERR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR(i) (0x00986488+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_SID 22:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDR_EXT_ADDRERR_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_1_ECC_ADDRERR_COUNT(i) (0x00986490+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_ECC_ADDRERR_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_ECC_ADDRERR_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ECC_ADDRERR_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE 0x009844B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_OVERRIDE 4+4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_OVERRIDE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BANK_SWIZZLE_OVERRIDE_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION 0x009844B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR 10:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER 0x009844C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_READS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_READS_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_READS_24 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_READS_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_RW 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_RW_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_RW_28 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_LTC_BANDWIDTH_LIMITER_RW_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO 0x009844C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_INIT 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_INIT_VAL 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET 13:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_READSCHEDULE_FIFO 0x009844CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_READSCHEDULE_FIFO__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_READSCHEDULE_FIFO_DEPTH_LIMIT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_READSCHEDULE_FIFO_DEPTH_LIMIT_FULL 0x000001FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL 0x00984500 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE 5:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_MRS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_REFRESH 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_SELFREFRESH_ENTRY 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_POWERSTATE_EXIT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_POWERDOWN_ENTRY 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_PRECHARGE 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_PRECHARGE_ALL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_ACTIVATE 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_WRITE 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_WRITE_AUTOPRE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_WRITE_ANY 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_READ 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_READ_AUTOPRE 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_READ_ANY 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_CACHE_MGMT_OP_PENDING 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_LDFF 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_RDTR 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_WRTR 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_ZQCL 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_ZQCS 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_REPLAY 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_REPLAY_START 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_READ_TRAINING 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_WRITE_TRAINING 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_MRR 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_MPC 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_REFSB 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_STEP 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_SEQUENCE 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_ADR 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_WCK 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_RD 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_WR 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_QUSE 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_MODE 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_TRAINING_PERIODIC 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_CHAR_WRITE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_CHAR_READ 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_CHAR_ERROR 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_CHAR_ERROR_ANY 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_MASKED_PW 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_PAIRED_RW 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_UNPAIRED_CH0 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_UNPAIRED_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_UNPAIRED_CH0_SW 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_UNPAIRED_CH1_SW 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_EDC_RD_ERR 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_EDC_WR_ERR 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_STATE_DQR 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_BASE_DELAY 12:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_BASE_DELAY_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_BASE_DELAY_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_LENGTH 23:20 /* RWIUF */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_LENGTH_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_LENGTH_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_INV 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_INV_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_INV_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_EN 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRIGGER_CNTRL_TRIGGER_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAP0 0x0098450C /* R--4R */ #define NV_PFB_FBPA_MC_1_CAP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CAP0_FABRIC_PRESENT 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CAP0_FABRIC_PRESENT_YES 0x00000001 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CAP0_FABRIC_PRESENT_NO 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_CAP0_ECC_PRESENT 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CAP0_ECC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CAP0_ECC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CAP0_EDC_PRESENT 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CAP0_EDC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CAP0_EDC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CAP0_REPLAY_PRESENT 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CAP0_REPLAY_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CAP0_REPLAY_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_PARITY 0x00984510 /* RW-4R */ #define NV_PFB_FBPA_MC_1_PARITY__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_DATALO 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_DATALO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_DATAHI 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_DATAHI_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_CMD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_PARITY_IB_FABRIC_ERROR_CMD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_PARITY_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_PARITY_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PARITY_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00984554 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT0 0x00984514 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT0__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT0_INTERCEPT 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT0_INTERCEPT_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT0_1 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT0_1_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT0_2 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT0_2_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT1 0x00984518 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT1__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT1_3 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT1_3_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT1_4 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT1_4_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT1_5 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT1_5_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT2 0x0098451C /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT2__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT2_6 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT2_6_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT2_7 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT2_7_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT2_8 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT2_8_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT3 0x00984520 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT3__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT3_9 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT3_9_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT3_10 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT3_10_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT3_11 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT3_11_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT4 0x00984524 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT4__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT4_12 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT4_12_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT4_13 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT4_13_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT4_14 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT4_14_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT5 0x00984528 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA_WT5__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_WT5_15 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT5_15_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA_WT5_16 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_BA_WT5_16_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_BA 0x00984550 /* RW-4R */ #define NV_PFB_FBPA_MC_1_BA__PRIV_LEVEL_MASK 0x00984554 /* */ #define NV_PFB_FBPA_MC_1_BA_BLKACTIVITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_BA_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_BA_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_BA_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_RD 0x00984558 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_RD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_RD_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_RD_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_RD_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_RD_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_RD_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_WR 0x0098455C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_WR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_WR_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_WR_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_WR_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_WR_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_WR_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER 0x00984560 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_STATUS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_STATUS_NO_ERROR 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_STATUS_ERROR 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_NUM 6:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_NUM_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_MODE_CONTINUOUS 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_MODE_ONCE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_MASK_SUBP0 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_MASK_SUBP0_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_MASK_SUBP1 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_TRIGGER_BYTE_MASK_SUBP1_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DATA0 0x00984564 /* R--4R */ #define NV_PFB_FBPA_MC_1_CRC_DATA0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_DATA0_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_DATA0_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DATA1 0x00984568 /* R--4R */ #define NV_PFB_FBPA_MC_1_CRC_DATA1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_DATA1_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_DATA1_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DATA2 0x0098456C /* R--4R */ #define NV_PFB_FBPA_MC_1_CRC_DATA2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_DATA 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_EXPECTED_EDC 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_EXPECTED_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_ACTUAL_EDC 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_DATA2_ACTUAL_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE 0x00984570 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_LIMIT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_LIMIT_1000 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_EXCEEDED 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_EXCEEDED_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_EXCEEDED_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_EXCEEDED_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_TICK_CLOCK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_TICK_CLOCK_LTCCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_RATE_TICK_CLOCK_MEMREF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_TICK 0x00984574 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_TICK__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_TICK_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_TICK_VALUE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_TICK_VALUE_1US 0x000002EE /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_MAX_DELTA 0x00984578 /* R--4R */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_MAX_DELTA__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_MAX_DELTA_VALUE 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_MAX_DELTA_VALUE_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0 0x009840D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1 0x009840D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0 0x009840D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1 0x009840DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC 0x00984580 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_DURING_RETRY 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_DURING_RETRY_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_DURING_RETRY_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_DURING_RETRY_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT 0x00984584 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_CNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_CNT_16384 0x00004000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_CNT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_CNT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_DELTA 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_DELTA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_MAX_DELTA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_ERR_ON_RETRY 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_ERR_ON_RETRY_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_CRC_INTERRUPT_EN_ERR_ON_RETRY_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG 0x00984588 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_ERR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_ERR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_RPL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_RPL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP0_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_ERR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_ERR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_RPL 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_RPL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_CRC_DEBUG_SUBP1_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_RD_BYTE(i) (0x00986400+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_RD_BYTE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_RD_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_RD_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_WR_BYTE(i) (0x00986420+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_WR_BYTE__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_WR_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CRC_ERROR_COUNT_WR_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG 0x00986440 /* RWI4R */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_MAXRETRY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_MAXRETRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_SUBP0_SKIPCNT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_SUBP0_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_SUBP1_SKIPCNT 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_REPLAY_DEBUG_SUBP1_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR(i) (0x009864D4+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_1ST 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_1ST 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_1ST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_1ST 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_2ND 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_2ND 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_2ND 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_2ND 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_RDAT3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_1ST 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_1ST 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_1ST 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_1ST 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_2ND 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_2ND 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_2ND 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_2ND 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_RR_FIFOERR_EDC3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_REFCTRL3 0x009864DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFCTRL3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR_SRC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR_SRC_DRAMC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_PBR2ABR_SRC_PWRM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_THRESHOLD 20:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_THRESHOLD_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_SPEEDUP 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_SPEEDUP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFCTRL3_SOFTKILLPBR_SPEEDUP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY 0x0098458C /* RW-4R */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY_MAX 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY_MAX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY_LAST 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_ISO_LATENCY_LAST_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS 0x00984398 /* R--4R */ #define NV_PFB_FBPA_MC_1_INTR_STATUS__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP0 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP0 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP0 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP0 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP0 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP1 16:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_SEC_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP1 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_DED_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_OOR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_POISON_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP1 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_ADDRERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP1 24:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_INTR_STATUS_AERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_OOR 0x009843A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_OOR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_OOR_COUNT_SUBP0 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_OOR_COUNT_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP0_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_OOR_COUNT_SUBP1 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_OOR_COUNT_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP1 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_OOR_RESET_COUNT_SUBP1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP0 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP1 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_1_OOR_INTR_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_OOR_INTR_ENABLE_OFF 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_OOR_INTR_ENABLE_ON 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0 0x0098438C /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CFG0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK_BANK 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK_BANK_8 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_DUAL_RANK_BANK_16 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SCHED_PC_LIMIT 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SCHED_PC_LIMIT_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SCHED_PC_LIMIT_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_OVR 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_VAL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID1_VAL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID1_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CFG0_SID1_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG 0x009843A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_SECCNT_ARB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_SECCNT_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_SECCNT_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_MIN_BG_SECTORS 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_MIN_BG_SECTORS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_RESIDUAL_THRESHOLD 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG_RESIDUAL_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1 0x009843A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_RD_RANK_DURATION 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_RD_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_RD_RANK_MIN_STAY 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_RD_RANK_MIN_STAY_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_WR_RANK_DURATION 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_ARB_CFG1_WR_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR 0x009843AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_DQ(i) (0x00000000 + (i)) /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_DQ__SIZE_1 128 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_ECC(i) (0x00000090 + (i)) /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_ECC__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_DBI(i) (0x00000080 + (i)) /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PIN_DBI__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PC 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PC_PC0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PC_PC1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_PC_PC01 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_DBI 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_DBI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_ECC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x009843B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x009843B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x009843B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x009843BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x009843C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x009843C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x009843C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x009843CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI 0x009843D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC 0x009843D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MAX 0x009843D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MAX__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MAX_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_MAX_V_INIT 0xFFFFFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_THRESHOLD 0x009843DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_THRESHOLD__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_THRESHOLD_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_HBM_CHAR_COUNTER_THRESHOLD_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_RR_CTRL 0x009843FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_RR_CTRL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_RR_CTRL_PC_NPC_GAP 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_CTRL_PC_NPC_GAP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_RR_CTRL_RW_GAP 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_RR_CTRL_RW_GAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK 0x009848FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST 0x00984590 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_SDDR23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_DDR3 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MODE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MODE_LATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MODE_EARLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_SEND_A14_A15_ON_ABI 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_EYE_MASK 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_EYE_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_EYE_MASK_LOWER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_EYE_MASK_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_EYE_MASK_UPPER 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GENERIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GENERIC2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR3_BGA136 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_SDDR3_BGA100 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR5_GT215_COMP 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR1 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_X8 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR_X8 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_SDDR4_BGA78 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_HBM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_SDDR4_3DS 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_USE_EXTENDED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_MODE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_SUBP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_GEARDOWN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_GEARDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_2T_CMD_GEARDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_G5X_CMD_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_G5X_CMD_MODE_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_G5X_CMD_MODE_G5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_MODE 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_RX_RCV_SEL 22:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_RX_RCV_SEL_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_RX_RCV_SEL_LOW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_RX_RCV_SEL_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_PAM4_RX_RCV_SEL_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_OB_FABRIC_DBI 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_OB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_OB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_IB_FABRIC_DBI 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_IB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_IB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_LPDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_1 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_2 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_IC 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_4 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6X_BGA180_MODE_1 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_90D 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_270D 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI 0x00984594 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_ON 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_MODE_SSO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_OUT_MODE_LP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_IN_ON 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_IN_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG_DBI_IN_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CHANNELCFG 0x00984598 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CHANNELCFG__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CHANNELCFG_CHANNEL_ENABLE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CHANNELCFG_CHANNEL_ENABLE_32_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CHANNELCFG_CHANNEL_ENABLE_64_BIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1 0x0098459C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_INTERP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_INTERP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_INTERP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RCVR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RCVR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RCVR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RX_CLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RX_CLK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BROADCAST1_POWER_EN_RX_CLK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5 0x00984604 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_CMD_PAD_DISABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_CMD_PAD_DISABLE_NOT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_CMD_PAD_DISABLE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V1P2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V1P8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V2P1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_VDDP_MODE_V2P4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_ATDAT_FORCE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_ATDAT_FORCE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_ATDAT_FORCE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_PU40_MODE_CMD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_PU40_MODE_CMD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CONFIG5_PU40_MODE_CMD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE 0x0098460C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE__PROD_C_DDR1 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE__PROD_C_DDR2 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE__PROD_C_DDR3 0x00300001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE__PROD_C_DDR4 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE__PROD_C_DDR5 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_DELAYED_CALDRV_SDDR 1:1 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_E_SER_FORCE_ONE 4:4 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_FORCE_MA_SDR 7:7 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_FORCE_MA_SDR_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_FORCE_MA_SDR_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_PAD_CALIBRATION 11:11 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_PAD_CALIBRATION_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_PAD_CALIBRATION_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_SERIALIZER 12:12 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_SERIALIZER_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_SERIALIZER_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_EN 25:25 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_EN_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_EN_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB 26:26 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV 27:27 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE_VALUE_CLK_OBS_CLK_SEL 29:28 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN 0x00984610 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN 0x00984614 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR 0x0098461C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_ASR__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VAUXC 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VCLAMP 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VAUXP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VAUXC 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VCLAMP 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ASR_BRICK_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL 0x00984670 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_FILTER_BITS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_FILTER_BITS_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_START_TRM 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_START_TRM_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_END_COUNT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_END_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_LEGACY_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_LEGACY_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_IGNORE_START 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_CALIBRATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS 0x00984674 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS 0x00984678 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL 0x0098467C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DLCELL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DLCELL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_CORS_TRIMMER 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_CORS_TRIMMER 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_MDDLL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_WDQS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL 0x00984694 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP0_ADR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP0_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP1_ADR0 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP1_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL 0x00984698 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL 0x0098469C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL 0x009846A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL 0x009846A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL 0x009846A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL 0x009846AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL 0x009846B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL 0x009846B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL 0x009846B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL 0x009846BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1 0x00984ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1 0x00984EDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE 0x00984700 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_BYTE_VREF_MODE_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL 0x00984704 /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_IB 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_IB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_OB 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_OB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_DQDQS 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_DQDQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_QUSE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_DDLL_QUSE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC 0x00984708 /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_MODE 1:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE 3:2 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_DAT 6:4 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_DAT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_DQS 10:8 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_VREF_DQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT 20:16 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1 0x0098470C /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x00984710 /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x00984714 /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3 0x00984718 /* -W-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE 2:0 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE 5:3 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE 8:6 /* -WIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK 0x00984650 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_PREDI 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_PREDI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK0_ON 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK0_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK0_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK1_ON 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK1_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK1_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK_RUN 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_CLK_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_POLARITY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_POLARITY_NORMAL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK_POLARITY_INVERT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY 0x0098465C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DELAY_PRIV_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY 0x009848E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DELAY_CMD_PRIV_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER 0x009848E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER_PATTERN 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER_PATTERN_INIT 0x33330F0F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_QDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_DDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6x 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK 0x0098466C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_TX_DRVDN 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_TX_DRVUP 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_E_PU40 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_E_PU40_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_E_PU40_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_FREEZE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL 0x00984504 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CFG_DRVDLY 31:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CFG_DRVDLY_A 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB 0x00984508 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB__PRIV_LEVEL_MASK 0x00984168 /* */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_1CYCLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_2CYCLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_3CYCLE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_4CYCLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_SEL_TRNG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_SEL_CAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_TRNG_ARB_SKIP_CNT_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR 0x00984720 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVR_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF 0x00984724 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVF_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT 0x00984728 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_DRVT_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR 0x00984730 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_SLWR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS 0x00984738 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVF 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVF_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVF_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVF_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_BYP_CS_DRVF_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0 0x009847D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD0_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD0_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD0_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD1_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD1_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD1_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD2_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD2_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD2_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD3_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD3_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD3_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD4_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD4_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD4_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD5_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD5_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD5_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD6_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD6_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD6_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD7_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD7_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD7_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD8_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD8_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD8_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD9_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD9_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD9_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD10_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD10_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD10_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD11_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD11_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD11_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD12_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD12_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD12_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD13_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD13_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD13_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD14_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD14_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD14_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD15_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD15_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL0_CMD15_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1 0x009847D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD16_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD16_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD16_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD17_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD17_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD17_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD18_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD18_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD18_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD19_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD19_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD19_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD20_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD20_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD20_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD21_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD21_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD21_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD22_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD22_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD22_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD23_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD23_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD23_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD24_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD24_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD24_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD25_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD25_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD25_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD26_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD26_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD26_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD27_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD27_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD27_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD28_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD28_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD28_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD29_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD29_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD29_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD30_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD30_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD30_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD31_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD31_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL1_CMD31_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2 0x009847D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD32 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD32_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD32_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD32_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD33 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD33_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD33_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD33_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD34 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD34_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD34_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD34_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD35 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD35_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD35_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD35_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD36 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD36_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD36_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD36_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD37 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD37_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD37_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD37_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD38 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD38_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD38_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD38_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD39 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD39_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD39_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD39_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD40 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD40_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD40_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD40_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD41 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD41_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD41_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD41_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD42 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD42_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD42_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD42_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD43 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD43_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD43_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD43_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD44 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD44_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD44_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD44_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD45 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD45_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD45_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD45_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD46 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD46_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD46_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD46_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD47 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD47_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD47_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL2_CMD47_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3 0x009847E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD48 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD48_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD48_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD48_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD49 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD49_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD49_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD49_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD50 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD50_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD50_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD50_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD51 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD51_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD51_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD51_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD52 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD52_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD52_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD52_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD53 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD53_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD53_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD53_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD54 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD54_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD54_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD54_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD55 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD55_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD55_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_CAL_ADR_DRV_SEL3_CMD55_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG 0x009847E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CMD_STEP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CMD_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CMD_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CK_STEP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_CK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_WCK_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_WCK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_WCK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_BGCAL_FREEZE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CALCFG_BGCAL_FREEZE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x00985EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x00985ECC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x00985ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x00985ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x00985ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x00985EDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x00985EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x00985EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x00985EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x00985EEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x00985EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x00985EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x00985EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x00985EFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x00985F00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x00985F04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x00985F08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x00985F0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x00985F10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x00985F14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x00985F18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x00985F1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x00985F20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x00985F24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK 0x00985F28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DRVDN_BYP_SEL_INI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML 0x00985F34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_CLK_VML_SEL_VML 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK 0x00985F2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML 0x00985F38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_SEL_CML 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CAL_WCK_VML_SEL_VML 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG 0x00984000 /* RWE4R */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_DLY_CNT__PROD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG1 0x00984004 /* RWE4R */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_1_PRI_FBPA_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8 0x00984800 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU__PROD_C_DDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INTERP_EDC_PWRD_ENABLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INTERP_EDC_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT 2:2 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG8_RFU_RDQS_RCVR_SEL_XOR 5:4 /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10 0x00984808 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_DQ 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_RDQS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_RDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_RDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_WDQS 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_CMD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPD_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_DQ 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_RDQS 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_RDQS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_RDQS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_WDQS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WKPU_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_DQ_TERM_MODE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_DQ_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_DQ_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_DQ_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_DQ_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_TERM_MODE 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WDQS_TERM_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_WDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_RDQS_DIFF_MODE 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_RDQS_DIFF_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_RDQS_DIFF_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_SRC_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_SRC_SEL_RDQS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_RDQS_SRC_SEL_WDQS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_INTERNAL_VREF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_INTERNAL_VREF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG10_E_INTERNAL_VREF_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BRLSHFT 0x00984820 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BRLSHFT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BRLSHFT_CMD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BRLSHFT_CMD_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD 0x00984824 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD__PRIV_LEVEL_MASK 0x0098486C /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CML_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CML_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CML_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_RDQS_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_PWRD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_TX_PWRD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_ON 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CLK_TX_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CLK_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CLK_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCK_TX_PWRD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCK_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCKB_TX_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCKB_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DIFFAMP_PWRD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DIFFAMP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DIFFAMP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CK_DIGDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11 0x00984828 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11__PRIV_LEVEL_MASK 0x0098486C /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_S_MACRO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_D_MACRO 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_S_PAD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_D_PAD 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_LOOPBK_MODE_I_PAD 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CK_DEEPLOOP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_E_LPBK_INTERFACE_MODE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_E_LPBK_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_E_LP_MODE_CMD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_E_LP_MODE_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_WCK_DEEPLOOP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_WCK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_VEND_ID_C0_LOAD_EN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_VEND_ID_C0_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_VEND_ID_C1_LOAD_EN 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_VEND_ID_C1_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_PARALLEL_LPBK_MODE_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_PARALLEL_LPBK_MODE_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CLAMP_VAL 23:23 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CLAMP_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CONFIG_CMD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG11_CONFIG_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12 0x0098482C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PVT_CODE_BYTE_C0_RB 10:8 /* R--VF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PVT_CODE_BYTE_C1_RB 13:11 /* R--VF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_INTRP_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_INTRP_8UI_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_INTRP_8UI_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_STEP16 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_STEP8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_STEP4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_STEP2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_STEP1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CYA_SELECT_NO_STEP 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_TX_EN_EARLY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_TX_EN_EARLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_TAPERED_START 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_TAPERED_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_WCK_TAPERED_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CAP 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_INTERP_CAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_CMD_BR8_DELAY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_CMD_BR8_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_CMD_BR8_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG12_CMD_BR8_DELAY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1 0x00984830 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_FBIO_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPRE_TWO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPRE_TWO_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPRE_TWO_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPOST 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPREPOST_DQ_VALUE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPREPOST_DQ_VALUE_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WPREPOST_DQ_VALUE_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WDQS_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WDQS_MODE_WDQS_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_WDQS_MODE_WDQS_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_HOLD_DQ 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_HOLD_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_SETUP_DQ 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_SETUP_DQ_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_SETUP_STR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_EN_SETUP_STR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_CMD_BRLSHFT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_CMD_BRLSHFT_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_CMD_BRLSHFT_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_ON 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_SHORT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_NORMAL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_LONG 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_QUSE_FORCE_HIGH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_QUSE_FORCE_HIGH_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_QUSE_FORCE_HIGH_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_BIT2 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_EXTENDED_QUSE_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_PADMACRO_SYNC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_PADMACRO_SYNC_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_PADMACRO_SYNC_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_RCV_CLOCKING 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_RCV_CLOCKING_STROBE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_RCV_CLOCKING_CONTINUOUS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_CLK_ASSERT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_CLK_ASSERT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_TX_CLK_ASSERT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_IB_PMACRO_PTR_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RUN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RESET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_PADMACRO_RESET 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_PADMACRO_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_INTERP_RESET 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_INTERP_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_DDLL_INIT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_DDLL_INIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG1_DDLL_INIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE2 0x00984834 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE2_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SPARE2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C0 0x00984838 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C0_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C0_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C1 0x0098483C /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C1_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VEND_ID_C1_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK 0x00984860 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_DLY_CK0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_DLY_CK0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_DLY_CK1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_DLY_CK1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMOS_CLK_SEL_CMOS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK 0x00984864 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK 0x00984868 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL 0x00984870 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_RCV_CTRL_LANE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7 0x00984874 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7_CMD_RCV_CTRL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7_CMD_RCV_CTRL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7_CMD_OB_SYNC_DLY 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG7_CMD_OB_SYNC_DLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL 0x00984890 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL__PRIV_LEVEL_MASK 0x0098486C /* */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_OB_BYTE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_BYTE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_CMD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WCK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_TRAINING_PRIV 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_TRAINING_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_FABRIC_FGCG 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_BLCG_BYTE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL 0x00984894 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_31 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 29:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1 0x00984898 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CG 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_DQ_DISABLE_ASR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_DQ_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_DISABLE_ASR 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_WCK_DISABLE_ASR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_WCK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CK_DISABLE_ASR 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L 0x009848C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H 0x009848CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL 0x009848D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK0_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK0_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK0_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK0_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK1 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK1_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK1_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK1_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CLK_CTRL_CLK1_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM 0x009848D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM_BYTE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM_BYTE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM_CMD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_LOOPBK_TRIM_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY 0x009848D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE1 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE2 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE2 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE2_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE3 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE3 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE3_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE4 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE4 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE4_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE5 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE5 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE5_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE6 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE6 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE6_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE7 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ENABLE_LANE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE7 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_PARITY_ERROR_LANE7_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY 0x009848DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PARITY_ERR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PARITY_ERR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG 0x00984E00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE_CML 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_ENABLE_CML_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_READY 16:16 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_LOCK 17:17 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSA 24:24 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSD 25:25 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_CML 26:26 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_CML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_4PHCML 27:27 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_4PHCML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_DLL 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_DLL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_600 29:29 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_600_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_600_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_PLL_600_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF 0x00984E04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_NDIV_INIT 0x00000014 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_NDIV_MIN 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_SEL_DIVBY2 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_SEL_DIVBY2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_SEL_DIVBY2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_COEFF_SEL_DIVBY2_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL 0x00984E08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_PLL_FREQLOCK 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_PLL_FREQLOCK_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_PLL_FREQLOCK_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_PLL_FREQLOCK_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_MON_TESTOUT 31:29 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_MON_TESTOUT_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_ENABLE_BG 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG2 0x00984E0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS 0x00984E14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_READY 0:0 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_LOCK 1:1 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK 2:2 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_READY 3:3 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_LOCK 4:4 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK 5:5 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_READY 6:6 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_LOCK 7:7 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK 8:8 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_READY 9:9 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_LOCK 10:10 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK 11:11 /* R-IUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_SETUP2 19:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_DUAL_STATUS_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3 0x00984E18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DEBUG_DLL 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DEBUG_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_KCP_DLL 9:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_KCP_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DELAYGAIN 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DELAYGAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_BYPASS_ASYNC 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_BYPASS_ASYNC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DLL_ENABLE 14:14 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_DLL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_SEL_DLLCLK 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_SEL_DLLCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_TESTSEL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_TESTSEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_SPEEDUP 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_SPEEDUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_TESTEN 29:29 /* RWIUF */ #define NV_PFB_FBPA_MC_1_DRAMPLL_CFG3_TESTEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG 0x00984E20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_SYNC_MODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENB_LCKDET_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_ENB_LCKDET_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_READY 16:16 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_LOCK 17:17 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSA 24:24 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSD 25:25 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_CML 26:26 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_4PHCML 27:27 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_DLL 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_PLL_600 29:29 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF 0x00984E24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_NDIV_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_NDIV_MIN 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL 0x00984E28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_MON_TESTOUT 31:29 /* R--UF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2 0x00984E2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SDM 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SSC 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SSC_BYP 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SSC_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SSC_BYP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SSC_BYP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SDM_RESET 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER2 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER2_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SSD_EN_DITHER2_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0 0x00984E30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0_SDM_SSC_STEP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0_SDM_DIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD0_SDM_DIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1 0x00984E34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1_SDM_SSC_MAX 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1_SDM_SSC_MIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_REFMPLL_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK 0x00986030 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x00986034 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_GSP_SEC2_IFF_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK 0x00986038 /* RW-4R */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR(i) (0x00984900+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_ROW 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_EXTBANK 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_EXTBANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_BANK 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD(i) (0x00984910+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD__PRIV_LEVEL_MASK 0x00986038 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_ADR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WCK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WCK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WR 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE_PRIME 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE_PRIME_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_QUSE_PRIME_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CHAR_ENGINE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CHAR_ENGINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CHAR_ENGINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_PERIODIC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RW_LEVEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RW_LEVEL_BYTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_RW_LEVEL_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STROBE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STROBE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STROBE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CONTROL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CONTROL_TRIMMER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CONTROL_DLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CONTROL_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_CONTROL_DLCELL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STEP 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_STEP_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_GO 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CMD_GO_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_TRAINING_DP(i) (0x00984918+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DP__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_LO 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_LO_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_HI 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_HI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD(i) (0x00984920+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_DBI 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_DBI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_EDC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_EDC_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_SEL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_SEL_RD 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_SEL_WR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_SEL_LEGACY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DP_CNTD_SEL_CHAR_ENGINE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL(i) (0x009849C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0(i) (0x00984938+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR4 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR4_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR5 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR5_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR6 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR6_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR7 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR7_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ0_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1(i) (0x00984940+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR8 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR8_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR9 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR9_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR10 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR10_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR11 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR11_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR12 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR12_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR13 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR13_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR14 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR14_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR15 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR15_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ1_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2(i) (0x00984948+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR16 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR16_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR17 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR17_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR18 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR18_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR19 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR19_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR20 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR20_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR21 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR21_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR22 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR22_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR23 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR23_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ2_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3(i) (0x00984950+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR24 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR24_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR25 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR25_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR26 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR26_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR27 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR27_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR28 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR28_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR29 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR29_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR30 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR30_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR31 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR31_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_DQ3_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0(i) (0x00984958+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_EDC_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR0 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR1 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR2 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR3 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC0_DBI_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1(i) (0x00984960+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR0 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR0_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR0_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR1 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR1_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR1_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC0 13:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC0_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC0_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC0_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC1 15:14 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC1_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC1_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC1_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR2 25:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR2_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR2_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR3 27:26 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR3_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_ERR3_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC2 29:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC2_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC2_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC2_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC3 31:30 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC3_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC3_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_DEBUG_MISC1_WCK_EDC3_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR(i) (0x00984968+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ADR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ADR_ACT_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ADR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_DP 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_DP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_DP_TRAIN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_DP_CHAR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ACT_ADR 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ACT_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATTERN_PTR_ACT_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING 0x00984970 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_ADRTRM_SETTLE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_ADRTRM_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_ADRTRM_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_ADRTRM_FLUSH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_ADRTRM_FLUSH_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_VREF_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_VREF_SETTLE_INIT 0x0000006E /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_INTRPLTR_SETTLE 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_INTRPLTR_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING_INTRPLTR_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2 0x009849C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2_PRIV_DELAY 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2_PRIV_DELAY_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2_APPLY_DELAY 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING2_APPLY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING3 0x00986050 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING3_TVREFD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TIMING3_TVREFD_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL 0x00986054 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_MIN_INIT 0x00000038 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_MAX_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS 0x00984974 /* R--4R */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP0_STATUS 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP0_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP0_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP0_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP0_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP1_STATUS 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP1_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP1_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP1_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_STATUS_SUBP1_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL 0x00984978 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FAST_UPDATES 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FAST_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FAST_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASR_FAST_EXIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASR_FAST_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASR_FAST_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_DELAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_DELAY_2UI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_DELAY_4UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASYNC_UPDATES 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASYNC_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_ASYNC_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DFE_OVERRIDE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DFE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DFE_OVERRIDE_FORCE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE_CLEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_EXTENDED_RW_OFFSET 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_EXTENDED_RW_OFFSET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_EXTENDED_RW_OFFSET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_G5X_EDC_TR_MODE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_G5X_EDC_TR_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_G5X_EDC_TR_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_VREF_TRAINING 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_VREF_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_VREF_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_TRAINING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_CORS_INTRPLTR_TRAINING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FINE_INTRPLTR_TRAINING 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_TRIMMER_TRAINING 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_TRIMMER_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_TRIMMER_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_STOP_CLOCKS 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_STOP_CLOCKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_STOP_CLOCKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_EARLY_FLIP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_EARLY_FLIP_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_EARLY_FLIP_DIABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_STALL_CMDQ 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_STALL_CMDQ_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_STALL_CMDQ_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_QUICK 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DOUBLE_CORS_RANGE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DOUBLE_CORS_RANGE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_DOUBLE_CORS_RANGE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_RD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_WR 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_FIRST_PARTIAL_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_PADS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_PADS_FOUR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_WCK_PADS_EIGHT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL 0x0098497C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_START_WAIT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_START_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_START_EN_WAIT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_START_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_START_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_FINISH_WAIT 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_FINISH_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_REFRESH 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_REFRESH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_REFRESH_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_WAIT_IDLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_WAIT_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_LEGACY_CTRL_WAIT_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2 0x00986040 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_USE_RD_DBI_EXPECTED 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_SWEEP_PHASE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_SWEEP_PHASE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_SWEEP_PHASE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_USE_BL16 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_USE_BL16_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_USE_BL16_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_WR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_SHIFT_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_CORS_STEP_OVERRIDE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_CORS_STEP_OVERRIDE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_CORS_STEP_OVERRIDE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_WR 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_RD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_INV_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_RD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_WR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_PI_OFFSET_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_DCC 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_DCC_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_DCC_HOLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_DCC_TRACK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_QUICK_WCK 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_QUICK_WCK_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_QUICK_WCK_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_8UI_MODE_G6 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL2_WCK_8UI_MODE_G6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL 0x00986070 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_BS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_BS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_BS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_CORS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_CORS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALT_CORS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALF_FBPA 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALF_FBPA_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_HALF_FBPA_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_RX_CAPTURE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_RX_CAPTURE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_RX_CAPTURE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_BS_FOR_CA_TR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_MISC_CTRL_BS_FOR_CA_TR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG 0x00984A00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_TAG 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_TAG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL_ALWAYS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL_GREATER_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL_GREATER_BYTE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL_GREATER_DOUBLE_BYTE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_STORE_OPTIMAL_GREATER_DRAM 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_FIRST_TAG 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_FIRST_TAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_FIRST_TAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_TAG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM 0x00984A04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_CHAR_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_CHAR_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_CHAR_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_CHAR_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_CHAR_MAX_MAX 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_BURST_CNT 22:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_BURST_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_INV_EN 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_INV_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_INV_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_PATTERN_LEN 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS7 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS11 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS23 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_DUAL_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_DUAL_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_DUAL_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_ACCESS_UPPER32 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_ACCESS_UPPER32_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_ACCESS_UPPER32_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_USE_RESET_LAST 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_USE_RESET_LAST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_USE_RESET_LAST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_OVERRIDE_TRAINING 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_OVERRIDE_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_OVERRIDE_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT 0x00984AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_RD 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_WR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_PERIODIC_RD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_PERIODIC_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_PERIODIC_WR 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT_PERIODIC_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2 0x00984AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2_ADDR_START 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2_ADDR_START_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2_ADDR_END 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_SELECT2_ADDR_END_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER 0x00984A08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MAX 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_THRESHOLD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x00984AC0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x00984AC8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x00984AD0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL 0x00984A0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_MODE_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_MODE_SWEEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_SWEEP_START 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_SWEEP_START_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_SWEEP_START_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_START_COUNT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_START_COUNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_START_COUNT_ACCUMULATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_STOP_ON_ERROR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_STOP_ON_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_STOP_ON_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_REFRESH 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_HOLD_TRAFFIC 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_AFTER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_ALWAYS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_NUM_BANKS 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_NUM_BANKS_1 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_NUM_BANKS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_FUNC_MTA 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_FUNC_MTA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_FUNC_MTA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_DBI_THRESHOLD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_DBI_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_PATTERN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_DATA 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ(i) (0x00000001 + (i)) /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ__SIZE_1 31 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI0 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI1 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI2 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC0 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC3 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC0 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC1 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC2 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC3 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_CTRL_ANALYSIS_PIN_ALL 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST 0x00984A10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST_COUNT_1BANK_LIMIT 0x00000100 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST_COUNT_2BANK_LIMIT 0x00000200 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BURST_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_TURN 0x00984A14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_TURN__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_TURN_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_TURN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_TURN_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL 0x00984A18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_MIN 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_MAX 23:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_INTRPLTR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_DDLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_TRIMMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_INTRPLTR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_TRIMMER 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_DDLL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_TRIMMER 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_DDLL 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_INTRPLTR 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL 0x00984AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_MIN 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_MAX 9:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_MAX_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_MIN 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_MIN_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_MAX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_MAX_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_PREA 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_PREA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_PREA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_RANK 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_A_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_RANK 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_SET_B_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_REFA 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_REFA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL_REFA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2 0x00984ADC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_FOREVER 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL 0x009849CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ADR_SETTING 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ADR_SETTING_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ADR_MAX 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ADR_MAX_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ENABLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_TADR_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL 0x009849D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL 0x009849D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_MIN_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL 0x00984984 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_X8_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_X8_MODE_BOTH 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_X8_MODE_RISING_ONLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_X8_MODE_FALLING_ONLY 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_MIRROR 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_MIRROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_MIRROR_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_MIRROR_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_MIRROR_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_REFRESH 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_REF_CNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_REF_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_1TCK 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_3TCK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_5TCK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_31TCK 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_SKIP_CNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL 0x00984988 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x009849D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX_INIT 0x000000F0 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL 0x009849DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_DDLL_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_TRIMMER_CTRL 0x009849E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_TRIMMER_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_TRIMMER_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x0098498C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x00984A1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_OPTIMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT 0x00984990 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MIN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MAX 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_WCK_EDC_LIMIT_LATE_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL 0x009849F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL 0x009849F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_MIN_INIT 0x000000D8 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL 0x009849FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_BURST_COUNT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_QUSE_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL 0x00984AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_RPT_MODE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_RPT_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL_RPT_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2 0x00984AEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_BURST_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3 0x00984AFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR 0x00984AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_MODE 2:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_MODE_SERIAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_MODE_PARALLEL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_MODE_STAGGER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PATTERN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PATTERN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PATTERN_CUSTOM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DRAM_DEVICE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DRAM_DEVICE_X4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DRAM_DEVICE_X8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DRAM_DEVICE_X16 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DRAM_DEVICE_X32 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PAGE_SELECT 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_0_MPR0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_0_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_0_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_0_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_1_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_1_MPR1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_1_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_1_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_2_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_2_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_2_MPR2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_2_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_3_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_3_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_3_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_READ_ADR_3_MPR3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_RPT_ORDER 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_RPT_ORDER_MPR_RPT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_RPT_ORDER_RPT_MPR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA 0x00984AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR0_DEFAULT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR1_DEFAULT 0x00000033 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR2_DEFAULT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_CTRL_MPR_DATA_MPR3_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL 0x00984994 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL_CMD_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR5_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL_CMD_CNT_DDR3_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR6X_MAX 0x0000000f /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL 0x00984998 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_MAX_INIT 0x00000035 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_STEP_LN 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x009849E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD_INIT 0x00000013 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR_INIT 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL 0x0098499C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL 0x009849A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL 0x009849E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL 0x009849EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL 0x009849A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_TRIMMER_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL 0x009849A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_AREA_BASED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_AREA_BASED_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_QUICK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_VREF_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT 0x009849AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_TRIMMER 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_TRIMMER_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_ERR_LIMIT_TRIMMER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL 0x009849B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_EN_AVG 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL_EN_AVG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL 0x009849F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2 0x009849B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3 0x00986048 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL 0x0098604C /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL_EDC_TRACKING_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL 0x00986044 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_AREA_BASED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x00984A20+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x00984A28+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x00984A30+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x00984A38+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x00984A40+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x00984A48+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x00984A50+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x00984A58+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x00984A60+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x00984A68+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x00984A70+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x00984A78+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x00984A80+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x00984A88+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC(i) (0x00984A90+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_IB_MISC_EDC3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x00984A98+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x00984AA0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x00984AA8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x00984AB0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC(i) (0x00984AB8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_RW_OFFSET_OB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_SEED(i) (0x00986000+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_SEED__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_SEED_VAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PATRAM_PRBS_SEED_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL 0x00986060 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_ADDR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_ABI 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_WCK 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_FULL_PERIODIC 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_PHASE 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_PHASE_FINE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_PHASE_CORS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_CTRL_PHASE_BS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_FULL 0x00986064 /* R--4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_FULL__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_FULL_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_FULL_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_PHASE 0x00986068 /* R--4R */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_PHASE__PRIV_LEVEL_MASK 0x00986030 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_PHASE_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_TRAINING_PROFILE_PHASE_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL 0x00986074 /* RW-4R */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL__PRIV_LEVEL_MASK 0x00986034 /* */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_PRBS_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_PRBS_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_TRAINING_ARRAY_CTRL_PRBS_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG 0x00986078 /* RW-4R */ #define NV_PFB_FBPA_MC_1_SW_CONFIG__PRIV_LEVEL_MASK 0x00986034 /* */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PTRIM_OPT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PTRIM_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PTRIM_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_SELFREF_OPT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_SELFREF_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_SELFREF_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_MSCG_OPT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_MSCG_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_MSCG_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_GC6_HIB_OPT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_GC6_HIB_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_GC6_HIB_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PA_FALCON_OPT 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PA_FALCON_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_PA_FALCON_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1 0x0098607C /* RW-4R */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1__PRIV_LEVEL_MASK 0x00986034 /* */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_TRAFFIC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_TRAFFIC_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_TRAFFIC_MANUAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_MANUAL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_MANUAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_ACTIVE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_THROTTLE 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_THROTTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_BANK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG1_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_NOISE_CFG2 0x00986080 /* RW-4R */ #define NV_PFB_FBPA_MC_1_NOISE_CFG2__PRIV_LEVEL_MASK 0x00986034 /* */ #define NV_PFB_FBPA_MC_1_NOISE_CFG2_BURST 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_NOISE_CFG2_BURST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK 0x00984B04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB 0x00984B14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK 0x00984B08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB 0x00984B18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL 0x00984EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CTRL 0x00984B0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CTRL 0x00984B10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET 0x00984B00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_IB 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_IB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_OB 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_OB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_ADDR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_WCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTRPLTR_OFFSET_WCK_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x00984B20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x00984B24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x00984B28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x00984B2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x00984B30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x00984B34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x00984B38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x00984B3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x00984B40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x00984B44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x00984B48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x00984B4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x00984B50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x00984B54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x00984B58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x00984B5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x00984B60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x00984B64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x00984B68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x00984B6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x00984B70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x00984B74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x00984B78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x00984B7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x00984BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x00984BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x00984BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x00984BCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x00984BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x00984BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x00984BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x00984BDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x00984BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x00984BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x00984BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x00984BEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x00984BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x00984BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x00984BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x00984BFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x00984C00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x00984C04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x00984C08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x00984C0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x00984C10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x00984C14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x00984C18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x00984C1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x00984C20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x00984C24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x00984C28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x00984C2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x00984C30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x00984C34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x00984C38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x00984C3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x00984C40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x00984C44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x00984C48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x00984C4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x00984C50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x00984C54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x00984C58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x00984C5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x00984C60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x00984C64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x00984C68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x00984C6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x00984C70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x00984C74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x00984C78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x00984C7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x00984CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x00984CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x00984CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x00984CCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x00984CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x00984CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x00984CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x00984CDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x00984CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x00984CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x00984CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x00984CEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x00984CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x00984CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x00984CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x00984CFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x00984D00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x00984D04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x00984D08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x00984D0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x00984D10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x00984D14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x00984D18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x00984D1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x00984D70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x00984D74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x00984D78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x00984D7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x00984D80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x00984D84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x00984D88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x00984D8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x00984D90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x00984D94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x00984D98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x00984D9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x00984DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x00984DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x00984DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x00984DAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x00984DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x00984DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x00984EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x00984EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD 0x00984D28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DLCELL 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL_RANK1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_LEG_TRIM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD 0x00984D2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL 0x00984D30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_TX_DCC_MODE 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_TX_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_PHASE0_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_PAD_CTRL_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL 0x00984D34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0 0x00984D38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2 0x00984D40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_VREF_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_E_RX_DFE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TX_E_DCC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1 0x00984DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2 0x00984DBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1 0x00984DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2 0x00984DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1 0x00984DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2 0x00984DCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1 0x00984DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2 0x00984DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1 0x00984DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2 0x00984DDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1 0x00984DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2 0x00984DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1 0x00984DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2 0x00984DEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1 0x00984DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2 0x00984DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x009845A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x009845A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x009845A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x009845AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x009845B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x009845B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x009845B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x009845BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x009845C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x009845C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x009845C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x009845CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x009845D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x009845D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x009845D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x009845DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x009845E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL 0x009845E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC 27:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC 0x00984D44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_CMD_CONFIG 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_CMD_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_DQ_CONFIG 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_DQ_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_MODE 28:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1 0x00984D48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DFE_CTRL 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_DFE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_RFU 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL 0x00984EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_RX_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL 0x00984EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL 0x00984EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_RX_SUBP0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_RX_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_SUBP0 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_SUBP0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_RX_SUBP1 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_RX_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_SUBP1 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_SUBP1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL 0x00984EBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL 0x00984ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL 0x00984EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL_CLKDIST_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL_CLKDIST_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2 0x00984EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_SPARE 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_IREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_IREF_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CK_IREF_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_WCK_IREF_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_WCK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3 0x00984EEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4 0x00984EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5 0x00984EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_SPARE 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_DQ_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_SPARE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CNTL5_CMD_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL 0x00984EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG 0x00984ECC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_CK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_WCK 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_WCK_PATTERN_MASK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_MISC_CONFIG_WCK_PATTERN_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2 0x00984ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_TX_DRVDN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_TX_DRVUP 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_E_PU40 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_E_PU40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_FREEZE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DELTA_DRVR 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DELTA_DRVF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_FORCE_CAL_UPDATE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CML_CLK2_FORCE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0 0x00985004 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_FBIO_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_LOOPBK_MODE 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_LOOPBK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_TX_EN_SETUP 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_TX_EN_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_BRLSHFT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_BRLSHFT_1UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_DRAM_ECC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_DRAM_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_DRAM_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_LEKAGE_STRENGTH 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG0_LEKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_1 0x00985008 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_1_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_1_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_2 0x0098500C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_2_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_SPARE_2_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL 0x00985010 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_OB_BYTE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_BYTE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_BLCG_BYTE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL 0x00985014 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG 0x00985018 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_CLK_CNTRL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_CLK_CNTRL_NORMAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_CLK_CNTRL_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_CLK_CNTRL_FLIP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY 0x00985020 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY 0x00985024 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x0098503C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x00985040 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x00985044 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x00985048 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x0098504C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x00985050 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x00985054 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x00985058 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x0098505C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x00985060 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x00985064 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x00985068 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x0098506C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x00985070 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x00985074 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x00985078 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x0098507C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x00985080 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x00985084 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x00985088 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x0098508C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x00985090 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x00985094 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x00985098 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x0098509C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x009850A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x003FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x009850A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x000FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x009850A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x009850AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x009850B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x009850B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x009850B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x009850BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x009850C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x009850C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x009850C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE 0x009850CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_TEMP 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG3_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG4_BRICK_SPARE 0x009850D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG4_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG4_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG4_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG5_BRICK_SPARE 0x009850D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG5_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG5_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG5_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x009850D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x009850DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x009850E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x009850E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x009850E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x009850EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x009850F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x009850F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x009850F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x009850FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x00985100 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x00985104 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x00985108 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x0098510C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x00985110 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x00985114 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x00985118 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x0098511C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x00985120 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x00985124 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x00985128 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x0098512C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x00985130 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x00985134 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x00985138 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x0098513C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x00985140 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x00985144 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x00985148 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x0098514C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x00985150 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x00985154 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL 0x00985158 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT 14:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_START_TRM 31:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL_START_TRM_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1 0x009851DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x00985160 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x00985164 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x00985168 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x0098516C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x00985170 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x00985174 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x00985178 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x0098517C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x00985180 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE_INIT 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x00985184 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x00985188 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x0098518C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x00985190 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x00985194 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x00985198 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x0098519C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x009851A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x009851A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG 0x009851A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_FREEZE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_CMD_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_CMD_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_SAMPLE_COUNT 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALCFG_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009851B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009851B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009851BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009851C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009851C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009851C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009851CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009851D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR 0x009851D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x009851D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x009851FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x00985200 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x00985204 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x00985208 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x0098520C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x00985210 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x00985214 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x00985218 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG 0x0098521C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL 15:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0 0x00985224 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM 21:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1 0x00985228 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE1 0x00985030 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE1_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE1_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE2 0x00985034 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE2_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE2_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE3 0x00985038 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE3_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_DONT_USE3_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x009852C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x009852C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x009852CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x009852D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG6_BRICK_SPARE 0x009852D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG6_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE 0x009852D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE 0x009852DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG9_BRICK_SPARE 0x009852F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG9_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE 0x009852E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE 0x009852E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x00985700 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x00985704 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x00985708 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x0098570C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x00985710 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x00985714 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x00985718 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x0098571C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x00985720 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x00985724 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x00985728 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x0098572C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x00985730 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x00985734 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x00985738 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x0098573C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x00985740 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x00985744 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x00985748 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x0098574C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x00985750 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x00985754 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x00985758 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x0098575C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x00985760 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x00985764 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x00985768 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x0098576C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x00985770 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x00985774 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x00985778 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x0098577C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x00985780 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x00985784 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x00985788 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x0098578C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x00985790 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x00985794 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x00985798 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x0098579C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x009857A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x009857A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x009857A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x009857AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x009857B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x009857B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x009857B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x009857BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x009857C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x009857C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x009857C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x009857CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x009857D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x009857D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x009857D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x009857DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x009857E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x009857E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x009857E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x009857EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x009857F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x009857F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x009857F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x009857FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x00985800 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x00985804 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x00985808 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x0098580C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x00985810 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x00985814 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x00985818 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x0098581C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x00985860 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x00985864 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x00985868 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x0098586C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x00985870 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x00985874 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x00985878 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x0098587C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x00985880 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x00985884 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x00985888 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x0098588C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x00985890 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x00985894 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x00985898 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x0098589C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x009858A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x009858A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x009858A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x009858AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x009858B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x009858B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x009858B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x009858BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x009858D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x009858D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x009858D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x009858DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x009858E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x009858E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x009858E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x009858EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x009858F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x009858F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x009858F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x009858FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x00985900 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x00985904 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x00985908 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x0098590C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x00985910 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x00985914 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x00985918 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x0098591C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x00985920 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x00985924 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x00985928 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x0098592C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x00985930 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x00985934 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x00985938 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x0098593C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x00985940 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x00985944 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x00985948 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x0098594C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x00985950 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x00985954 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x00985958 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x0098595C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x00985960 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x00985964 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x00985968 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x0098596C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x00985970 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x00985974 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x00985978 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x0098597C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x00985980 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x00985984 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x00985988 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x0098598C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x00986600 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x00986604 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x00986608 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x0098660C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x00986610 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x00986614 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x00986618 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x0098661C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x00986620 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x00986624 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x00986628 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x0098662C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x00986630 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x00986634 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x00986638 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x0098663C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x00986640 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x00986644 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x00986648 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x0098664C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x00986650 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x00986654 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x00986658 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x0098665C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x00986660 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x00986664 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x00986668 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x0098666C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x00986670 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x00986674 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x00986678 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x0098667C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x00986680 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x00986684 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x00986688 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x0098668C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x00986690 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x00986694 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x00986698 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x0098669C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x009866A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x009866A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x009866A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x009866AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x009866B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x009866B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x009866B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x009866BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x009866C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x009866C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x009866C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x009866CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x009866D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x009866D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x009866D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x009866DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x009866E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x009866E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x009866E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x009866EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x009866F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x009866F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x009866F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x009866FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x00986700 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x00986704 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x00986708 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x0098670C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x00986710 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x00986714 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x00986718 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x0098671C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x00986720 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x00986724 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x00986728 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x0098672C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x00986730 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x00986734 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x00986738 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x0098673C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x00986740 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x00986744 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x00986748 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x0098674C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x00986750 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x00986754 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x00986758 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x0098675C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x00986760 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x00986764 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x00986768 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x0098676C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x00986770 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x00986774 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x00986778 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x0098677C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT 0x009867A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x009867A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT 0x009867A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x009867AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT 0x009867B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_DDLLCAL_LT_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x00985990 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x00985994 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x00985998 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x0098599C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x009859A0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x009859A4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x009859A8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x009859AC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x009859B0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x009859B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x009859B8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x009859BC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x009859C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x009859C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x009859C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x009859CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x009859D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x009859D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x009859D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x009859DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x009859E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x009859E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x009859E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x009859EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x00985FC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x00985FC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x00985FC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x00985FCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x00985FD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x00985FD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x00985FD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x00985FDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x00985FE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x00985FE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x00985FE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x00985FEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x00985FF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x00985FF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x00985FF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x00985FFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x00985820 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x00985824 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x00985828 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x0098582C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x00985830 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x00985834 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x00985838 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x0098583C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL 0x00985A00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_STARTVAL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_STARTVAL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SEL_ODD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SEL_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SEL_VREFU 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_OFFSET_CAL_CTRL_SEL_VREFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_MISC_CTRL 0x00985A04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_MISC_CTRL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x00985A10 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x00985A14 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x00985A18 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x00985A1C /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x00985A20 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x00985A24 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x00985A28 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x00985A2C /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x00985A30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x00985A34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x00985A38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x00985A3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x00985A40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x00985A44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x00985A48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x00985A4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x00985A50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x00985A54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x00985A58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x00985A5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x00985A60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x00985A64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x00985A68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x00985A6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x00985A70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x00985A74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x00985A78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x00985A7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x00985A80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x00985A84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x00985A88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x00985A8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00985A90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00985A94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00985A98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00985A9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00985AA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00985AA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00985AA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00985AAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00985AB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00985AB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00985AB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00985ABC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00985AC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00985AC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00985AC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00985ACC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00985AD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00985AD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00985AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00985ADC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00985AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00985AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00985AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00985AEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00985AF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00985AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00985AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00985AFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00985B00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00985B04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00985B08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00985B0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00985B10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00985B14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00985B18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00985B1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00985B20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00985B24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00985B28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00985B2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00985B30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00985B34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00985B38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00985B3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00985B40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00985B44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00985B48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00985B4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00985B50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00985B54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00985B58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00985B5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00985B60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00985B64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00985B68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00985B6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00985B70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00985B74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00985B78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00985B7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00985B80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00985B84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00985B88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00985B8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00985B90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00985B94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00985B98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00985B9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00985BA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00985BA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00985BA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00985BAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00985BB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00985BB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00985BB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00985BBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00985BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00985BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00985BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00985BCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00985BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00985BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00985BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00985BDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00985BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00985BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00985BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00985BEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00985BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00985BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00985BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00985BFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00985C00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00985C04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00985C08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00985C0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00985C10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00985C14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00985C18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00985C1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00985C20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00985C24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00985C28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00985C2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00985C30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00985C34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00985C38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00985C3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00985C40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00985C44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00985C48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00985C4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00985C50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00985C54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00985C58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00985C5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00985C60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00985C64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00985C68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00985C6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00985C70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00985C74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00985C78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00985C7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00985C80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00985C84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00985C88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00985C8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00985C90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00985C94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00985C98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00985C9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00985CA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00985CA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00985CA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00985CAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00985CB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00985CB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00985CB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00985CBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00985CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00985CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00985CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00985CCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00985CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00985CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00985CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00985CDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00985CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00985CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00985CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00985CEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00985CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00985CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00985CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00985CFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00985D00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00985D04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00985D08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00985D0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00985D10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00985D14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00985D18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00985D1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00985D20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00985D24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00985D28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00985D2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00985D30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00985D34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00985D38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00985D3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00985D40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00985D44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00985D48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00985D4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00985D50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00985D54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00985D58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00985D5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00985D60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00985D64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00985D68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00985D6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00985D70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00985D74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00985D78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00985D7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00985D80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00985D84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00985D88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00985D8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x00985DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x00985DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x00985DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x00985DAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x00985DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x00985DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x00985DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x00985DBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x00985DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x00985DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x00985DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x00985DCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x00985DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x00985DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x00985DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x00985DDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x00985DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x00985DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x00985DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x00985DEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x00985DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x00985DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x00985DF8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x00985DFC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLLCAL 0x00985E00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLLCAL 0x00985E04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLLCAL 0x00985E08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLLCAL 0x00985E0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLLCAL 0x00985E10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLLCAL 0x00985E14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLLCAL 0x00985E18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLLCAL 0x00985E1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF 0x00985E20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLLCAL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF 0x00985E24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF 0x00985E28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF 0x00985E2C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF 0x00985E30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF 0x00985E34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF 0x00985E38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF 0x00985E3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF 0x00985E40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF 0x00985E44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1 0x00985E48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2 0x00985E4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1 0x00985E50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2 0x00985E54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1 0x00985E58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2 0x00985E5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1 0x00985E60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2 0x00985E64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1 0x00985E68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2 0x00985E6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1 0x00985E70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2 0x00985E74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1 0x00985E78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2 0x00985E7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1 0x00985E80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2 0x00985E84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU 0x00985E88 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU 0x00985E8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU 0x00985E90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU 0x00985E94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU 0x00985E98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU 0x00985E9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU 0x00985EA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU 0x00985EA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD 0x00985EA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD 0x00985EAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD 0x00985EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD 0x00985EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD 0x00985EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD 0x00985EBC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD 0x00985EC0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD 0x00985EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT 0x00985F30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_TEMP_COEFF 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_TEMP_COEFF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_IBG_CNTL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_BG_CNTL 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_LV_CDBVAUXC 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_LV_CDBVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_LIMITER 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_CDBVAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BG_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB 0x00985F4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB 0x00985F40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB 0x00985F3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB 0x00985F44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS 0x00985F48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SUBP0_CK 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SUBP1_CK 23:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1 0x00985F50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0 0x00986780 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1 0x00986784 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2 0x00986788 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3 0x0098678C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0 0x00986790 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1 0x00986794 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2 0x00986798 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3 0x0098679C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING 0x00985F54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_RD_GAIN 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_RD_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_WR_GAIN 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_WR_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EDGE_BRLSHFT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EDGE_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_CENTER_BRLSHFT 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_CENTER_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_BLOCK_COUNT 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_BLOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EN 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_HUNT_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_HUNT_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_USE_CENTER_ONLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_USE_CENTER_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_HALF_RATE_EDC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_HALF_RATE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING 0x00985F58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_GAIN 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_ACCUM 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_ACCUM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT 19:11 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW 21:21 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF 28:22 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_VREF_EDGE_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_VREF_EDGE_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2 0x009867B4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_SHADOW_LOAD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_SHADOW_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_SHADOW_SELECT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_SHADOW_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_CDR_MASK 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING2_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1 0x009867B8 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFP_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFP_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFP_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFP_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFN_EVEN 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFN_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFN_ODD 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ1_VREFN_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2 0x009867BC /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x009867C8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x009867CC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x009867D0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x009867D4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x009867D8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x009867DC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x009867E0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x009867E4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x009867E8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x009867EC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x009867F0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x009867F4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x009867F8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x009867FC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x00986800 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x00986804 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG 0x00985F5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT 11:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW 14:14 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DQ_SEL 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DQ_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DIR_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DIR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW 27:27 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW 28:28 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1 0x00985F60 /* R--4R */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI 13:7 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_DQ_PI 20:14 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_DQ_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT 26:21 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x00985F64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x00985F68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x00985F6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x00985F70 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x00985F74 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x00985F78 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x00985F7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x00985F80 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14 0x00985F84 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE1 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE2 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE3 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE4 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE5 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE7 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_EDC_PIN_STATE_BYTE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_FORCE_PIN_STATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CFG14_FORCE_PIN_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC 0x00985F8C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_EN_X 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_EN_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SIGNAL_SEL_X 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SIGNAL_SEL_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_OFFSET_X 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_OFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SELECT_X 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SELECT_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_EN_Y 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_EN_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SIGNAL_SEL_Y 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SIGNAL_SEL_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_OFFSET_Y 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_OFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SELECT_Y 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HSDAC_SELECT_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0 0x009867C0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC0_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1 0x009867C4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_CMD_HSDAC1_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0 0x00985F90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1 0x00985F94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS 0x00985F98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_TERM 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_TERM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI 0x00985F9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_RX 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_TX 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_SPARE 31:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_INTERP_2UI_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x00985FA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x00985FA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x00985FA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x00985FAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x00985FB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x00985FB4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1 0x00985FB8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1__PRIV_LEVEL_MASK 0x009848FC /* */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_CDR_MASK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_SUPPORT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_EDC_TRACKING1_LOCK_SUPPORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK 0x00987C7C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_1_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG 0x00987C90 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SYNCMODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SYNCMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SYNCMODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SYNCMODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_LCKDET 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_LCKDET_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_LCKDET_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_LOCK_OVERRIDE 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_PLL_LOCK 5:5 /* R--UF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_FSTLCK 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_IDDQ 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE_BG 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_STOP_SYNCMUX 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_BYPASSPLL 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_BYPASSPLL_VCO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_BYPASSPLL_BYPASSCLK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL 0x00987C94 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF 0x00987C98 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_NDIV_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO 0x00987C9C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST 0x00987CA0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RFU 24:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG 0x00987CA4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK 27:21 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG1 0x00987CA8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG1_TX_EN 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_CFG1_TX_EN_INIT 0x00FFD98A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD1 0x00987CAC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD1_TX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD1_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD2 0x00987CB0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD2_RX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_BRICK_TEST_PWRD2_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE 0x00987CCC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG13_BRICK_SPARE 0x00987CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG13_BRICK_SPARE__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG 0x00987CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_INT_VREF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_INT_VREF_INIT 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1 0x00987CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK 7:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK 28:22 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2 0x00987CDC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW 10:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD 12:11 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1 0x00987CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREG14V_CTRL 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREG10V_CTRL 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG1_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0 0x00987CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1 0x00987CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL 6:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_RFU 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_HBMCDB_CFG1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0 0x00987CEC /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU_INIT 0x00000030 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG2 0x00987CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG2_SETUP 27:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBMPLL_CFG2_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG 0x00987C00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN 0x00987C04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX 0x00987C08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL 0x00987C0C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB 0x00987C10 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_RISE_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_FALL_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_TERM 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2 0x00987C14 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_RISE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_FALL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_SPARE 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3 0x00987C18 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4 0x00987C1C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5 0x00987C20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x00987C30 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x00987C34 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x00987C38 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x00987C3C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x00987C40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x00987C44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x00987C48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x00987C4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x00987C50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x00987C54 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x00987C58 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x00987C5C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x00987C60 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x00987C64 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2 0x00987C68 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3 0x00987C6C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG 0x00987D00 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_SYNC_MODE 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL 0x00987D04 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2 0x00987D08 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_SEL_TESTOUT 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_SETUP2 27:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_TESTMODE 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_REFMPLL_CFG2_TESTMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG 0x00987D20 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_CLAMP_P0 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_CLAMP_P0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_CLAMP_P0_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_CLAMP_P0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL 0x00987D24 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL 31:29 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2 0x00987D28 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2_SETUP2 11:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0 0x00987D40 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_LV_VAUXC 18:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_BW 22:19 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST 30:28 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1 0x00987D44 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CMD_VTT_SPARE 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CMD_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_BYTE_VTT_SPARE 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_BYTE_VTT_SPARE_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VTT_SPARE 21:20 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_CDB_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL 29:22 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL 0x00987D48 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_BG_CNTL 3:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IBG_CNTL 5:4 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IRX_CNTL 7:6 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IRX_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IRX_SRC_SEL 10:8 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IRX_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEMP_COEF 13:11 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_CDB_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_CDB_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_SEL 20:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_E_RES_CAL_CODE_IN 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_E_RES_CAL_CODE_IN_BYP_SEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL 26:22 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IBG_SRC_SEL 29:27 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CDBCTRL_IBG_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV 0x00987D4C /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_SPARE 10:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_PTRIM_OVRD 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_PTRIM_OVRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_MODE_SWITCH 13:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_MODE_SWITCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_MODE_SWITCH_DRAMPLL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_MODE_SWITCH_ONESOURCE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_MODE_SWITCH_REFMPLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_DPD 16:16 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_DPD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_DPD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE 17:17 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL 18:18 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2 0x00987D50 /* RW-4R */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2__PRIV_LEVEL_MASK 0x00987C7C /* */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM 5:3 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM 8:6 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_BGAP_TRIM 11:9 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_BGAP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_E_TRIM 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_E_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXC 16:13 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXC_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXP 20:17 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VAUXP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VCLAMP 24:21 /* RWIUF */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VCLAMP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_1_FBIO_VTT_CTRL2_CDB_VCLAMP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK 0x00988168 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK 0x00988148 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK 0x0098814C /* RW-4R */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_HISECTESTCMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK 0x00988170 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_ecc" /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK 0x009881B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK 0x009881B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK 0x0098A578 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK 0x0098800C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK 0x0098A250 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK 0x0098886C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMID_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_SPARE 0x00988050 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SPARE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SPARE_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_INIT 0xFF001040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_OFIFO_OFFSET 5:0 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_OFIFO_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_CMDFF_DEPTH 12:8 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_CMDFF_DEPTH_INIT 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_CMDFF_DEPTH_MAX 0x00000010 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_CMDFF_DEPTH_SAFE 0x00000004 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_SYNC_PULSE_POLARITY 13:13 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_SYNC_PULSE_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_OFIFO_OFFSET_POLARITY 14:14 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_OFIFO_OFFSET_POLARITY_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_PDEN_OFFSET 19:16 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_PDEN_OFFSET_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_L2_CRC_MODE 20:20 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_L2_CRC_MODE_INIT 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_VS_DELAY 23:21 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_VS_DELAY_INIT 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BIT30 30:30 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BIT30_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BUG765178_TEST_MODE 31:31 /* ----F */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BUG765178_TEST_MODE_INIT 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BUG765178_TEST_MODE_SKIP 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE_BITS_BUG765178_TEST_MODE_RUN 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_SPARE2 0x009880CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_SPARE2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SPARE2_BITS 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SPARE2_BITS_INIT 0xFFFF0000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FALCON_MONITOR 0x00988054 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FALCON_MONITOR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FALCON_MONITOR_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FALCON_MONITOR_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER 0x00988064 /* R--4R */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_DEV 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_DEV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_ECO 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_ECO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_MINOR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_MINOR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_MAJOR 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FALCON_CTRL_VER_MAJOR_INIT 0x00000004 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD 0x00988060 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CFG_PWRD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_80 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_TX_FABRIC_PWRD_HOLDOFF_120 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_RCVR_PWRD_DLY 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_RCVR_PWRD_DLY_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_BLCG_USE_TRAINING_IDLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_BLCG_USE_TRAINING_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG_PWRD_BLCG_USE_TRAINING_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0 0x00988080 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DEBUG_0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_0_MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_MRS_256 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_MRS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PERIODIC_QRST 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PERIODIC_QRST_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PERIODIC_QRST_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_SPARE0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_SPARE0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_SPARE0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_PIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_PIN_CMD 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_PIN_RESET 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_PIN_DEBUG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_MODE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_MODE_WRITE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_ODT_MODE_NOTREAD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_USE_CFG0_BL8_HBM 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_USE_CFG0_BL8_HBM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_USE_CFG0_BL8_HBM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BL16EDC_SET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BL16EDC_SET_EVEN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BL16EDC_SET_ODD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_WFT_IDLE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_WFT_IDLE_NEW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_WFT_IDLE_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FB_IDLE_NOPBR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FB_IDLE_NOPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FB_IDLE_NOPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HANDSHAKE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HANDSHAKE_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HANDSHAKE_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FORCE_FULL_MEMREF 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FORCE_FULL_MEMREF_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_FORCE_FULL_MEMREF_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_R2P_BL_ADJUST 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_R2P_BL_ADJUST_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_R2P_BL_ADJUST_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_POST_SP_TR 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_POST_SP_TR_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_POST_SP_TR_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_TOGGLE_FIX 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_TOGGLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_TOGGLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HWACPDIDLE_FIX 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HWACPDIDLE_FIX_NOUSE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DISABLE_HWACPDIDLE_FIX_USE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_MODE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_MODE_SDR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_MODE_DDR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DEBUGPIN_CHSEL_IN_SDR_CH1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PRI_REG_UPDATE_EXT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PRI_REG_UPDATE_EXT_15 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_PRI_REG_UPDATE_EXT_31 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_REFCFG_REQ_PENDING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_REFCFG_REQ_PENDING_FIXED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_REFCFG_REQ_PENDING_OLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BECS_ACK 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BECS_ACK_LEVEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_BECS_ACK_PULSE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DRAM_ACK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DRAM_ACK_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_DRAM_ACK_IDLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_TREFI_UPDATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_0_TREFI_UPDATE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_0_TREFI_UPDATE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_1 0x00988084 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DEBUG_1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_1_L2_ECC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_1_L2_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_1_L2_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DEBUG_2 0x0098A340 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_2_XBAR_ASR_OK 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_2_XBAR_ASR_OK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_2_XBAR_ASR_WAKEUP 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_2_XBAR_ASR_WAKEUP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_2_STOP_FB_REQ 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_2_STOP_FB_REQ_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_2_STOP_FB_ACK 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_2_STOP_FB_ACK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_SUBPIDLE(i) (0x0098A344+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_DEBUG_SUBPIDLE__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_SUBPIDLE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_SUBPIDLE_IDLES 27:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_SUBPIDLE_IDLES_INIT 0x0FFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_PAIDLE 0x0098A34C /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_PAIDLE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_PAIDLE_IDLES 21:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_PAIDLE_IDLES_INIT 0x003FFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0 0x0098A350 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0_EN_COUNT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0_EN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0_CLR_COUNT 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_0_CLR_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1 0x0098A354 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_1 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_2 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_3 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DEBUG_CTRL_1_SEL_3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_BASE 0x0098A358 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_BASE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_BASE 0x0098A35C /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_BASE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_BASE_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_BASE_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_0 0x0098A360 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_0 0x0098A364 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_1 0x0098A368 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_1 0x0098A36C /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_2 0x0098A370 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_2 0x0098A374 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_2_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_2_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_3 0x0098A378 /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_LO_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_3 0x0098A37C /* R--4R */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_3_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DEBUG_COUNT_HI_3_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP 0x009881DC /* R--4R */ #define NV_PFB_FBPA_MC_2_ROW_REMAP__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_ENABLE 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_ENABLE_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_ENABLE_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD(i) (0x009881F0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ENTRY_VLD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ENTRY_VLD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ROW 25:9 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ROW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_RD_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR(i) (0x009881F8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR__PRIV_LEVEL_MASK 0x0098800C /* */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_TRIGGER 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_TRIGGER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_EXT_BANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_EXT_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_BANK 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_ROW 25:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_SID 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_ENTRY 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ROW_REMAP_WR_ENTRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD 0x00988090 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TESTCMD__PRIV_LEVEL_MASK 0x0098814C /* */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LPDDR4_SELF_REF_ENTRY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LPDDR4_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CKE_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CS1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_CAS_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_HBM_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_HBM_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_HBM_SELF_REF_EXIT1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_WE_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR5_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_LEGACY_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_RES_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_4_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR6_SELF_REF_ENTRY1 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR6_SELF_REF_ENTRY2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_BANK_DDR6_SELF_REF_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR 25:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_HBM_SELF_REF_ENTRY3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_ADR_UPPER_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR5_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_LEGACY_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_HBM_SELF_REF_EXIT2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_LDFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_GO_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR5_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LEGACY_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_HBM_SELF_REF_ENTRY3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_HBM_SELF_REF_EXIT1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_HBM_SELF_REF_EXIT2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_LDFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_HOLD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT 0x00988094 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT__PRIV_LEVEL_MASK 0x0098814C /* */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_VLD_DRAM1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ADR_DRAM1 10:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ADR_DRAM1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY1 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_ENTRY2 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ADR_DRAM1_DDR6_SELF_REF_EXIT 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DEBUG 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DEBUG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DEBUG_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ODT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ODT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ODT_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ODT_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_RW_CMD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_RW_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_RW_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_MRS_CMD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_MRS_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_MRS_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DR_CMD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DR_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_DR_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_4CK_CMD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_4CK_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_4CK_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_LAM_CMD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_LAM_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_LAM_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_CMD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_ACT_CMD_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_SID 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_SID_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_SID_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_SID_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1 0x00988154 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1__PRIV_LEVEL_MASK 0x0098814C /* */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_ENTRY 0x00018018 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR5_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_HBM_SELF_REF_ENTRY3 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT1 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_HBM_SELF_REF_EXIT2 0x00001803 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY1 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_ENTRY2 0x00000400 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LEGACY_MIRR_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LPDDR4_SELF_REF_EXIT 0x00014014 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_LDFF 0x00000800 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB0_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_ENTRY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_LPDDR4_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_ENTRY2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_CSB1_DDR6_SELF_REF_EXIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_ENTRY2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TESTCMD_EXT_1_USE_ADR_DDR6_SELF_REF_EXIT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0 0x009880A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1 0x009880A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2 0x009880A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3 0x009880AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP0BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0 0x009880B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE0_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1 0x009880B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE1_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2 0x009880B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE2_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3 0x009880BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ4_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ4_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ5_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ6_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ6_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ7_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BIT_SUBP1BYTE3_DQ7_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI 0x009880C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE0_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE1_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE2_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE3_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_DBI_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC 0x009880C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP0BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE0_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE0_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE0_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE1_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE1_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE1_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE2_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE2_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE2_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE3_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE3_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_ECC_SUBP1BYTE3_MAX 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE 0x009880C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCK01 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCKB01 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCK23 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCKB23 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP0_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCK01 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCKB01 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCK23 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCK23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCKB23 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SWIZZLE_BYTE_SUBP1_WCKB23_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM 0x00988100 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PM__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC0 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT0 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT1 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ0 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ2 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC2 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ2 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ3 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ4 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ5 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC4 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT4 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT5 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ4 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ6 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRTYREQ7 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC6 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SLC7 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT6 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDAT7 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ6 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READREQ7 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_SUBP0 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_SUBP1 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_CH0_SUBP0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_CH0_SUBP1 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_CH1_SUBP0 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_ACT_CH1_SUBP1 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_BANK_ACT_SUBP0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_BANK_ACT_SUBP1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_NO_ACT_SUBP0 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_NO_ACT_SUBP1 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP0 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACTARB_NUM_RW_BANKS_SUBP1 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BANKQ_EMPTY_SUBP0 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BANKQ_EMPTY_SUBP1 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BA_OUTPUT 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BA_SIGS 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_CKG0 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_CKG1 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRARB_SUBP0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DIRARB_SUBP1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_BANKS_SUBP0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_BANKS_SUBP1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_EXTRA_SUBP0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_EXTRA_SUBP1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RWALL 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_SUBP0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_SUBP1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_CH0_SUBP0 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_CH0_SUBP1 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_CH1_SUBP0 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RW_CH1_SUBP1 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_SUBP0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_SUBP1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_CH0_SUBP0 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_CH0_SUBP1 0x00000043 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_CH1_SUBP0 0x00000044 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_CH1_SUBP1 0x00000045 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_CH0_SUBP0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_CH0_SUBP1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_CH1_SUBP0 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_CH1_SUBP1 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_PART2_SUBP0 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_PART2_SUBP1 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_PP_SUBP0 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_WAIT_PP_SUBP1 0x0000004D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ECC_CH0_SUBP0 0x0000004E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ECC_CH0_SUBP1 0x0000004F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ECC_CH1_SUBP0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ECC_CH1_SUBP1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_FT_IDLE_SUBP0 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_FT_IDLE_SUBP1 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_CH0_SUBP0 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_CH0_SUBP1 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_CH1_SUBP0 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_CH1_SUBP1 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SUBP0 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_IDLE_SUBP1 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INFLIGHT_READ_COUNT 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INFLIGHT_READ_COUNT_VC0 0x0000005C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INFLIGHT_READ_COUNT_VC1 0x0000005D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INFLIGHT_READ_COUNT_VC2 0x0000005E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_INFLIGHT_WRITE_COUNT 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_OUT_READS 0x00000060 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_OUT_WRITES 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_PENDING_REFRESH_SUBP0 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_PENDING_REFRESH_SUBP1 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_PART2_SUBP0 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_PART2_SUBP1 0x00000065 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_SUBP0 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_SUBP1 0x00000067 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP0 0x00000068 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC0_REQ_FIFO_SUBP1 0x00000069 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP0 0x0000006A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC1_REQ_FIFO_SUBP1 0x0000006B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP0 0x0000006C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RDBANKQ_VC2_REQ_FIFO_SUBP1 0x0000006D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READARB_SUBP0 0x0000006E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READARB_SUBP1 0x0000006F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_READARB_VC 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_REFSB_SUBP0 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_REFSB_SUBP1 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT0_PART2_SUBP0 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT0_PART2_SUBP1 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT0_SUBP0 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT0_SUBP1 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT1_PART2_SUBP0 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT1_PART2_SUBP1 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT1_SUBP0 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RFT1_SUBP1 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_STAT_CH0_SUBP0 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_STAT_CH0_SUBP1 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_STAT_CH1_SUBP0 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_STAT_CH1_SUBP1 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_SINGLE_PASS_SUBP0 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_SINGLE_PASS_SUBP1 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_STATIC_PATTERN_555_12_GROUP 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_STATIC_PATTERN_AAA_12_GROUP 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_SUBP01_TRAFFIC 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_SUBP01_TRAFFIC_CH0 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_SUBP01_TRAFFIC_CH1 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WFT0_SUBP0 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WFT0_SUBP1 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WFT1_SUBP0 0x00000088 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WFT1_SUBP1 0x00000089 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP0 0x0000008A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRBANKQ_REQ_FIFO_SUBP1 0x0000008B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRBANKQ_SUBP0 0x0000008C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRBANKQ_SUBP1 0x0000008D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEARB_SUBP0 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEARB_SUBP1 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_UTIL_SUBP0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_UTIL_SUBP1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RCMD_CH0_SUBP0 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RCMD_CH0_SUBP1 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RCMD_CH1_SUBP0 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_DRAMC_RCMD_CH1_SUBP1 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_SUBP0 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_SUBP1 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_CH0_SUBP0 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_CH0_SUBP1 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_CH1_SUBP0 0x0000009A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BUCKET_CH1_SUBP1 0x0000009B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ISO_TRACKING0_SUBP0 0x0000009C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ISO_TRACKING0_SUBP1 0x0000009D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ISO_TRACKING1_SUBP0 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ISO_TRACKING1_SUBP1 0x0000009F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC0_SUBP0 0x000000A0 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC0_SUBP1 0x000000A1 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC1_SUBP0 0x000000A2 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC1_SUBP1 0x000000A3 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC2_SUBP0 0x000000A4 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_BW_TRACKING_VC2_SUBP1 0x000000A5 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_REQ_FIFO_SG0 0x000000A6 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_REQ_FIFO_SG1 0x000000A7 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_REQ_FIFO_SG2 0x000000A8 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_WRITEPULL_REQ_FIFO_SG3 0x000000A9 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_RETURN_FIFO_SG0 0x000000AA /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_RETURN_FIFO_SG1 0x000000AB /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_RETURN_FIFO_SG2 0x000000AC /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_RR_RETURN_FIFO_SG3 0x000000AD /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR0_SUBP0 0x000000AE /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR0_SUBP1 0x000000AF /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR1_SUBP0 0x000000B0 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR1_SUBP1 0x000000B1 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR2_SUBP0 0x000000B2 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR2_SUBP1 0x000000B3 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR3_SUBP0 0x000000B4 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR3_SUBP1 0x000000B5 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR4_SUBP0 0x000000B6 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SELECT_ACPD_ASR4_SUBP1 0x000000B7 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP(i) (0x009881E0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_SUBP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_SUBP__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_SUBP_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_SUBP_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_ACT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_ACT_CH0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_ACT_CH1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_BANK_ACT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_NO_ACT 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACTARB_NUM_RW_BANKS 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BANKQ_EMPTY 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DIRARB 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_CH0 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_CH1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_BANKS 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_EXTRA 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_RW 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_RW_CH0 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_RW_CH1 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_WAIT_CH0 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_WAIT_CH1 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_WAIT_PART2 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_WAIT_PP 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ECC_CH0 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ECC_CH1 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_FT_IDLE 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_IDLE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_IDLE_CH0 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_IDLE_CH1 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_PENDING_REFRESH 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RDBANKQ 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RDBANKQ_PART2 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RDBANKQ_VC0_REQ_FIFO 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RDBANKQ_VC1_REQ_FIFO 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RDBANKQ_VC2_REQ_FIFO 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_READARB 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_REFSB 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RFT0 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RFT0_PART2 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RFT1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RFT1_PART2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RR_STAT_CH0 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_RR_STAT_CH1 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_SINGLE_PASS 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WFT0 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WFT1 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WRBANKQ 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WRBANKQ_REQ_FIFO 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WRITEARB 0x0000002E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_WRITEPULL_UTIL 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_RCMD_CH0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_DRAMC_RCMD_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BUCKET 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BUCKET_CH0 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BUCKET_CH1 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ISO_TRACKING0 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ISO_TRACKING1 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BW_TRACKING_VC0 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BW_TRACKING_VC1 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_BW_TRACKING_VC2 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACPD_ASR0 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACPD_ASR1 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACPD_ASR2 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACPD_ASR3 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_SUBP_SELECT_ACPD_ASR4 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE(i) (0x00988180+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_HI(i) (0x0098A500+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_HI__SIZE_1 12 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_HI__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_HI_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_HI_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_WINDOW(i) (0x009881D0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_WINDOW__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_WINDOW__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_WINDOW_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_WINDOW_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_CTL 0x009881D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_CTL__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_CTL_INVERT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_CAPTURE_CTL_INVERT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET(i) (0x0098A530+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_BUCKET__SIZE_1 11 /* */ #define NV_PFB_FBPA_MC_2_PM_BUCKET__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL 0x0098A55C /* RW-4R */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE_RD_CMD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE_WR_CMD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE_COL_CMD 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE_ANY_CMD 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_BUCKET_CTL_TYPE_ISO_TRACKING 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_CTL 0x0098A560 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PM_CTL__PRIV_LEVEL_MASK 0x009881B0 /* */ #define NV_PFB_FBPA_MC_2_PM_CTL_ISO_SUBID_MSB_INDEX 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_CTL_ISO_SUBID_MSB_INDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PM_CTL_ISO_SUBID_MSB_INDEX_MAX 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_REG_CTL 0x0098A564 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REG_CTL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REG_CTL_FBIO_NOACK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REG_CTL_FBIO_NOACK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REG_CTL_FBIO_NOACK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_ASR_NUM(i) (0x00988110+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_ASR_NUM__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_NUM__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_NUM_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_ASR_NUM_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_ASR_CYCCNT(i) (0x00988118+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_ASR_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_CYCCNT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_ASR_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_ASR_MAXCYC(i) (0x00988120+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_PM_ASR_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_MAXCYC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PM_ASR_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_PM_ASR_MINCYC(i) (0x00988128+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_PM_ASR_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_MINCYC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASR_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PM_ASR_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_CYCCNT(i) (0x00988130+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_CYCCNT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_CYCCNT_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_CYCCNT_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MAXCYC(i) (0x00988138+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MAXCYC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MAXCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MAXCYC_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MINCYC(i) (0x00988140+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MINCYC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MINCYC_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PM_ASRSTALL_MINCYC_VALUE_INIT 0xFFFFFFFF /* R-I-V */ #define NV_PFB_FBPA_MC_2_ASRCTRL_NONISO 0x00988150 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASRCTRL_NONISO__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASRCTRL_NONISO_THRESHOLD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASRCTRL_NONISO_THRESHOLD_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL 0x00988160 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_10 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_11 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_12 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_13 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_14 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_15 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_PERIOD_16 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_EN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_CTRL_INTERVAL_TIMER_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_FBPS 0x00988164 /* RW-4R */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_FBPS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_FBPS_V_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_LTCS 0x0098816C /* RW-4R */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_LTCS_V 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NUM_ACTIVE_LTCS_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE0 0x00988174 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPRE0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ0_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ1_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ2_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE0_DQ3_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE1 0x00988178 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPRE1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ4_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ5_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ6_INIT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE1_DQ7_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE2 0x0098817C /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPRE2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPRE2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE2_DBI_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPRE2_TR_PATTERN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPRE2_TR_PATTERN_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST0 0x009881B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPOST0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ0_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ1_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ2_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST0_DQ3_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST1 0x009881BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPOST1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ4_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ5_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ6_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST1_DQ7_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_WPOST2 0x009881C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WPOST2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WPOST2_DBI 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WPOST2_DBI_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0 0x00988200 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CFG0__PRIV_LEVEL_MASK 0x0098A250 /* */ #define NV_PFB_FBPA_MC_2_CFG0_BL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_BL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_BL_BL4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_BL_BL8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_BL_BL16 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_EXTBANK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_EXTBANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_EXTBANK_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_EXTBANK__PROD_C_SINGLE_SIDED_MEM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_EXTBANK__PROD_C_DUAL_SIDED_MEM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_X8 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_X8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_X8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_CA_RETURN_TO_ZERO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_CA_RETURN_TO_ZERO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_CA_RETURN_TO_ZERO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_HBM_CMD_PARITY_OVERRIDE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_HBM_CMD_PARITY_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_HBM_CMD_PARITY_OVERRIDE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_RATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_RATE_HALF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_RATE_FULL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_GAPLESS_WTR 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_GAPLESS_WTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_GAPLESS_WTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACPD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACPD_NO_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACPD_ACTIVE_POWERDOWN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ATR__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_DATA_SCRAMBLE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_DATA_SCRAMBLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_DATA_SCRAMBLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_SYNC 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_LOW_POWER 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_LOW_POWER_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_LOW_POWER_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_ABI 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_BURST_LENGTH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_BURST_LENGTH_4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_BURST_LENGTH_8 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_DM_ON_ADR 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_DM_ON_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_DM_ON_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_TIMING_UNIT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_TIMING_UNIT_DRAMCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_TIMING_UNIT_DRAMDIV2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_CMD_PARITY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_CMD_PARITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_CMD_PARITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_ODT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_CLAMSHELL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_CLAMSHELL_X32 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_CLAMSHELL_X16 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_EARLY_VALUE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_EARLY_VALUE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_EDC_EARLY_VALUE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_BG_8 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_BG_8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_BG_8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_PRE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_PRE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_AUTO_PRE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_SAME_QUSE_TWO_RANKS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_SAME_QUSE_TWO_RANKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_SAME_QUSE_TWO_RANKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_RDEDC 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_RDEDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_RDEDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_WREDC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_WREDC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_WREDC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_REPLAY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_REPLAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_REPLAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_MS01_ECC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_MS01_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_MS01_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG0_DRAM_ACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1 0x00988204 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CFG1__PRIV_LEVEL_MASK 0x00988148 /* */ #define NV_PFB_FBPA_MC_2_CFG1_SUBP 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_SUBP_256B 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_SUBP_512B 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_SUBP_1KB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_SUBP_2KB 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_AP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A8 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A12 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_AP_A13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_STACK 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_STACK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_STACK_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_STACK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_COL_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_COL_15 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWA_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_10 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_11 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_12 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_13 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_14 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_15 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_16 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_ROWB_17 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_BANK 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_BANK_2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_BANK_3 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_BANK_4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_BG_8_OVR 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_BG_8_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_BG_8_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_BG 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_ROW_BG 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_ROW_BG_2 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_ROW_BG_4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CFG1_NUM_BANKS_PER_ROW_BG_8 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CSTATUS 0x0098820C /* R--4R */ #define NV_PFB_FBPA_MC_2_CSTATUS__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_RAMAMOUNT 16:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_RAMAMOUNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CSTATUS_OVERRIDE 0x0098A57C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CSTATUS_OVERRIDE__PRIV_LEVEL_MASK 0x0098A578 /* */ #define NV_PFB_FBPA_MC_2_CSTATUS_OVERRIDE_RAMAMOUNT 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CSTATUS_OVERRIDE_RAMAMOUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL 0x00988210 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFCTRL__PRIV_LEVEL_MASK 0x0098A250 /* */ #define NV_PFB_FBPA_MC_2_REFCTRL_PUT 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL_PUT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL_GET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL_GET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL_RESET 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL_RESET_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL_RESET_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFCTRL_VALID 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL_VALID_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL_VALID_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ 0x00988214 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ZQ__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ZQ_CL_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_CL_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_CS_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_CS_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_CL_PERIODIC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_CL_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_CL_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_CS_PERIODIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_CS_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_CS_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_CH 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_CH_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_CH_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_RANK 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_RANK_PARALLEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_PERIODIC_RANK_SERIAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ZQ_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ZQ_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ZQ_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN 0x00988218 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PIN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PIN_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_CKE_POWERDOWN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_DQM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_DQM_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_DQM_INACTIVE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_RESET 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_RESET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_RESET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_CKE_POLARITY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_CKE_POLARITY_ACTIVE_HI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_CKE_POLARITY_ACTIVE_LO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_A0 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_A0_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_A0_LOW 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_A0_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_WDQS_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_WDQS_MODE_RETURN_TO_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_WDQS_MODE_RETURN_TO_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PIN_WDQS_MODE_FREERUNNING 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_PIN_DBI 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PIN_DBI_X8 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD 0x0098821C /* RW-4R */ #define NV_PFB_FBPA_MC_2_PAD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PAD_CKE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_CKE_TRISTATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_CKE_NORMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_CKE__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_CMD27 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_CMD27_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_CMD27_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_CMD28 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_CMD28_TRISTATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_CMD28_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_CHANNEL_PULLDN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_CHANNEL_PULLDN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_CHANNEL_PULLDN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_INPUT_DRIVER_CTRL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_INPUT_DRIVER_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_INPUT_DRIVER_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PAD_DBI 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PAD_DBI_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PAD_DBI_OVERRIDE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING 0x009883F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING_ACT2PDEN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING_ACT2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING_ACT2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING_PCHG2PDEN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING_PCHG2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING_PCHG2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING_AR2PDEN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING_AR2PDEN_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING_AR2PDEN_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING_DQRQPOP 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING_DQRQPOP_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING_DQRQPOP_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING_NOP2MRS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING_NOP2MRS_CONFIG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING_NOP2MRS_TIMING 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0 0x00988220 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING0_RC 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RFC 22:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RFC_MAX 0x000003FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RAS 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RAS_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1 0x00988224 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2W__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2R 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING1_W2R_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2R_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2R_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2R__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2P 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING1_R2P_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2P_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_R2P__PROD_C_SAMSUNG_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2P 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING1_W2P_18 0x00000012 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2P_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2P_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING1_W2P__PROD_C_SAMSUNG_DDR3 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2 0x00988228 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING2_RD_RCD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING2_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING2_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_RD_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_RD_RCD__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WR_RCD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING2_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING2_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WR_RCD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WR_RCD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_RRD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING2_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING2_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_RRD_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_RRD__PROD_C_SAMSUNG_DDR3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV__PROD_C_WL1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV__PROD_C_WL6 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING2_WDV__PROD_C_SAMSUNG_DDR3 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3 0x0098822C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE__PROD_C_CL11 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QUSE__PROD_C_SAMSUNG_DDR3 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST__PROD_C_CL11 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QRST__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QSAFE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING3_QSAFE_17 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING3_QSAFE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_QSAFE_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV_60 0x0000003C /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV_27 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV_MIN 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV_MAX 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV__PROD_C_CL11 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING3_RDV__PROD_C_SAMSUNG_DDR3 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4 0x00988230 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2WR 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2WR_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2WR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2WR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2WR__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2RD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2RD_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2RD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2RD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEX2RD__PROD_C_SAMSUNG_DDR3 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW_40 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_FAW__PROD_C_SAMSUNG_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_MSB 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING4_PDEN2PDEX_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING5 0x00988234 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING5_PCHG2PDEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING5_PCHG2PDEN_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING5_PCHG2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_PCHG2PDEN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_PCHG2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_RW2PDEN 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING5_RW2PDEN_13 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING5_RW2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_RW2PDEN_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_RW2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_ACT2PDEN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING5_ACT2PDEN_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING5_ACT2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_ACT2PDEN_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_ACT2PDEN__PROD_C_SAMSUNG_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_AR2PDEN 31:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING5_AR2PDEN_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING5_AR2PDEN_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_AR2PDEN_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING5_AR2PDEN__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6 0x00988238 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING6_PPD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING6_PPD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING6_BUS_W2R 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING6_BUS_W2R_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING6_BUS_W2R_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_DRAMC 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_DRAMC_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_DRAMC_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO_70 0x00000046 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO_20 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING6_CMD2MCIDLE_FBIO_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING7 0x0098823C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING7_REXT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING7_REXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING7_WEXT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING7_WEXT_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING7_ATR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATR_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATRLEN 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING7_ATRLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATRLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING7_ATRLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8 0x00988240 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING8__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING8_ODT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING8_ODT_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING8_ODT_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_ODT_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_ODTLEN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING8_ODTLEN_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_ODTLEN_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING8_ODTLEN_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_QPOP_OFFSET 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING8_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_QPOP_OFFSET_ELEVEN 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING8_QPOP_OFFSET_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_RPRE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING8_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING8_RPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_WPRE 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING8_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING8_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING8_WPRE_MAX 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING9 0x00988244 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING9__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDL_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING9_CCDS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_ADR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_ADR_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_WCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_WCK_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_WREDC 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING9_QPOP_OFFSET_WREDC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10 0x00988248 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING10__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2TR 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2TR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_LTLTR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_LTLTR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_LTL7TR 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_LTL7TR_4 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_MRD 22:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_MRD_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS_MSB2 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS_MSB2_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_REFTR 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_REFTR_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_REFTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING10_REFTR_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2TR_MSB 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2TR_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS_MSB 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING10_WCK2MRS_MSB_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11 0x0098824C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING11__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING11_ADZ 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING11_ADZ_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11_WTR_RCD 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING11_WTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11_WTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_WTR_RCD_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTR_RCD 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING11_LTR_RCD_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTR_RCD_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTRTR 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING11_LTRTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTRTR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11_LTRTR_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_KO 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING11_KO_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING11_KO_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING11_KO_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING12 0x00988250 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING12__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING12_RDCRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING12_RDCRC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING12_CKE 9:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING12_CKE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING12_CKE_5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING12_CKSRE 13:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING12_CKSRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING12_CKSRE_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING12_LOCKPLL 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING12_LOCKPLL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING12_LOCKPLL_3000 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING12_LOCKPLL_MAX 0x00003FFF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13 0x00988254 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING13__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK_5 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK_MSB 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASREX2CLK_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD_MSB 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX_MSB 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD_120 0x00000078 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2NRD__PROD_C_SAMSUNG_DDR3 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX_5K 0x00001388 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX_MIN 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX_MAX 0x0000FFFF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING13_ASR2ASREX__PROD_C_SAMSUNG_DDR3 0x00004E20 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING14 0x00988258 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING14__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING14_ZQCS 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING14_ZQCS_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING14_ZQCL 17:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING14_ZQCL_100 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING15 0x0098825C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING15__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING15_RDRET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING15_RDRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING15_WRRET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING15_WRRET_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING15_RDINTRP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING15_RDINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING15_WRINTRP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING15_WRINTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING16 0x00988260 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING16__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING16_RDFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING16_RDFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING16_WRFLUSH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING16_WRFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING16_RP 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING16_RP_10 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING16_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING16_RP_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING16_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING16_WCK_QRST 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING16_WCK_QRST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING17 0x00988264 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING17__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING17_RDRET_PRE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING17_RDRET_PRE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING17_WCK2RDWCK 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING17_WCK2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING17_MRS2RDWCK 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING17_MRS2RDWCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING18 0x00988268 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING18__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING18_WRCRCFLUSH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING18_WRCRCFLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING18_REXT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING18_REXT_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING18_QUSE_SETTLE 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING18_QUSE_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING18_DLCELL_SETTLE 29:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING18_DLCELL_SETTLE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING19 0x0098826C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING19__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING19_QRST_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING19_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING19_QRST_FLUSH 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING19_QRST_FLUSH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING19_MPRR 16:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING19_MPRR_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING20 0x0098828C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING20__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING20_RD_REFRESH 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING20_RD_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING20_WR_REFRESH 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING20_WR_REFRESH_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21 0x00988390 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING21__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_FORCE_FULL 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_FORCE_FULL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_FORCE_FULL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DUAL_REQUEST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DUAL_REQUEST_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DUAL_REQUEST_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DELAYED_THRESHOLD 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DELAYED_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_FULL_REF_PERIOD 19:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_FULL_REF_PERIOD_INIT 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DISPATCH_PERIOD 31:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING21_REFSB_DISPATCH_PERIOD_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING22 0x00988394 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING22__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBA_INIT 0x00000032 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBR 17:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBR_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBA_MSB 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING22_RFCSBA_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23 0x0098839C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING23__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING23_CCDR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING23_CCDR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23_CCDR_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING23_RD_RANK_SEL_DELAY 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING23_RD_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_RANK_SEL_DELAY 17:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_RANK_SEL_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDL_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDS_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING23_WR_CCDS_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24 0x009883E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING24__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING24_RRDL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING24_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING24_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24_RRDL_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24_CCDMW 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING24_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING24_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24_CCDMW_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING24_LPDDR4_RDV_OFFSET 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING24_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING24_ABPA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING24_ABPA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING24_XS_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING24_XS_OFFSET_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING25 0x009883EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING25__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING25_ZQCAL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING25_ZQCAL_1_US 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING25_MRRW 21:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING25_MRRW_64 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING25_MRRWL 30:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING25_MRRWL_256 0x00000100 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING26 0x0098A4E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING26__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING26_RFC_DLR 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING26_RFC_DLR_58 0x0000003A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING26_RFC_DLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING26_RFC_DLR_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING27 0x0098A4E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING27__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING27_REFSR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING27_REFSR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING27_REFSR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING28 0x0098A4E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING28__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING28_WRIDON 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING28_WRIDON_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING28_WRIDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING28_WRIDOFF_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING28_NOP2QPOP 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING28_NOP2QPOP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING28_NOP2MRS 22:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING28_NOP2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING28_TKO2MRS 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING28_TKO2MRS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING29 0x0098A4EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING29__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING29_TDCC1 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING29_TDCC1_INIT 0x00000BB8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING29_TDCC2 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING29_TDCC2_INIT 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING30 0x0098A4FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING30__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING30_FB_FBIO_DRAM_IDLE_DELAY 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_INIT 0x0000013C /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_GDDR6 0x0000013C /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_SDDR4 0x00000278 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING30_FB_FBIO_DRAM_IDLE_DELAY_HBM2 0x0000009E /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING30_FBIO_CKE_CKOFF_SKEW 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING30_FBIO_CKE_CKOFF_SKEW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TIMING31 0x0098A4F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TIMING31__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING31_XSMRS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TIMING31_XSMRS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_0 0x0098A4F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_POWER_0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRUP_RD_INTERP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRUP_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRDN_RD_INTERP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRDN_RD_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRUP_WR_INTERP 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRUP_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRDN_WR_INTERP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_0_OFFSET_PWRDN_WR_INTERP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_1 0x0098A4F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_POWER_1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRUP_RCVR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRUP_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRDN_RCVR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRDN_RCVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRUP_RX_CLK 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRUP_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRDN_RX_CLK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_POWER_1_OFFSET_PWRDN_RX_CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0 0x0098A300 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_DELAY_REF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_DELAY_REF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_BLCG_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL0_BLCG_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1 0x0098A304 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2 0x0098A308 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3 0x0098A30C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4 0x0098A310 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5 0x0098A314 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6 0x0098A318 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7 0x0098A31C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0 0x0098A320 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_ENTRY_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_ENTRY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_STALL_DELAY 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_STALL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_INV_BW_EVAL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_INV_BW_EVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_EN_WCKTR 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_EN_WCKTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_CHECK_DISPLAY_OK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL0_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1 0x0098A324 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1_SEC_CNT_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL1_SEC_CNT_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2 0x0098A328 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2_SEC_CNT_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL2_SEC_CNT_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3 0x0098A32C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3_SEC_CNT_MIN_WR 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3_SEC_CNT_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3_SEC_CNT_MAX_WR 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL3_SEC_CNT_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4 0x0098A330 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4_SEC_CNT_MIN_ALL 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4_SEC_CNT_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4_SEC_CNT_MAX_ALL 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL4_SEC_CNT_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5 0x0098A334 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5_SEC_CNT_MIN_ARBS 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5_SEC_CNT_MIN_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5_SEC_CNT_MAX_ARBS 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL5_SEC_CNT_MAX_ARBS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6 0x0098A338 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MIN_RD_VC0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MIN_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MAX_RD_VC0 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MAX_RD_VC0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MIN_RD_VC2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MIN_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MAX_RD_VC2 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL6_LATENCY_MAX_RD_VC2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7 0x0098A33C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MIN_WR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MIN_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MAX_WR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MAX_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MIN_ALL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MIN_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MAX_ALL 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACPD_CTRL7_LATENCY_MAX_ALL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL 0x0098A444 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DQR_CTRL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_PERIOD 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_PERIOD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_SET 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_SET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_CLR 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_CLR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC0_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC0_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC1_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_CTRL_EN_IC1_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP0 0x0098A4C0 /* R--4R */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP1 0x0098A4C4 /* R--4R */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC0_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP0 0x0098A4C8 /* R--4R */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP0_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP0_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP1 0x0098A4CC /* R--4R */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP1_VALUE 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_DQ_IC1_SUBP1_VALUE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD 0x0098A4D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP0 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC0_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP0 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP0_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP0_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP1 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP1_INVALID 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP1_VALID 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DQR_STATUS_VLD_IC1_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CONFIG0 0x00988290 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG0_RC 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG0_RC_35 0x00000023 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RC_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RC__PROD_C_SAMSUNG_DDR3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RFC 16:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG0_RFC_45 0x0000002D /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RFC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RFC_MAX 0x000001FF /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RFC__PROD_C_SAMSUNG_DDR3 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RAS 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG0_RAS_25 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RAS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RAS_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RAS__PROD_C_SAMSUNG_DDR3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RP 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG0_RP_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RP_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RP_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_RP__PROD_C_SAMSUNG_DDR3 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_USE_TIMING_REGS 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG0_USE_TIMING_REGS_FALSE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_USE_TIMING_REGS_TRUE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG0_USE_TIMING_REGS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG0_USE_TIMING_REGS_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1 0x00988294 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG1_CL 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG1_CL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG1_CL_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_CL_MAX 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WL 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG1_WL_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WL_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WL_MAX 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_RD_RCD 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG1_RD_RCD_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG1_RD_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_RD_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WR_RCD 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG1_WR_RCD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WR_RCD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_WR_RCD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET 31:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_HBM_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_G6_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_G6_HS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_G6X_LS 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG1_QPOP_OFFSET_G6X_HS 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2 0x00988298 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG2_RPRE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_RPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_RPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_RPRE_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WPRE 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_WPRE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WPRE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WPRE_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_CDLR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_CDLR_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_CDLR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_CDLR_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_WR_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WR_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_WR_MAX 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_W2R_BUS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_W2R_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_W2R_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_W2R_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_R2W_BUS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG2_R2W_BUS_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG2_R2W_BUS_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG2_R2W_BUS_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3 0x0098829C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEX_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEN2PDEX 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEN2PDEX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEN2PDEX_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_PDEN2PDEX_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_FAW 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_FAW_40 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_FAW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_FAW_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_AOND 23:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_AOND_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_AOND_12 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_AOND_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_AOND_MAX 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDL 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDL_MAX 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDS 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDS_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG3_CCDS_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4 0x009882A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO_1F 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO_MIN 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO_3_9_US 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_LO_7_8_US 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH 14:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_11 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_MAX 0x00000FFF /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_3_9_US 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH_7_8_US 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_REFRESH__PROD_C_SAMSUNG_DDR3 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_RRD 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG4_RRD_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG4_RRD_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_RRD_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY_10 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY_14 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_DDR5 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_DDR5X 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_DDR6 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_HBM 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_SDDR4 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY__PROD_C_LEGACY 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_IDLE_DELAY_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC 31:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_9 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_13 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_18 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_26 0x0000001A /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR5X 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_DDR6X 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_HBM 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_SDDR4 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG4_CMD2MCIDLE_DRAMC__PROD_C_LEGACY 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG5 0x009882A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG5_ADR_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_ADR_MIN_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRCRC 10:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRCRC_11 0x0000000B /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRCRC_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRCRC_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG5_QSAFE_OFFSET 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_QSAFE_OFFSET_39 0x00000027 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_INTRP_MSB 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_INTRP_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_RDRET_OFFSET 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_RDRET_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRRET_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_WRRET_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG5_INTRP 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG5_INTRP_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6 0x009882A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG6_RDFLUSH_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_RDFLUSH_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_WRFLUSH_OFFSET 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_WRFLUSH_OFFSET_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_DDR6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD2MCIDLE_DRAMC_EXT__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG6_WDAT_LATENCY 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_WDAT_LATENCY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_PPD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_PPD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_SDDR4_RDV_OFFSET 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_SDDR4_RDV_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD_ADJUST 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD_ADJUST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG6_CMD_ADJUST_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG7 0x009882AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG7_ZQCS_INTERVAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG7_ZQCS_INTERVAL_64 0x0061A800 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG7_ZQCS_INTERVAL_128 0x00C35000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG8 0x009882CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG8__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG8_ATR_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG8_ATR_OFFSET_INIT 0x0000000D /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG8_ATR_PADDING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG8_ATR_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG8_ODT_PADDING 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG8_ODT_PADDING_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG8_WCK2PH 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG8_WCK2PH_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG8_MRSTWCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG8_MRSTWCK_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9 0x009882E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG9__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG9_QUSE_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_QUSE_OFFSET_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9_QUSE_DDLL_SETTLE 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_QUSE_DDLL_SETTLE_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9_REXT_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_REXT_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9_DLCELL_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_DLCELL_SETTLE_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9_QRST_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_QRST_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG9_MPRR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG9_MPRR_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10 0x009882F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG10__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG10_RFC_MSB 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_RFC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_PDEN2PDEX_MSB 6:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_PDEN2PDEX_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_RD_RCD_MSB 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_RD_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_WR_RCD_MSB 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_WR_RCD_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_SDDR4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_IDLE_DELAY_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR5X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_DDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_HBM 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_SDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_CMD2MCIDLE_DRAMC_HI__PROD_C_LEGACY 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG10_RDRET_OFFSET_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG10_RDRET_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11 0x009883E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG11__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG11_RRDL 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_RRDL_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_RRDL_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_RRDL_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_CCDMW 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_CCDMW_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_CCDMW_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_CCDMW_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_CCDMW_MAX 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_MTA 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_MTA_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_MTA_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_WPOST 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_LPDDR4_RDV_OFFSET 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_WEXT_OFFSET 22:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_WEXT_OFFSET_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_RPRE_TOGGLE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_RPRE_TOGGLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG11_RPRE_TOGGLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_RD_RANK_SEL_DELAY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_RD_RANK_SEL_DELAY_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG11_WR_RANK_SEL_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG11_WR_RANK_SEL_DELAY_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG12 0x0098815C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFIG12__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFIG12_BLDIV 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG12_BLDIV_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG12_ADR_TERM 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG12_ADR_TERM_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG12_ADR_TERM_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFIG12_ADRTR_FIFO_MARGIN 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG12_ADRTR_FIFO_MARGIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG12_CABI_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFIG12_CABI_MODE_DC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFIG12_CABI_MODE_AC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN 0x009882B0 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RC 8:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RFC 22:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RFC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RAS 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING0_GEN_RAS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN 0x009882B4 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_R2W 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_R2W_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_W2R 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_R2P 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_R2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_W2P 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING1_GEN_W2P_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN 0x009882B8 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_RD_RCD 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_RD_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_WR_RCD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_WR_RCD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_RRD 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_RRD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_WDV 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING2_GEN_WDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN 0x009882BC /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QUSE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QUSE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QRST 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QSAFE 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_QSAFE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_RDV 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING3_GEN_RDV_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN 0x009882C0 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEX2WR 5:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEX2WR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEX2RD 13:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEX2RD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEN2PDEX 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEN2PDEX_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_FAW 28:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_FAW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEN2PDEX_MSB 30:29 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING4_GEN_PDEN2PDEX_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN 0x009882C4 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_PCHG2PDEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_PCHG2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_RW2PDEN 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_RW2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_ACT2PDEN 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_ACT2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_AR2PDEN 31:23 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING5_GEN_AR2PDEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN 0x009882C8 /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_PPD 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_PPD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_BUS_W2R 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_BUS_W2R_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_CMD2MCIDLE_DRAMC 21:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_CMD2MCIDLE_DRAMC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_CMD2MCIDLE_FBIO 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING6_GEN_CMD2MCIDLE_FBIO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN 0x009882D0 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_REXT 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_REXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_WEXT 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_WEXT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_ATR 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_ATR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_ATRLEN 28:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING7_GEN_ATRLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN 0x009882D4 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_ODT 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_ODT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_ODTLEN 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_ODTLEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_QPOP_OFFSET 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_QPOP_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_RPRE 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_RPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_WPRE 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING8_GEN_WPRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN 0x009882D8 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_CCDL 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_CCDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_CCDS 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_CCDS_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_ADR 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_ADR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_WCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_WCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_WREDC 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING9_GEN_QPOP_OFFSET_WREDC_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN 0x009882DC /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_RDRET 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_RDRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_WRRET 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_WRRET_INIT 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_RDINTRP 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_RDINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_WRINTRP 30:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING15_GEN_WRINTRP_INIT 0x00000008 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN 0x009882E0 /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_RDFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_RDFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_WRFLUSH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_WRFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_RP 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_RP_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_WCK_QRST 26:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING16_GEN_WCK_QRST_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN 0x009882E4 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_RDRET_PRE 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_RDRET_PRE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_WCK2RDWCK 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_WCK2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_MRS2RDWCK 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING17_GEN_MRS2RDWCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN 0x009882EC /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_WRCRCFLUSH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_WRCRCFLUSH_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_REXT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_REXT_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_QUSE_SETTLE 20:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_QUSE_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_DLCELL_SETTLE 29:21 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING18_GEN_DLCELL_SETTLE_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN 0x009882F0 /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_QRST_OFFSET 4:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_QRST_OFFSET_INIT 0x00000002 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_QRST_FLUSH 9:5 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_QRST_FLUSH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_MPRR 16:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_MPRR_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_REFSB_SUBP0 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_REFSB_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_REFSB_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING19_GEN_REFSB_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN 0x00988288 /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN_RD_REFRESH 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN_RD_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN_WR_REFRESH 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING20_GEN_WR_REFRESH_INIT 0x0000001F /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN 0x009883F8 /* R--4R */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBA 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBA_INIT 0x00000032 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBR 17:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBR_INIT 0x00000020 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBA_MSB 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING22_GEN_RFCSBA_MSB_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN 0x009883E8 /* R-I4R */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_RRDL 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_RRDL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_CCDMW 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_CCDMW_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_LPDDR4_RDV_OFFSET 18:15 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_LPDDR4_RDV_OFFSET_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_ABPA 25:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_ABPA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_XS_OFFSET 31:26 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TIMING24_GEN_XS_OFFSET_INIT 0x0000000A /* R-I-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET 0x00988158 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PTR_RESET__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PTR_RESET_TESTCMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PTR_RESET_TESTCMD_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_TESTCMD_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_WDATFIFO 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PTR_RESET_WDATFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_WDATFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_EDCFIFO 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PTR_RESET_EDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_EDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RRDATAFIFO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RRDATAFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RRDATAFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RREDCFIFO 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RREDCFIFO_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PTR_RESET_RREDCFIFO_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP 0x00988384 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_EN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_EN_ENABLE_LAT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_RES_THRES 15:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_RES_THRES_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_LAT_THRES 27:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_STALL_WKUP_LAT_THRES_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP 0x009882F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_CNT 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_CNT_5K 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_ENABLE_STD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_ENABLE_STRICT 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_ENABLE_BOTH 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_ENABLE_TIMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_EN_ENABLE_NISO 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_PIPE 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ASR_WAKEUP_PIPE_16 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR 0x009882FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAM_ASR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_EN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRPD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRPD_NO_POWERDOWN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRPD_POWERDOWN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRCLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRCLK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ASRCLK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NOISO 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NOISO_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NOISO_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_PREA 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_PREA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_PREA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NO_WCKTR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NO_WCKTR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_NO_WCKTR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_REF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_REF_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_REF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ACPD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ACPD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ACPD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ZQ 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ZQ_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ZQ_CL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_ZQ_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_CHECK_DISPLAY_OK 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_CHECK_DISPLAY_OK_IGNORE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAM_ASR_CHECK_DISPLAY_OK_CONSIDER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS 0x00988300 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS__PRIV_LEVEL_MASK 0x0098A250 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_HBM_RDBI 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_HBM_WDBI 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_CL 6:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_TESTMODE 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_TESTMODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_TESTMODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR5_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_ADR_GDDR6X_WR 11:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS 0x00988304 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_ADR_RTT_NOM 10:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT 0x00988308 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_ADR__PROD_C_MICRON_DDR3 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS_EXT_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT 0x0098830C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000405 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_ADR__PROD_C_MICRON_DDR3 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS_EXT_BA_EMRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REF 0x00988310 /* -W-4R */ #define NV_PFB_FBPA_MC_2_REF__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REF_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_REF_CMD_REFRESH 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_REF_CMD_REFRESH_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_2_REF_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_REF_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_2_REF_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_REF_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_2_REF_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_REF_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_REF_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE 0x00988314 /* -W-4R */ #define NV_PFB_FBPA_MC_2_PRE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PRE_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_PRE_CMD_PRECHARGE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_PRE_CMD_PRECHARGE_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_RANK_MASK 19:18 /* -WIVF */ #define NV_PFB_FBPA_MC_2_PRE_RANK_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_PRE_RANK_MASK_RANK0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_RANK_MASK_RANK1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_RANK_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_CH_MASK 29:28 /* -WIVF */ #define NV_PFB_FBPA_MC_2_PRE_CH_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_PRE_CH_MASK_CH0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_CH_MASK_CH1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_CH_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_SUBP_MASK 31:30 /* -WIVF */ #define NV_PFB_FBPA_MC_2_PRE_SUBP_MASK_NONE 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_PRE_SUBP_MASK_SUBP0 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_SUBP_MASK_SUBP1 0x00000002 /* -W--T */ #define NV_PFB_FBPA_MC_2_PRE_SUBP_MASK_BOTH 0x00000003 /* -W--T */ #define NV_PFB_FBPA_MC_2_NOP 0x00988318 /* -W-4R */ #define NV_PFB_FBPA_MC_2_NOP__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_NOP_CMD 0:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_NOP_CMD_NOP 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_NOP_CMD_NOP_1 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_SELF_REF 0x0098831C /* RW-4R */ #define NV_PFB_FBPA_MC_2_SELF_REF__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_SELF_REF_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SELF_REF_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SELF_REF_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_SELF_REF_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SELF_REF_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_SELF_REF_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_SELF_REF_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_SELF_REF_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2 0x00988320 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_ADR_CWL 5:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_BA__PROD_C_SAMSUNG_DDR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3 0x00988324 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT 0x00988328 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT_ADR__PROD_C_SAMSUNG_DDR2 0x00000190 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS2_EXT_BA_EMRS2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT 0x0098832C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_EMRS3_EXT_BA_EMRS3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1 0x00988330 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_HBM_WR 4:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_HBM_DRV 7:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DRIVE_STRENGTH_NORMAL 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_AUTO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DRIVE_STRENGTH_FIXED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_DATA_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM 3:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_40 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_DATA_TERM_48 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM 5:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_CKE_VAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ADDR_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CAL_UPDATE_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_RDBI 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_RDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_RDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_MTA 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_MTA_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_MTA_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_WDBI 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_WDBI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_WDBI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_PAM4 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_PAM4_PAM4 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_PAM4_GDDR6 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_ABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CABI 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CABI_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR6X_CABI_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL_RESET 11:11 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_ADR_GDDR5_PLL_RESET_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_BA_MRS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS1_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2 0x00988334 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_HBM_WL 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_HBM_RL 7:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR5_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_PULLDOWN_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR5_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_PULLUP_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR5_DATA_WCK_TERM_OFFSET 8:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR5_ADDRESS_TERM_OFFSET 11:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_SELF_REF 7:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_SELF_REF_ATCSR 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CRC_WRTR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_RDQS_MODE_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_CADT_SRF_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST 11:11 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_NO 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_ADR_GDDR6X_FIFO_PTR_RST_YES 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_BA_MRS 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS2_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3 0x00988338 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH 1:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_32MS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_16MS 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_SELF_REFRESH_8MS 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_HBM_RAS 5:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK01_INV 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK01_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_DATA_TERM_OFFSET 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK23_INV 3:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK23_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING 4:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK2CK_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_RDQS 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_RDQS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_RDQS_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_CA_TERM_OFFSET 5:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_INFO_VENDOR_ID 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_INFO 7:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_INFO_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID1 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_INFO_TEMPERATURE 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_INFO_VENDOR_ID2 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK_TERM 9:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ_DIV2 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_WCK_TERM_ZQ 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING 9:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_1X 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_WR_SCALING_2X 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_ENABLED 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_3 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR5_BANK_GROUPS_CCDL_4 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS 11:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_ADR_GDDR6X_BANK_GROUPS_ON 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_BA_MRS 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS3_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4 0x0098833C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_EDC_HOLD_PATTERN 3:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_CRCWL 6:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_CRCCL 8:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_RDCRC 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_RDCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_RDCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_WRCRC 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_WRCRC_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_WRCRC_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_EDC13_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR5_EDC13_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV 11:11 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_ADR_GDDR6X_EDC1_INV_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_BA_MRS 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5 0x00988340 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP1 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP1_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP1_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP2 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP2_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP2_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP3 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP3_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_LP3_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_PLL_BANDWIDTH 5:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR5_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_RAS_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_ADR_GDDR6X_RAS 11:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_DM 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_DM_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_DM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_WDBI 11:11 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_WDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_WDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RDBI 12:12 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RDBI_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RDBI_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_BA_MRS 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6 0x00988344 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_WCKPIN 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_WCKPIN_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREF_MERGE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREFD 3:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREFD_EXTERNAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREFD_INTERNAL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE23 7:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_ADR_GDDR5_VREFD_OFFSET_BYTE01 11:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7 0x00988348 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_STANDBY_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK_AP 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK_AP_PIN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_PLL_FAST_LOCK_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HIBERNATE_SR_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_1DB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_TXEQ_LEVEL_2DB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE 3:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_LOW_FREQ_MODE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC 4:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_WCK2CK_AUTOSYNC_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DQ_PREAMBLE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_40 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VREFD_4048_48 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_TEMP_SENSE_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFC_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_70 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_HALF_VREFD_50 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_5 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_35 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_VDD_RANGE_1_2 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE 9:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_35 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_VDD_RANGE_1_25 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DCC_HOLD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR5_DCC_RESET 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_DCC 11:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_DCC_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_DCC_START 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_ADR_GDDR6X_DCC_HOLD 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_BA_MRS 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS7_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8 0x00988354 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_CL_EHF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_CL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_CL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_WR_EHF 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR5_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TERM 1:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TERM_80 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_FIFO_SEQ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_INV_READ 3:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_INV_READ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_INV_READ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TO 4:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TO_RESET 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CA_TO_PROG 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_EDC_HIZ_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_DIS 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_CK_AUTOCAL_EN 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_REFPB 7:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_REFPB_PB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_REFPB_P2B 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_RL_EHF 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_RL_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_WR_EHF 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_NORMAL 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6X_WR_EHF_EXTENDED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6_CATH 3:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6_PLL_RANGE 4:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_ADR_GDDR6_MICRON_PLL_RANGE_MSB 5:5 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_BA_MRS 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS8_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9 0x00988358 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR__PROD_C_SAMSUNG_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR__PROD_C_QIMONDA_GDDR5 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR5_PRE_EMPHASIS 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_RX_MASK 1:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDL 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDM 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_RX_MASK_VREFDU 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_TXEQ 6:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_TXEQ_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_TXEQ_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_ADR_GDDR6X_PIN_SUB_ADDRESS 11:7 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10 0x0098A200 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET 3:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT 5:4 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK0_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT 7:6 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_0 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_90 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_180 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK1_SHIFT_270 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK2CK 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK2CK_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_VREFC_OFFSET_MSB 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM 11:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_60 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_ADR_GDDR6X_WCK_TERM_120 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS10_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11 0x0098A204 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS11_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12 0x0098A208 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_VDDQ_OFF_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_LSB 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_P2BR_ADDR_MSB 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_PRBS 2:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_PRBS_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_PRBS_ON 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK 11:3 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_ADR_GDDR6X_CRC_LANE_MASK_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS12_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13 0x0098A20C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS13_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14 0x0098835C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR_MICRON_CORE_VOLTAGE 4:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_ADR_MICRON_SUBREG_SELECT 11:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15 0x0098834C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR__PROD_C_SAMSUNG_GDDR5 0x00000C1C /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR__PROD_C_QIMONDA_GDDR5 0x00000802 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_HBM_IVREF 2:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREA 0:0 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREA_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREA_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREB 1:1 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREB_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_MREB_BLOCKED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_CADT 3:2 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_CADT_OFF 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_CADT_RISING 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_CADT_FALLING 0x00000002 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR6X_CADT_CABI 0x00000003 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF0 8:8 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF0_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF1 9:9 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_MRA_MF1_DISABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING 10:10 /* ----F */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_DISABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_ADR_GDDR5_ADDRESS_TRAINING_ENABLED 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_BA_MRS 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS15_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16 0x0098A210 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS16_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17 0x0098A214 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS17_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18 0x0098A218 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS18_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19 0x0098A21C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS19_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20 0x0098A220 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS20_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22 0x0098A224 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS22_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23 0x0098A228 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS23_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24 0x0098A22C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS24_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25 0x0098A230 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS25_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32 0x0098A234 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS32_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40 0x0098A238 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_BA_MRS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS40_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_MRR 0x0098A23C /* RW-4R */ #define NV_PFB_FBPA_MC_2_MRR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_MRR_CMD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MRR_CMD_MRR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MRR_CMD_MRR_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MRR_BA 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MRR_BA_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MRR_RANK 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MRR_RANK_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MRR_CH 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MRR_CH_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_VLD_SUBP0 10:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_VLD_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_SUBP0 18:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_VLD_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_VLD_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_SUBP1 27:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_MRR_GEN_DATA_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_MPC 0x0098A240 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MPC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_MPC_ADR 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MPC_ADR_NOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MPC_ADR_START_DQS_OSC 0x0000004b /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_ADR_STOP_DQS_OSC 0x0000004d /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MPC_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MPC_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MPC_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MPC_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_SUBP_MASK 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MPC_SUBP_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MPC_SUBP_MASK_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_SUBP_MASK_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_MPC_SUBP_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC 0x00988350 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_RDWR_ARB_ISSUE_AT_CCDS_RATE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_BANK_SEQ 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_BANK_SEQ_INC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_BANK_SEQ_BG 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_NO_TR_ACT_IN_TFAW 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_NO_TR_ACT_IN_TFAW_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_NO_TR_ACT_IN_TFAW_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_TR_RW_ALL_BANK 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_TR_RW_ALL_BANK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_TR_RW_ALL_BANK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_IDLE_ON_TR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_IDLE_ON_TR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_IDLE_ON_TR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ACT_HIGH_PRIORITY 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ACT_HIGH_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ACT_HIGH_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_HOLDOFF_WRACT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_HOLDOFF_WRACT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_HOLDOFF_WRACT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BALANCED_WRITEPULL_LATENCY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_WR_FEEDBACK 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_WR_FEEDBACK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_WR_FEEDBACK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BG_ENABLE_ON_CCD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BG_ENABLE_ON_CCD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_BG_ENABLE_ON_CCD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ENABLE_RRDL_COUNTER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ENABLE_RRDL_COUNTER_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ENABLE_RRDL_COUNTER_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_KILL_PEND_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_KILL_PEND_CTRL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_KILL_PEND_CTRL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_TR_SAFE_SCHED 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_TR_SAFE_SCHED_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ABPA_PER_RANK 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_ABPA_PER_RANK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_MAX_BANK_HITS 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_MAX_BANK_HITS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_MAX_BANK_HITS_MAX 0x0000007E /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_PRIORITY 28:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_PRIORITY_HIGHEST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_PRIORITY_MEDIUM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_PRIORITY_LOWEST 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_GBL_RRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_GBL_RRD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_PBR_GBL_RRD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_CMDQ_ALWAYS_ON 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_CMDQ_ALWAYS_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_CMDQ_ALWAYS_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_FORCE_G5_TO_G5X 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_FORCE_G5_TO_G5X_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MISC_DRAMC_FORCE_G5_TO_G5X_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_IC_CTRL 0x00988208 /* RW-4R */ #define NV_PFB_FBPA_MC_2_IC_CTRL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_DIRECTION_SYNC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_DIRECTION_SYNC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_DIRECTION_SYNC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_SP2DRAMC_FLOP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_IC_CTRL_SP2DRAMC_FLOP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_SP2DRAMC_FLOP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_ACPD_ON_REFSB_IDLE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_IC_CTRL_DRAMC_IGNORE_COUNTER_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO 0x0098A3FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO_THRESHOLD 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO_THRESHOLD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO_STALL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_STALL_CMD_FIFO_STALL_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0 0x00988360 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1 0x00988364 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_BA_MRS 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0 0x00988368 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1 0x0098836C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_BA_MRS 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS9_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0 0x00988370 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP0_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1 0x00988374 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_RANK_MASK 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_RANK_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_RANK_MASK_RANK0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_RANK_MASK_RANK1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_RANK_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_BA_MRS 0x0000000E /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_CH_MASK 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_CH_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_CH_MASK_CH0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_CH_MASK_CH1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS14_SUBP1_CH_MASK_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT 0x00988378 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS4_EXT_BA_MRS4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT 0x0098837C /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS5_EXT_BA_MRS5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT 0x00988380 /* RW-4R */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT_ADR 16:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT_BA 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_GENERIC_MRS6_EXT_BA_MRS6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1 0x00988280 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CG1__PRIV_LEVEL_MASK 0x009881B4 /* */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_TRAINING 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_TRAINING_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_TRAINING_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIV 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIV_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIV_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_REPLAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_REPLAY_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_REPLAY_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SS2PACMD1 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SS2PACMD1_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SS2PACMD1_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_FABSCAN 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_FABSCAN_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_FABSCAN_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIVSYNC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIVSYNC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PRIVSYNC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_6_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_6_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAF2TSUBP 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAF2TSUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAF2TSUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_ILA 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_ILA_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_ILA_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAL 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAL_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_PAL_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_10 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_10_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_10_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_11 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_11_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_11_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_12 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_12_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_12_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_13 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_13_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_13_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_14 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_14_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_14_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_15 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_15_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_15_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_16 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_16_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_16_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_17 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_17_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_17_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_18 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_18_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_18_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_19 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_19_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_19_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_20 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_20_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_20_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_21 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_21_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_21_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_22 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_22_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_22_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_23 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_23_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_23_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_24 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_24_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_24_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_25 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_25_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_25_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_26 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_26_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_26_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_27 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_27_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_27_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_28 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_28_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_28_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_29 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_29_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_29_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_30 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_30_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_30_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_31 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_31_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_SPARE_31_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG 31:0 /* ----F */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG_DISABLED 0xFFFFFFFF /* ----V */ #define NV_PFB_FBPA_MC_2_CG1_SLCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_CG2 0x00988284 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CG2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FAB_INTFC 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FAB_INTFC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FAB_INTFC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_SUBP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_SUBP_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_MISC 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_MISC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_MISC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FABRIC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_PRI_REG_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_PRI_REG_UPDATE_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_PRI_REG_UPDATE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_CMD_FABRIC 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_CMD_FABRIC_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_CMD_FABRIC_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG 5:0 /* ----F */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_ENABLED 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG_DISABLED 0x0000003F /* ----V */ #define NV_PFB_FBPA_MC_2_CG2_FGCG__PROD 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG 0x00988400 /* RW-4R */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_CHAIN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_CHAIN_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_CHAIN_32 0x0000001f /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_CHAIN_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_LIST_SIZE 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_LIST_SIZE_8 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_MAX_LIST_SIZE_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_PAGE_SIZE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_PAGE_SIZE_1K 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_PAGE_SIZE_2K 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_SET_SWIZZLE 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG 0x00988410 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_8 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_EVICT_ON_CLEAN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_EVICT_ON_CLEAN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_EVICT_ON_CLEAN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_BANKQ 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL 18:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_16 0x0000000f /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_64 0x0000003f /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_DISABLE 0x0000007f /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_MAX_CHAIN_CLOSE_FL_CLEAN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_SET_SWIZZLE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_SET_SWIZZLE_ENABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_SET_SWIZZLE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_FT_CFG_AUTO_CLEAN_BANKQ_THRESHOLD_3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG 0x00988420 /* RW-4R */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_VC1_BEFORE_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG 0x00988430 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_MAX_HITS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_HEAD_BANKQ_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_BANKQ_CFG_BANK_HIT_ONLY_SAME_DIR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0 0x00988440 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_LATENCY_INTERVAL 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_LATENCY_INTERVAL_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_LATENCY_INTERVAL_32 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LATENCY_OFFSET 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LATENCY_OFFSET_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LATENCY_OFFSET_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LATENCY_OFFSET_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LATENCY_OFFSET_F 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LATENCY_OFFSET_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_READ_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT_MAX 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_WRITE_LIMIT_DISABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_R2W_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG0_W2R_MAX_VC1_LATENCY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1 0x00988444 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_NO_TURN_IF_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_BYPASSES_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_TURN_WAIT_ON_BANK_HIT_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_SNAPSHOT_ARB 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_SNAPSHOT_ARB_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_SNAPSHOT_ARB_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_COMPLETE_SNAP_WR_VC1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_BLOCKS_SPSM 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_BLOCKS_SPSM_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_READ_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_READ_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_WRITE_SNAPSHOT_LAT_LIMIT_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_VC1_SNAPSHOT_LAT_LIMIT_8 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG1_MIN_WRITE_INT_PER_TURN_VC1_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2 0x00988448 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_READ_SEC_THRESHOLD 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_READ_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_READ_SEC_OFFSET 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_READ_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_WRITE_SEC_THRESHOLD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_WRITE_SEC_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG2_WRITE_SEC_OFFSET_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3 0x0098846C /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_READ_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_WRITE_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_VC1_SNAPSHOT_LAT_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_READ_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_WRITE_LATENCY_OFFSET_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_R2W_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_W2R_MAX_VC1_LATENCY_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_LATENCY_USES_LTCCLK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG3_LATENCY_USES_LTCCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4 0x009884BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4_READ_LIMIT_MSB 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4_READ_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4_WRITE_LIMIT_MSB 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG4_WRITE_LIMIT_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5 0x0098A580 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5_HIGH_EFF_RD_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG5_HIGH_EFF_WR_SECTORS_INIT 0x0000ffff /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6 0x0098A584 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6_LOW_EFF_RD_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG6_LOW_EFF_WR_SECTORS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7 0x0098A588 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_LOW_EFF_MIN_RD_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_LOW_EFF_MIN_WR_INT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_HIGH_EFF_RD_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_DIR_ARB_CFG7_HIGH_EFF_WR_LIMIT_INIT 0x000000ff /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG 0x00988450 /* RW-4R */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WRITEPULL_REQ 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WRITEPULL_REQ_IMM 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_WRITEPULL_REQ_WAIT_RWDIR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_USE_DRAMC_BUSY 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_USE_DRAMC_BUSY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_USE_DRAMC_BUSY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CMD_FIFO_DEPTH 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CMD_FIFO_DEPTH_NOLIMIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_POLICY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_PRIORITY 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_PRIORITY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_PRIORITY_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CMD_FIFO_DEPTH_MSB_NOLIMIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_DELAY 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_DELAY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_WRITE_ARB_CFG_CCDMW_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG 0x00988454 /* RW-4R */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_WT_SELECT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_WT_SELECT_ORDER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_WT_SELECT_CNT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_HOLDOFF 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_HOLDOFF_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_SECTOR_EQUALIZATION_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_SECTOR_THRESHOLD_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_BANK_GROUP_IGNORE_LOW_PRI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_POLICY 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_POLICY_IMB 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_POLICY_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_LEVEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_LEVEL_TURN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_LEVEL_ALWAYS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_COMBINE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_COMBINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READ_ARB_CFG_SECCNT_BGARB_COMBINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG 0x00988460 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_RD_SUBPACKETS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_RD_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_RESNAP_DURING_TURN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_RESNAP_DURING_TURN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_RESNAP_DURING_TURN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SNAP_BASED_ON_VC 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SNAP_BASED_ON_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SNAP_BASED_ON_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_WR_SUBPACKETS 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_WR_SUBPACKETS_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_BGSEC 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_BGSEC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_BGSEC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_BANKQ_ENTRIES 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_BANKQ_ENTRIES_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MAX_SKIP_COUNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MAX_SKIP_COUNT_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_MIN_ACT_SUBP_EFF_PM_6 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_PER_VC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_PER_VC_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_PER_VC_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_MODE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG_SKIP_CNT_MODE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1 0x00988464 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_ACTARB_CMD_DELAY 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_ACTARB_CMD_DELAY_4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_ACTARB_CMD_DELAY_6 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_HOLDOFF 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_RD_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_NO_BANK_HIT_WRITE_TURN_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_HOLDOFF 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_HOLDOFF_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_HOLDOFF_4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_HOLDOFF_4 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH 25:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_WR_ACT_NEAR_FULL_THRESH_28 0x0000001C /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_ACTARB_FIFO_DELAY 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG1_ACTARB_FIFO_DELAY_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2 0x00988468 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_READS_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_WR_BANK_HIT_ACT_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_RD_BANK_HIT_BGSEC_WT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_32 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_WRITES_IN_FLIGHT_128 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE 25:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_READS_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE 30:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG2_MAX_WRITES_PER_ACTIVATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG3 0x009884C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG3_IC_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG3_IC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG3_IC_MODE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4 0x009884D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_WEIGHT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ACT_ARB_CFG4_BGSEC_MIN_CNT_BLOCK_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH 0x009884D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR5 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR5 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MAX__PROD_C_GDDR6X 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MIN 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_MIN_INIT 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_TYPE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_TYPE_STATIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FIFO_DEPTH_ASYNC_CMDQ_TYPE_DYNAMIC 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW 0x009884D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_ACPD_ASR 0x00988458 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_ACPD_ASR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT 12:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WINDOW_ACPD_ASR_MAX_COUNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR 0x009884DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_WR_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0 0x009884F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC0_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1 0x009884F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC1_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2 0x009884F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2_MAX_COUNT_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_VC2_SINGLE_WINDOW_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR 0x009884FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR_MAX_COUNT_INIT 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_SECTORS_ACPD_ASR_SINGLE_WINDOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WR 0x009884E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_WR_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC0 0x009884E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC0_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC0_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1 0x009884E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_UTIL_INIT 0x00000800 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_ECC 0x0098845C /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_ECC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_ECC_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC1_ECC_UTIL_INIT 0x00000555 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC2 0x009884EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC2_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_VC2_UTIL_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ACPD 0x009884B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ACPD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ACPD_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ACPD_UTIL_INIT 0x000000CC /* RWI-V */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ASR 0x0098844C /* RW-4R */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ASR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ASR_UTIL 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BW_TRACKER_ASR_UTIL_INIT 0x00000199 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL 0x00988470 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL__PRIV_LEVEL_MASK 0x00988170 /* */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_MASTER_EN 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_MASTER_EN_ENABLED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_MASTER_EN_DISABLED 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_INCLUDE_ADDR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_INCLUDE_ADDR_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_INCLUDE_ADDR_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL_OFF 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_WRITE_KILL_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_EN 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_EN_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_EN_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_SIDEBAND_EN 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_SIDEBAND_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_SIDEBAND_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR_MODE 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR_MODE_OFF 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR_MODE_ALL 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR_MODE_ADR 0x2 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0 17:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR0_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_EN_FALSE 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_EN_TRUE 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1 28:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_INIT 0x000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_MIN 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_WRITE_KILL_PTR1_MAX 0x10F /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_ENABLED 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_CONTROL_ECC_CACHE_INVALIDATE_ON_ACT_DISABLED 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL 0x00988474 /* RW-4R */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_SEC_INTR_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_SEC_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_SEC_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_DED_INTR_EN 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_DED_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_DED_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_POISON_INTR_EN 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_POISON_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_POISON_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_ADDRERR_INTR_EN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_ADDRERR_INTR_EN_ENABLED 0x1 /* RW--V */ #define NV_PFB_FBPA_MC_2_ECC_INTR_CTRL_ADDRERR_INTR_EN_DISABLED 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS(i) (0x00988478+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ECC_STATUS__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_INTR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_INTR 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_POISON_INTR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_POISON_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_POISON_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_POISON_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_INTR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_INTR_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_INTR_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_INTR_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_COUNTER_OVERFLOW 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_SEC_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_COUNTER_OVERFLOW 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_DED_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_NOT_PENDING 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_PENDING 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_STATUS_ADDRERR_COUNTER_OVERFLOW_RESET 0x1 /* -W--C */ #define NV_PFB_FBPA_MC_2_ECC_SEC_COUNT(i) (0x00988480+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ECC_SEC_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_SEC_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_SEC_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_DED_COUNT(i) (0x00988488+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ECC_DED_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_DED_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_DED_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG(i) (0x00988490+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_2_ECC_DIAG__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_TYPE 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_TYPE_SEC 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_TYPE_DED 0x1 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_TYPE_POISON 0x2 /* R---V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_DED 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_DED_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_SEC 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_SEC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_POISON 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_POISON_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_SECBIT 16:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_DIAG_SECBIT_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR(i) (0x00988498+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR__PRIV_LEVEL_MASK 0x00988170 /* */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_COL 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_COL_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_PC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_PC_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_ROW 26:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_ROW_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_BANK 30:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_BANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXTBANK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXTBANK_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXT(i) (0x0098A4B8+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXT__PRIV_LEVEL_MASK 0x00988170 /* */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXT_SID 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ERR_INJECTION_ADDR_EXT_SID_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR(i) (0x009884A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT(i) (0x009884A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2(i) (0x0098A498+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED(i) (0x0098A448+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_DED_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED(i) (0x0098A450+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_DED_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_DED(i) (0x0098A4A0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_DED_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_DED_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC(i) (0x0098A458+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_SEC_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC(i) (0x0098A460+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_SEC_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SEC(i) (0x0098A4A8+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SEC_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_SEC_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON(i) (0x0098A468+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_POISON_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON(i) (0x0098A470+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_REMAPPED_ROW 26:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_REMAPPED_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_REMAPPED 29:29 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_REMAPPED_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_POISON_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_POISON(i) (0x0098A4B0+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_POISON_SID 2:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT2_POISON_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR(i) (0x0098A480+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_COL 10:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_ROW 27:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_ROW_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_BANK 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_ADDRERR_BANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR(i) (0x0098A488+(i)*4) /* R-I4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_COL 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_COL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_SID 22:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_SID_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL 30:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_PSEUDO_CHANNEL_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_EXTBANK 31:31 /* R-IVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDR_EXT_ADDRERR_EXTBANK_INIT 0x0 /* R-I-V */ #define NV_PFB_FBPA_MC_2_ECC_ADDRERR_COUNT(i) (0x0098A490+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_ECC_ADDRERR_COUNT__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_ECC_ADDRERR_COUNT_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ECC_ADDRERR_COUNT_V_INIT 0x0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE 0x009884B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_ENABLE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_ENABLE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_OVERRIDE 4+4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_OVERRIDE_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BANK_SWIZZLE_OVERRIDE_MAX 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION 0x009884B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR 10:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CONFLICT_RESOLUTION_FRC_PRIORITY_CTR_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER 0x009884C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_READS 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_READS_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_READS_24 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_READS_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_RW 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_RW_16 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_RW_28 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_LTC_BANDWIDTH_LIMITER_RW_NO_LIMIT 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO 0x009884C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_INIT 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_INIT_VAL 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE2_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET 13:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE3_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE4_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE5_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE6_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_BYTE7_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET 28:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_CMD0_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO2PA_RESYNC_FIFO_CMD1_OFFSET_VAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_READSCHEDULE_FIFO 0x009884CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_READSCHEDULE_FIFO__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_READSCHEDULE_FIFO_DEPTH_LIMIT 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_READSCHEDULE_FIFO_DEPTH_LIMIT_FULL 0x000001FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL 0x00988500 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE 5:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_INVALID 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_MRS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_REFRESH 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_SELFREFRESH_ENTRY 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_POWERSTATE_EXIT 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_POWERDOWN_ENTRY 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_PRECHARGE 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_PRECHARGE_ALL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_ACTIVATE 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_WRITE 0x00000009 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_WRITE_AUTOPRE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_WRITE_ANY 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_READ 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_READ_AUTOPRE 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_READ_ANY 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_CACHE_MGMT_OP_PENDING 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_LDFF 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_RDTR 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_WRTR 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_ZQCL 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_ZQCS 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_REPLAY 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_REPLAY_START 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_READ_TRAINING 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_WRITE_TRAINING 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_MRR 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_MPC 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_REFSB 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_STEP 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_SEQUENCE 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_ADR 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_WCK 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_RD 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_WR 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_QUSE 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_MODE 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_TRAINING_PERIODIC 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_CHAR_WRITE 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_CHAR_READ 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_CHAR_ERROR 0x0000002C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_CHAR_ERROR_ANY 0x0000002D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_MASKED_PW 0x0000002F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_PAIRED_RW 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_UNPAIRED_CH0 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_UNPAIRED_CH1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_UNPAIRED_CH0_SW 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_UNPAIRED_CH1_SW 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_EDC_RD_ERR 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_EDC_WR_ERR 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_STATE_DQR 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_BASE_DELAY 12:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_BASE_DELAY_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_BASE_DELAY_MAX 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_LENGTH 23:20 /* RWIUF */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_LENGTH_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_LENGTH_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_LENGTH_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_INV 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_INV_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_INV_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_EN 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_EN_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRIGGER_CNTRL_TRIGGER_EN_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAP0 0x0098850C /* R--4R */ #define NV_PFB_FBPA_MC_2_CAP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CAP0_FABRIC_PRESENT 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CAP0_FABRIC_PRESENT_YES 0x00000001 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CAP0_FABRIC_PRESENT_NO 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_CAP0_ECC_PRESENT 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CAP0_ECC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CAP0_ECC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CAP0_EDC_PRESENT 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CAP0_EDC_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CAP0_EDC_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CAP0_REPLAY_PRESENT 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CAP0_REPLAY_PRESENT_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CAP0_REPLAY_PRESENT_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_PARITY 0x00988510 /* RW-4R */ #define NV_PFB_FBPA_MC_2_PARITY__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_DATALO 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_DATALO_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_DATAHI 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_DATAHI_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_CMD 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_PARITY_IB_FABRIC_ERROR_CMD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_PARITY_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_PARITY_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PARITY_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00988554 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "ba" /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BLK_ACTIVITY_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT0 0x00988514 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT0__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT0_INTERCEPT 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT0_INTERCEPT_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT0_1 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT0_1_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT0_2 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT0_2_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT1 0x00988518 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT1__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT1_3 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT1_3_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT1_4 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT1_4_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT1_5 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT1_5_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT2 0x0098851C /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT2__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT2_6 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT2_6_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT2_7 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT2_7_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT2_8 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT2_8_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT3 0x00988520 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT3__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT3_9 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT3_9_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT3_10 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT3_10_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT3_11 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT3_11_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT4 0x00988524 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT4__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT4_12 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT4_12_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT4_13 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT4_13_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT4_14 29:20 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT4_14_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT5 0x00988528 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA_WT5__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_WT5_15 9:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT5_15_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA_WT5_16 19:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_BA_WT5_16_INIT 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_BA 0x00988550 /* RW-4R */ #define NV_PFB_FBPA_MC_2_BA__PRIV_LEVEL_MASK 0x00988554 /* */ #define NV_PFB_FBPA_MC_2_BA_BLKACTIVITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_BA_BLKACTIVITY_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_BA_BLKACTIVITY_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_BA_BLKACTIVITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_RD 0x00988558 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_RD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_RD_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_RD_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_RD_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_RD_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_RD_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_WR 0x0098855C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_WR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_WR_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_WR_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_WR_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_WR_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_WR_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER 0x00988560 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_STATUS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_STATUS_NO_ERROR 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_STATUS_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_STATUS_ERROR 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_NUM 6:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_NUM_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_MODE_CONTINUOUS 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_MODE_ONCE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_MASK_SUBP0 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_MASK_SUBP0_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_MASK_SUBP1 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_TRIGGER_BYTE_MASK_SUBP1_ALL 0x0000000F /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DATA0 0x00988564 /* R--4R */ #define NV_PFB_FBPA_MC_2_CRC_DATA0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_DATA0_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_DATA0_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DATA1 0x00988568 /* R--4R */ #define NV_PFB_FBPA_MC_2_CRC_DATA1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_DATA1_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_DATA1_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DATA2 0x0098856C /* R--4R */ #define NV_PFB_FBPA_MC_2_CRC_DATA2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_DATA 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_EXPECTED_EDC 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_EXPECTED_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_ACTUAL_EDC 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_DATA2_ACTUAL_EDC_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE 0x00988570 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_LIMIT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_LIMIT_1000 0x000003E8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_EXCEEDED 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_EXCEEDED_NO 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_EXCEEDED_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_EXCEEDED_YES 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_TICK_CLOCK 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_TICK_CLOCK_LTCCLK 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_RATE_TICK_CLOCK_MEMREF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_TICK 0x00988574 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_TICK__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_TICK_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_TICK_VALUE_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_TICK_VALUE_1US 0x000002EE /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_MAX_DELTA 0x00988578 /* R--4R */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_MAX_DELTA__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_MAX_DELTA_VALUE 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_MAX_DELTA_VALUE_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0 0x009880D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1 0x009880D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1_MAX_CNT 15:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1_RESET_MAX_CNT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_RETRY_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0 0x009880D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP0_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1 0x009880DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1_MAX_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1_MAX_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_CYCLES_SUBP1_RESET_MAX_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC 0x00988580 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_CNT 23:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_CNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_RESET_ERROR_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_RESET_ERROR_CNT_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_RESET_ERROR_CNT_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_DURING_RETRY 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_DURING_RETRY_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_DURING_RETRY_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_DURING_RETRY_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT 0x00988584 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_CNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_CNT_16384 0x00004000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_CNT 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_CNT_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_CNT_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_DELTA 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_DELTA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_MAX_DELTA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_ERR_ON_RETRY 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_ERR_ON_RETRY_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_CRC_INTERRUPT_EN_ERR_ON_RETRY_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG 0x00988588 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_ERR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_ERR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_RPL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_RPL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP0_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_ERR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_ERR 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_ERR_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_ERR_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_RPL 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_RD_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_RPL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_RPL_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_CRC_DEBUG_SUBP1_WR_RPL_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_RD_BYTE(i) (0x0098A400+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_RD_BYTE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_RD_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_RD_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_WR_BYTE(i) (0x0098A420+(i)*4) /* RWI4A */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_WR_BYTE__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_WR_BYTE_ERRCNT 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CRC_ERROR_COUNT_WR_BYTE_ERRCNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG 0x0098A440 /* RWI4R */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_MAXRETRY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_MAXRETRY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_SUBP0_SKIPCNT 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_SUBP0_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_SUBP1_SKIPCNT 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_REPLAY_DEBUG_SUBP1_SKIPCNT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR(i) (0x0098A4D4+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_1ST 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_1ST 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_1ST 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_1ST 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_2ND 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_2ND 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_2ND 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_2ND 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_RDAT3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_1ST 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_1ST 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_1ST 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_1ST 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_1ST_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_1ST_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_1ST_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_2ND 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC0_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_2ND 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC1_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_2ND 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC2_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_2ND 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_2ND_OCCURED 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_2ND_NOT_OCCURED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_RR_FIFOERR_EDC3_2ND_CLEAR 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_REFCTRL3 0x0098A4DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFCTRL3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR_SRC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR_SRC_DRAMC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_PBR2ABR_SRC_PWRM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_THRESHOLD 20:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_THRESHOLD_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_SPEEDUP 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_SPEEDUP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFCTRL3_SOFTKILLPBR_SPEEDUP_ENABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY 0x0098858C /* RW-4R */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY_MAX 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY_MAX_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY_LAST 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_ISO_LATENCY_LAST_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS 0x00988398 /* R--4R */ #define NV_PFB_FBPA_MC_2_INTR_STATUS__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP0 0:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP0 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP0 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP0 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP0 8:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP1 16:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_SEC_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP1 17:17 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_DED_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP1 18:18 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_OOR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP1 19:19 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_POISON_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP1 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_ADDRERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP1 24:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_INTR_STATUS_AERR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_OOR 0x009883A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_OOR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_OOR_COUNT_SUBP0 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_OOR_COUNT_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP0 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP0_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_OOR_COUNT_SUBP1 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_OOR_COUNT_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP1 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_OOR_RESET_COUNT_SUBP1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP0 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP0_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP0_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP0_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP1 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP1_NOT_PENDING 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP1_PENDING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_SUBP1_RESET 0x00000001 /* -W--C */ #define NV_PFB_FBPA_MC_2_OOR_INTR_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_OOR_INTR_ENABLE_OFF 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_OOR_INTR_ENABLE_ON 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0 0x0098838C /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CFG0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK_BANK 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK_BANK_8 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_DUAL_RANK_BANK_16 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SCHED_PC_LIMIT 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SCHED_PC_LIMIT_MIN 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SCHED_PC_LIMIT_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_OVR 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_OVR_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_OVR_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_VAL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID1_VAL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID1_VAL_SID0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CFG0_SID1_VAL_SID1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG 0x009883A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_SECCNT_ARB 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_SECCNT_ARB_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_SECCNT_ARB_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_MIN_BG_SECTORS 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_MIN_BG_SECTORS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_RESIDUAL_THRESHOLD 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG_RESIDUAL_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1 0x009883A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_RD_RANK_DURATION 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_RD_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_RD_RANK_MIN_STAY 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_RD_RANK_MIN_STAY_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_WR_RANK_DURATION 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_ARB_CFG1_WR_RANK_DURATION_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR 0x009883AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_DQ(i) (0x00000000 + (i)) /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_DQ__SIZE_1 128 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_ECC(i) (0x00000090 + (i)) /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_ECC__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_DBI(i) (0x00000080 + (i)) /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PIN_DBI__SIZE_1 16 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PC 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PC_PC0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PC_PC1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_PC_PC01 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_DBI 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_DBI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_DBI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_ECC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x009883B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x009883B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x009883B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x009883BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x009883C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x009883C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x009883C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x009883CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI 0x009883D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_DBI_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC 0x009883D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MASK_ECC_INVERT_DW3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MAX 0x009883D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MAX__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MAX_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_MAX_V_INIT 0xFFFFFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_THRESHOLD 0x009883DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_THRESHOLD__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_THRESHOLD_V 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_HBM_CHAR_COUNTER_THRESHOLD_V_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_RR_CTRL 0x009883FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_RR_CTRL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_RR_CTRL_PC_NPC_GAP 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_CTRL_PC_NPC_GAP_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_RR_CTRL_RW_GAP 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_RR_CTRL_RW_GAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK 0x009888FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST 0x00988590 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_SDDR23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_DDR3 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR3 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_DDR4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_MS01 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_SDDR4 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM2 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR5X 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR3 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_LPDDR4 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_HBM1 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_DDR_MODE__PROD_C_GDDR6X 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MODE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MODE_LATE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MODE_EARLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_SEND_A14_A15_ON_ABI 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_SEND_A14_A15_ON_ABI_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_EYE_MASK 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_EYE_MASK_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_EYE_MASK_LOWER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_EYE_MASK_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_EYE_MASK_UPPER 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GENERIC 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GENERIC2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR3_BGA136 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_SDDR3_BGA100 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR5_GT215_COMP 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR3_GT215_COMP_MIRR1 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_X8 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_GDDR5_170_MIRR_X8 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_SDDR4_BGA78 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_HBM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_SDDR4_3DS 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_USE_EXTENDED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_MODE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_SUBP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_SUBP_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_GEARDOWN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_GEARDOWN_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_2T_CMD_GEARDOWN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_G5X_CMD_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_G5X_CMD_MODE_G5X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_G5X_CMD_MODE_G5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_MODE 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_ASSERT_QUSE__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_RX_RCV_SEL 22:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_RX_RCV_SEL_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_RX_RCV_SEL_LOW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_RX_RCV_SEL_MID 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_PAM4_RX_RCV_SEL_HIGH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_OB_FABRIC_DBI 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_OB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_OB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_IB_FABRIC_DBI 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_IB_FABRIC_DBI_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_IB_FABRIC_DBI_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_LPDDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR5X_BGA190_MIRR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_1 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_2 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_IC 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_3 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_BGA180_MODE_4 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6X_BGA180_MODE_1 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_90D 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_CMD_MAPPING_EXT_GDDR6_G6X_EMI_270D 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST_MEMCLK_CHANGE_ALERT_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI 0x00988594 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_ON 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_MODE_SSO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_OUT_MODE_LP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_IN_ON 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_IN_ON_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG_DBI_IN_ON_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CHANNELCFG 0x00988598 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CHANNELCFG__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CHANNELCFG_CHANNEL_ENABLE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CHANNELCFG_CHANNEL_ENABLE_32_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CHANNELCFG_CHANNEL_ENABLE_64_BIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1 0x0098859C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_INTERP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_INTERP_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_INTERP_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RCVR 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RCVR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RCVR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RX_CLK 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RX_CLK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BROADCAST1_POWER_EN_RX_CLK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5 0x00988604 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_CMD_PAD_DISABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_CMD_PAD_DISABLE_NOT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_CMD_PAD_DISABLE_DISABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V1P5 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V1P35 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V1P25 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V1P2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V1P8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V2P1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_VDDP_MODE_V2P4 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_ATDAT_FORCE 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_ATDAT_FORCE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_ATDAT_FORCE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_PU40_MODE_CMD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_PU40_MODE_CMD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CONFIG5_PU40_MODE_CMD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE 0x0098860C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE__PROD_C_DDR1 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE__PROD_C_DDR2 0x00300000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE__PROD_C_DDR3 0x00300001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE__PROD_C_DDR4 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE__PROD_C_DDR5 0x80300001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_DELAYED_CALDRV_SDDR 1:1 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_E_SER_FORCE_ONE 4:4 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_E_SER_FORCE_ONE_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_FORCE_MA_SDR 7:7 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_FORCE_MA_SDR_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_FORCE_MA_SDR_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_PAD_CALIBRATION 11:11 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_PAD_CALIBRATION_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_PAD_CALIBRATION_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_SERIALIZER 12:12 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_SERIALIZER_ENABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_SERIALIZER_DISABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_EN 25:25 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_EN_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_EN_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB 26:26 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_OB_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV 27:27 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_ENABLE 0x00000001 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_SEL_INV_DISABLE 0x00000000 /* ----V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE_VALUE_CLK_OBS_CLK_SEL 29:28 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN 0x00988610 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVCLAMP_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_BRICK_VAUXGEN_REG_LVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN 0x00988614 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVDN_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRVUP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_E_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_DRV_VCLAMP_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VCLAMP_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_REF_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_BW_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_VTTGEN_VAUXGEN_REG_VAUXC_LVL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR 0x0098861C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_ASR__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VAUXP 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VAUXC 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VCLAMP 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VAUXP 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VAUXP_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VAUXC 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VAUXC_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VCLAMP 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ASR_BRICK_VCLAMP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL 0x00988670 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_FILTER_BITS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_FILTER_BITS_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_START_TRM 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_START_TRM_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_END_COUNT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_END_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_LEGACY_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_LEGACY_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_USE_LEGACY_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_IGNORE_START 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_CALIBRATE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS 0x00988674 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS 0x00988678 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR0 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR1 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_ADR1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK01 5:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK23 7:6 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCK23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB01_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_WCKB23_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0 17:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE0_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1 19:18 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE1_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2 21:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE2_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3 23:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DDLLCAL_STATUS_BYTE3_OVERFLOW 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL 0x0098867C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DLCELL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DLCELL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DLCELL_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DLCELL_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_DDLLCAL_BYPASS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_ADR_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_WCK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_CORS_TRIMMER 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_IB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_CORS_TRIMMER 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_OB_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQDQS_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_QUSE_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_CLK_CORS_TRIMMER_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_MDDLL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLL_CTRL_DQ_MDDLL_TRIM_SEL_WDQS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL 0x00988694 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP0_ADR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP0_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP0_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP1_ADR0 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP1_ADR0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_ADR_DDLL_SUBP1_CMD_CLK_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL 0x00988698 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL 0x0098869C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL 0x009886A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL 0x009886A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_IB_DDLL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL 0x009886A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL 0x009886AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_OB_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL 0x009886B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL 0x009886B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_DQDQS_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL 0x009886B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL 0x009886BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1 0x00988ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1 0x00988EDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_QUSE_DDLL_RANK1_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE 0x00988700 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_BYTE_VREF_MODE_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL 0x00988704 /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_IB 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_IB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_OB 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_OB_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_DQDQS 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_DQDQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_QUSE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_DDLL_QUSE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC 0x00988708 /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_MODE 1:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE 3:2 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_DQS_VREF_MODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_DAT 6:4 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_DAT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_DQS 10:8 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_VREF_DQS_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT 20:16 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC_QUSE_BRLSHFT_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1 0x0098870C /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQS_VREF_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE 31:24 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x00988710 /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP0_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x00988714 /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE 7:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE 15:8 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE 23:16 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC2_SUBP1_DQ_VREF_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3 0x00988718 /* -W-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE 2:0 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_LOWER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE 5:3 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_MID_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE 8:6 /* -WIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_BROADCAST_MISC3_DQ_DFE_UPPER_CODE_INIT 0x00000000 /* -WI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK 0x00988650 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_PREDI 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_PREDI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK0_ON 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK0_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK0_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK1_ON 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK1_ON_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK1_ON_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK_RUN 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK_RUN_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_CLK_RUN_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_POLARITY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_POLARITY_NORMAL 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK_POLARITY_INVERT 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY 0x0098865C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DELAY_PRIV_SRC_MAX 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY 0x009888E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_SRC 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_PRIV_SRC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_PRIV_SRC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DELAY_CMD_PRIV_SRC_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER 0x009888E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER_PATTERN 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER_PATTERN_INIT 0x33330F0F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_QDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6_DDR 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_WCK_TAPER_PATTERN_GDDR6x 0x33330F0F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK 0x0098866C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_DRVI 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_DRVI_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_DRVZ 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_DRVZ_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_TX_DRVDN 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_TX_DRVUP 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_E_PU40 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_E_PU40_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_E_PU40_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_FREEZE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL 0x00988504 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CFG_DRVDLY 31:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CFG_DRVDLY_A 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB 0x00988508 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB__PRIV_LEVEL_MASK 0x00988168 /* */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_1CYCLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_2CYCLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_3CYCLE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_4CYCLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_SEL_TRNG 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_SEL_CAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_TRNG_ARB_SKIP_CNT_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR 0x00988720 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVR_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF 0x00988724 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_SUBP 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_SUBP_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_SUBP_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_SUBP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_SUBP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVF_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT 0x00988728 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DAT 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DAT_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DAT_SEL 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DAT_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DAT_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DQS 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DQS_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DQS_SEL 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DQS_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_DRVT_DQS_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR 0x00988730 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR_ADR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR_ADR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR_ADR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR_ADR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_SLWR_ADR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS 0x00988738 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVR 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVR_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVR_SEL 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVR_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVR_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVF 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVF_15 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVF_SEL 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVF_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_BYP_CS_DRVF_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0 0x009887D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD0_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD0_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD0_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD1_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD1_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD1_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD2_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD2_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD2_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD3_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD3_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD3_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD4_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD4_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD4_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD5_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD5_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD5_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD6_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD6_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD6_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD7_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD7_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD7_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD8_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD8_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD8_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD9_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD9_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD9_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD10_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD10_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD10_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD11_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD11_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD11_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD12_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD12_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD12_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD13_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD13_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD13_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD14_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD14_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD14_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD15_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD15_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL0_CMD15_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1 0x009887D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD16_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD16_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD16_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD17_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD17_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD17_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD18_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD18_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD18_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD19_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD19_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD19_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD20_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD20_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD20_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD21_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD21_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD21_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD22_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD22_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD22_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD23_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD23_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD23_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD24_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD24_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD24_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD25_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD25_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD25_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD26_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD26_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD26_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD27_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD27_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD27_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD28_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD28_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD28_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD29_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD29_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD29_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD30_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD30_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD30_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD31_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD31_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL1_CMD31_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2 0x009887D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD32 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD32_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD32_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD32_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD33 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD33_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD33_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD33_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD34 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD34_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD34_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD34_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD35 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD35_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD35_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD35_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD36 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD36_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD36_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD36_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD37 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD37_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD37_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD37_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD38 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD38_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD38_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD38_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD39 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD39_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD39_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD39_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD40 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD40_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD40_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD40_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD41 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD41_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD41_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD41_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD42 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD42_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD42_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD42_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD43 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD43_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD43_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD43_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD44 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD44_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD44_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD44_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD45 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD45_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD45_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD45_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD46 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD46_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD46_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD46_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD47 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD47_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD47_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL2_CMD47_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3 0x009887E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD48 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD48_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD48_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD48_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD49 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD49_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD49_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD49_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD50 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD50_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD50_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD50_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD51 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD51_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD51_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD51_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD52 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD52_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD52_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD52_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD53 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD53_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD53_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD53_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD54 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD54_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD54_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD54_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD55 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD55_ADR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD55_SUBP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_CAL_ADR_DRV_SEL3_CMD55_CS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG 0x009887E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CMD_STEP 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CMD_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CMD_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CK_STEP 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_CK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_WCK_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_WCK_STEP_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_WCK_STEP_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_BGCAL_FREEZE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CALCFG_BGCAL_FREEZE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x00989EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x00989ECC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x00989ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x00989ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x00989ED8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x00989EDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVR_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x00989EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x00989EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x00989EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x00989EEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x00989EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x00989EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVF_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x00989EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x00989EFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DAT_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x00989F00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x00989F04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_DQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x00989F08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP0_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x00989F0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVT_SUBP1_WDQS_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x00989F10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP0_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x00989F14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP0_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x00989F18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG 27:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVR_SUBP1_BG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x00989F1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_SUBP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_CMD_DRVF_SUBP1_CS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x00989F20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP0_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x00989F24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_RDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_CAL_SLV_DELTA_DRVDN_SUBP1_RX_WDQS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK 0x00989F28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DRVDN_BYP_SEL_INI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML 0x00989F34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_CLK_VML_SEL_VML 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK 0x00989F2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_TX_DRVDN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DRVDN_BYP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_TX_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DRVUP_BYP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DELTA_DRVR 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DELTA_DRVF 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_CAL_FREEZE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML 0x00989F38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_DELTA_DRVR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_DELTA_DRVF 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_SEL 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_SEL_CML 0x0 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CAL_WCK_VML_SEL_VML 0x1 /* RWI-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG 0x00988000 /* RWE4R */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_DLY_CNT__PROD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_EN 6:6 /* RWEVF */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STATE_CG_EN 7:7 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STATE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STATE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STATE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_DLY_CNT 13:8 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_EN 14:14 /* RWEVF */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_QUIESCENT_CG_EN 15:15 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_CNT 23:20 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_CNT__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_DI_DT_SKEW_VAL 27:24 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_EN 28:28 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_SW_OVER 29:29 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_PAUSE_CG_EN 30:30 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_PAUSE_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_HALT_CG_EN 31:31 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_HALT_CG_EN_ENABLED 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_HALT_CG_EN_DISABLED 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG_HALT_CG_EN__PROD 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG1 0x00988004 /* RWE4R */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG1_MONITOR_CG_EN 0:0 /* RWEVF */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */ #define NV_PFB_FBPA_MC_2_PRI_FBPA_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8 0x00988800 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU__PROD_C_DDR4 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INTERP_EDC_PWRD_ENABLE 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INTERP_EDC_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT 2:2 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_INTERP_EDC_PWRD_BIT_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG8_RFU_RDQS_RCVR_SEL_XOR 5:4 /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10 0x00988808 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_DQ 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_RDQS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_RDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_RDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_WDQS 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_CMD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPD_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_DQ 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_DQ_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_DQ_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_RDQS 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_RDQS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_RDQS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_WDQS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_WDQS_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_WDQS_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_CMD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WKPU_CMD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR3 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_IB_BRLSHFT__PROD_C_DDR5 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_DQ_TERM_MODE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_DQ_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_DQ_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_DQ_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_DQ_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_TERM_MODE 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WDQS_TERM_MODE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WDQS_TERM_MODE_NONE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WDQS_TERM_MODE_CTT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WDQS_TERM_MODE_PULLUP 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_WDQS_TERM_MODE_RFU 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_RDQS_DIFF_MODE 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_RDQS_DIFF_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_RDQS_DIFF_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_SRC_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_SRC_SEL_RDQS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_RDQS_SRC_SEL_WDQS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_INTERNAL_VREF 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_INTERNAL_VREF_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG10_E_INTERNAL_VREF_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BRLSHFT 0x00988820 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BRLSHFT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BRLSHFT_CMD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BRLSHFT_CMD_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD 0x00988824 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD__PRIV_LEVEL_MASK 0x0098886C /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CML_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CML_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CML_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_RDQS_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_INTERP_RDQS_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_PWRD 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_TX_PWRD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_GDDR5_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_LEGACY_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_RX_SCHMT_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_CTRL_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_ON 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_BIAS_DYNAMIC_CTRL_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CLK_TX_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CLK_TX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CLK_TX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCK_TX_PWRD 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCK_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCKB_TX_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCKB_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DIFFAMP_PWRD 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DIFFAMP_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DIFFAMP_PWRD_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_RX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQ_TX_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_DQDQS_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_QUSE_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CK_DIGDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_CK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCK_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_WCKB_DIGDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG_PWRD_RDQS_DIFFAMP_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11 0x00988828 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11__PRIV_LEVEL_MASK 0x0098886C /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_S_MACRO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_D_MACRO 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_S_PAD 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_D_PAD 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_LOOPBK_MODE_I_PAD 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CK_DEEPLOOP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_E_LPBK_INTERFACE_MODE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_E_LPBK_INTERFACE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_E_LP_MODE_CMD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_E_LP_MODE_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_WCK_DEEPLOOP_SEL 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_WCK_DEEPLOOP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_VEND_ID_C0_LOAD_EN 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_VEND_ID_C0_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_VEND_ID_C1_LOAD_EN 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_VEND_ID_C1_LOAD_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_PARALLEL_LPBK_MODE_EN 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_PARALLEL_LPBK_MODE_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_PARALLEL_LPBK_TX_EVEN_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CLAMP_VAL 23:23 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CLAMP_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CONFIG_CMD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG11_CONFIG_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12 0x0098882C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PVT_CODE_BYTE_C0_RB 10:8 /* R--VF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PVT_CODE_BYTE_C1_RB 13:11 /* R--VF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_INTRP_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_INTRP_8UI_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_INTRP_8UI_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_STEP16 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_STEP8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_STEP4 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_STEP2 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_STEP1 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CYA_SELECT_NO_STEP 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_TX_EN_EARLY 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_TX_EN_EARLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_DOUBLE_EDC_INTERP_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_IB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_PAM4_ODD_OB_BRLSHFT_CYA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_TAPERED_START 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_TAPERED_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_WCK_TAPERED_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CAP 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_INTERP_CAP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_CMD_BR8_DELAY 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_CMD_BR8_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_CMD_BR8_DELAY_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG12_CMD_BR8_DELAY_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1 0x00988830 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_BRLSHFT_LOWSPEED_MODE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_BUB_SEL_LOAD_CMD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_FBIO_SUBP_ENABLE_FUSE_OVERRIDE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_FBIO_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPRE_TWO 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPRE_TWO_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPRE_TWO_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPOST 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPOST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPOST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPREPOST_DQ_VALUE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPREPOST_DQ_VALUE_ZERO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WPREPOST_DQ_VALUE_ONE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WDQS_MODE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WDQS_MODE_WDQS_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_WDQS_MODE_WDQS_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_HOLD_DQ 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_HOLD_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_SETUP_DQ 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_SETUP_DQ_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_SETUP_STR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_EN_SETUP_STR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_CMD_BRLSHFT 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_CMD_BRLSHFT_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_CMD_BRLSHFT_BIT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_ON 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_SHORT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_NORMAL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_LONG 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_QUSE_FORCE_HIGH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_QUSE_FORCE_HIGH_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_QUSE_FORCE_HIGH_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_BIT2 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_EXTENDED_QUSE_BIT2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE_0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR1 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR2 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_ASSERT_QUSE__PROD_C_DDR3 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_PADMACRO_SYNC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_PADMACRO_SYNC_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_PADMACRO_SYNC_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_RCV_CLOCKING 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_RCV_CLOCKING_STROBE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_RCV_CLOCKING_CONTINUOUS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_CLK_ASSERT 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_CLK_ASSERT_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_TX_CLK_ASSERT_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_IB_PMACRO_PTR_OFFSET 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RUN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_IB_PMACRO_PTR_OFFSET_FIFO_RESET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_PADMACRO_RESET 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_PADMACRO_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_INTERP_RESET 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_INTERP_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_DDLL_INIT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_DDLL_INIT_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG1_DDLL_INIT_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE2 0x00988834 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE2_VALUE 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SPARE2_VALUE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C0 0x00988838 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C0_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C0_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C1 0x0098883C /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C1_VAL 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VEND_ID_C1_VAL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK 0x00988860 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_DLY_CK0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_DLY_CK0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_DLY_CK1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_DLY_CK1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_SEL_CML 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMOS_CLK_SEL_CMOS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK 0x00988864 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK 0x00988868 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE01_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_DISABLED 0x000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMOS_WCK_ON_BYTE23_ENABLED 0x000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL 0x00988870 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_RCV_CTRL_LANE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7 0x00988874 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7_CMD_RCV_CTRL 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7_CMD_RCV_CTRL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7_CMD_OB_SYNC_DLY 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG7_CMD_OB_SYNC_DLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL 0x00988890 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL__PRIV_LEVEL_MASK 0x0098886C /* */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_OB_BYTE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_BYTE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_CMD 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WCK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_TRAINING_PRIV 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_TRAINING_PRIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_FABRIC_FGCG 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_BLCG_BYTE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_WDQS_INTERP_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_DQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_WDQS_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_CMOS_CLK_GATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_EFFICIENT_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL 0x00988894 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF 14:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_EDC_PWRD_HOLDOFF_31 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF 19:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_INTERP_TURN_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 29:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1 0x00988898 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_WDQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CG 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_HORIZ_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_DQ_TX_E_CLK_OLD_DELAY_CYA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_DQ_DISABLE_ASR 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_DQ_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_DISABLE_ASR 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_WCK_DISABLE_ASR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_WCK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CK_DISABLE_ASR 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CK_DISABLE_ASR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_IB_CMD_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_MIN 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_CMD_TX_E_SER_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_E_PH0_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_E_PI_CLK_SYNC_GATING_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PWR_CTRL1_PAD_CMD_VERT_CLK_DIST_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L 0x009888C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_L_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H 0x009888CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE0_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE1_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE2_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE3_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE4_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE5_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE6_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_CONFIG_H_BYTE7_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL 0x009888D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK0_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK0_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK0_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK0_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK1 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK1_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK1_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK1_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CLK_CTRL_CLK1_GDDR5 0x00000066 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM 0x009888D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM_BYTE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM_BYTE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM_CMD 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_LOOPBK_TRIM_CMD_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY 0x009888D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE0 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE1 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE1 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE2 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE2 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE2_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE3 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE3 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE3_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE4 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE4 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE4_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE5 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE5 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE5_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE6 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE6 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE6_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE7 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ENABLE_LANE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE7 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_PARITY_ERROR_LANE7_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY 0x009888DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PARITY_ERR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR 2:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP0_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PARITY_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PARITY_ERR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PARITY_SUBP1_PRI_PARITY_ERR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG 0x00988E00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE_CML 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_ENABLE_CML_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_READY 16:16 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_LOCK 17:17 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSA 24:24 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSA_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSD 25:25 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_CML 26:26 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_CML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_4PHCML 27:27 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_4PHCML_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_DLL 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_DLL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_600 29:29 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_600_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_600_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_PLL_600_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF 0x00988E04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_NDIV_INIT 0x00000014 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_NDIV_MIN 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_SEL_DIVBY2 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_SEL_DIVBY2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_SEL_DIVBY2_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_COEFF_SEL_DIVBY2_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL 0x00988E08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_PLL_FREQLOCK 28:28 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_PLL_FREQLOCK_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_PLL_FREQLOCK_FALSE 0x0000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_PLL_FREQLOCK_TRUE 0x0000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_MON_TESTOUT 31:29 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_MON_TESTOUT_INIT 0x0000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_ENABLE_BG 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG2 0x00988E0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS 0x00988E14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_READY 0:0 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_LOCK 1:1 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK 2:2 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL0_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_READY 3:3 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_LOCK 4:4 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK 5:5 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL1_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_READY 6:6 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_LOCK 7:7 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK 8:8 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL2_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_READY 9:9 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_READY_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_LOCK 10:10 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_LOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK 11:11 /* R-IUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_PLL3_FREQLOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_SETUP2 19:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_DUAL_STATUS_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3 0x00988E18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DEBUG_DLL 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DEBUG_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_KCP_DLL 9:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_KCP_DLL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DELAYGAIN 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DELAYGAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_BYPASS_ASYNC 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_BYPASS_ASYNC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DLL_ENABLE 14:14 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_DLL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_SEL_DLLCLK 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_SEL_DLLCLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_TESTSEL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_TESTSEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_SPEEDUP 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_SPEEDUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_TESTEN 29:29 /* RWIUF */ #define NV_PFB_FBPA_MC_2_DRAMPLL_CFG3_TESTEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG 0x00988E20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_IDDQ 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_SYNC_MODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENB_LCKDET 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENB_LCKDET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENB_LCKDET_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_ENB_LCKDET_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_LOCK_OVERRIDE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_READY 16:16 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_READY_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_READY_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_LOCK 17:17 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSA 24:24 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSA_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSA_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSD 25:25 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSD_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_SSD_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_CML 26:26 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_CML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_CML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_4PHCML 27:27 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_4PHCML_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_4PHCML_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_DLL 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_DLL_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_DLL_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_PLL_600 29:29 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_EN_FSTLCK 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF 0x00988E24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_NDIV_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_NDIV_MIN 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL 0x00988E28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_EN_IREF 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_EN_IREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_MON_TESTOUT 31:29 /* R--UF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2 0x00988E2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SDM 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SDM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SDM_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SDM_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SSC 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SSC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SSC_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_SSC_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SSC_BYP 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SSC_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SSC_BYP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SSC_BYP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SDM_RESET 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SDM_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SDM_RESET_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_SDM_RESET_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER2 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER2_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SSD_EN_DITHER2_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SETUP2 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0 0x00988E30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0_SDM_SSC_STEP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0_SDM_SSC_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0_SDM_DIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD0_SDM_DIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1 0x00988E34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1_SDM_SSC_MAX 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1_SDM_SSC_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1_SDM_SSC_MIN 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_REFMPLL_SSD1_SDM_SSC_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK 0x0098A030 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x0098A034 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_fbpa_mem_wr_secure" /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_HISEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_GSP_SEC2_IFF_ENABLED_FUSE1 0x0000004C /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK 0x0098A038 /* RW-4R */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbpa_mem" /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_MEM_TR_CMD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR(i) (0x00988900+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_ROW 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_ROW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_EXTBANK 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_EXTBANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_BANK 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADR_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD(i) (0x00988910+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD__PRIV_LEVEL_MASK 0x0098A038 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_ADR 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WCK 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WCK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WCK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RD_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RD_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WR 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_WR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE_PRIME 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE_PRIME_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_QUSE_PRIME_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CHAR_ENGINE 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CHAR_ENGINE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CHAR_ENGINE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_PERIODIC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_PERIODIC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_PERIODIC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RW_LEVEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RW_LEVEL_BYTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_RW_LEVEL_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STROBE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STROBE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STROBE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CONTROL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CONTROL_TRIMMER 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CONTROL_DLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CONTROL_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_CONTROL_DLCELL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STEP 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STEP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_STEP_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_GO 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_GO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CMD_GO_NOW 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_TRAINING_DP(i) (0x00988918+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DP__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DP__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_LO 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_LO_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_HI 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_HI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD(i) (0x00988920+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_DBI 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_DBI_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_EDC 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_EDC_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_SEL 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_SEL_RD 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_SEL_WR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_SEL_LEGACY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DP_CNTD_SEL_CHAR_ENGINE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL(i) (0x009889C0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT 0x00000060 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WCK 0x00000064 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_SEQUENCER 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_INTERFACE 0x00000081 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ERROR_PATTERN 0x00000082 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ERROR_LIMIT_COUNT 0x00000083 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING8 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING9 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING10 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ADDR_PASSING11 0x0000005B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING0 0x00000016 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING1 0x00000017 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING2 0x00000018 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING3 0x00000019 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING4 0x0000001A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING5 0x0000001B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING6 0x0000001C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING7 0x0000001D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_DBI 0x0000001E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_EDC 0x0000001F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG_PASSING_BYTE 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG0 0x00000040 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG1 0x00000041 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_TAG2 0x00000042 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH0 0x00000046 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH1 0x00000047 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_IB_WIDTH2 0x00000048 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH0 0x00000049 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH1 0x0000004A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_OB_WIDTH2 0x0000004B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE0 0x00000061 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE1 0x00000062 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT_WIDE2 0x00000063 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT0 0x00000070 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT1 0x00000071 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT2 0x00000072 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT3 0x00000073 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE0 0x00000074 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE1 0x00000075 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE2 0x00000076 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE3 0x00000077 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE4 0x00000078 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE5 0x00000079 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE6 0x0000007A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE7 0x0000007B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE8 0x0000007C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_ERRCNT_WIDE9 0x0000007D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ADDR 0x0000007F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_L 0x00000084 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DQ_U 0x00000085 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_ECC 0x00000086 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_HBM_CHAR_1ST_ERR_DBI 0x00000087 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_ADDR 0x0000008E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_1ST_ERR_PIN 0x0000008F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_0 0x00000090 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_1 0x00000091 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_2 0x00000092 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_3 0x00000093 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_AREA_4 0x00000094 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_0 0x00000095 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_1 0x00000096 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_2 0x00000097 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_3 0x00000098 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_MAX_AREA_4 0x00000099 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_0 0x0000009a /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_1 0x0000009b /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_2 0x0000009c /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_3 0x0000009d /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_ACCUM_WIN_4 0x0000009e /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_0 0x000000a0 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_1 0x000000a1 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_MIN_FRAC_2 0x000000a2 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_0 0x000000a3 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_1 0x000000a4 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_RD_WIN_FRAC_2 0x000000a5 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_0 0x000000a6 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_1 0x000000a7 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_MIN_FRAC_2 0x000000a8 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_0 0x000000a9 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_1 0x000000aa /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_WR_WIN_FRAC_2 0x000000ab /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING4 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING5 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING6 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING7 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_DBI 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_EDC 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_PASSING_BYTE 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT0 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT1 0x00000031 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT2 0x00000032 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT3 0x00000033 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT4 0x00000034 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT5 0x00000035 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT6 0x00000036 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT7 0x00000037 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT8 0x00000038 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT9 0x00000039 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT10 0x0000003A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT11 0x0000003B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT12 0x0000003C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT13 0x0000003D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT14 0x0000003E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_CHAR_ERRCNT15 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING0 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING2 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING3 0x0000000E /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING4 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING5 0x00000010 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING6 0x00000011 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING7 0x00000012 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_DBI 0x00000013 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_EDC 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK0_PASSING_BYTE 0x00000015 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING0 0x00000050 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING1 0x00000051 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING2 0x00000052 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING3 0x00000053 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING4 0x00000054 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING5 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING6 0x00000056 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING7 0x00000057 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_DBI 0x00000058 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_EDC 0x00000059 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_SELECT_DQ_QUSE_RANK1_PASSING_BYTE 0x0000005A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_RISING_DEV1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_WATCH_FALLING_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP0_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP1_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP2_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV01 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_ADDR_COMP3_X8_WATCH_DEV23 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_WINDOW_LIMIT 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_CTRL_WINDOW_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0(i) (0x00988938+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR4 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR4_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR5 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR5_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR6 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR6_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR7 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR7_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ0_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1(i) (0x00988940+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR8 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR8_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR9 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR9_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR10 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR10_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR11 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR11_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR12 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR12_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR13 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR13_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR14 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR14_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR15 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR15_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ1_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2(i) (0x00988948+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR16 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR16_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR17 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR17_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR18 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR18_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR19 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR19_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR20 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR20_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR21 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR21_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR22 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR22_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR23 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR23_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ2_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3(i) (0x00988950+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR24 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR24_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR25 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR25_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR26 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR26_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR27 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR27_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR28 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR28_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR29 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR29_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR30 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR30_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR31 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR31_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_MIN_PASSING 11:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_MAX_PASSING 23:12 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_WINDOW_COUNT 31:28 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR0_WIDE 7:0 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR1_WIDE 15:8 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR2_WIDE 23:16 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_DQ3_ERR3_WIDE 31:24 /* ----F */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0(i) (0x00988958+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR0 3:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR1 7:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR2 11:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR3 15:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_EDC_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR0 19:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR0_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR1 23:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR1_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR2 27:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR2_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR3 31:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC0_DBI_ERR3_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1(i) (0x00988960+(i)*4) /* R--4A */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR0 9:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR0_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR0_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR0_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR1 11:10 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR1_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR1_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR1_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC0 13:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC0_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC0_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC0_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC1 15:14 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC1_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC1_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC1_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR2 25:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR2_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR2_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR2_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR3 27:26 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR3_NONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_EARLY 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR3_NO_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_ERR3_BOTH 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC2 29:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC2_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC2_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC2_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC3 31:30 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC3_EARLY 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC3_LATE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_DEBUG_MISC1_WCK_EDC3_TRANS 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR(i) (0x00988968+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ADR 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ADR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ADR_ACT_MAX 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ADR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_DP 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_DP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_DP_TRAIN_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_DP_CHAR_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ACT_ADR 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ACT_ADR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATTERN_PTR_ACT_ADR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING 0x00988970 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_ADRTRM_SETTLE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_ADRTRM_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_ADRTRM_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_ADRTRM_FLUSH 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_ADRTRM_FLUSH_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_VREF_SETTLE 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_VREF_SETTLE_INIT 0x0000006E /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_INTRPLTR_SETTLE 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_INTRPLTR_SETTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING_INTRPLTR_SETTLE_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2 0x009889C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2_PRIV_DELAY 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2_PRIV_DELAY_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2_APPLY_DELAY 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING2_APPLY_DELAY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING3 0x0098A050 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING3_TVREFD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TIMING3_TVREFD_INIT 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL 0x0098A054 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_MIN_INIT 0x00000038 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_MAX_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PI_OFFSET_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS 0x00988974 /* R--4R */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP0_STATUS 1:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP0_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP0_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP0_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP0_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP1_STATUS 3:2 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP1_STATUS_FINISHED 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP1_STATUS_RUNNING 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP1_STATUS_ERROR 0x00000002 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_STATUS_SUBP1_STATUS_STEP_DONE 0x00000003 /* R---V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL 0x00988978 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FAST_UPDATES 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FAST_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FAST_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASR_FAST_EXIT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASR_FAST_EXIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASR_FAST_EXIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_DELAY 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_DELAY_2UI 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_DELAY_4UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASYNC_UPDATES 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASYNC_UPDATES_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_ASYNC_UPDATES_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DFE_OVERRIDE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DFE_OVERRIDE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DFE_OVERRIDE_FORCE_DISABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DFE_OVERRIDE_FORCE_ENABLE_CLEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_EXTENDED_RW_OFFSET 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_EXTENDED_RW_OFFSET_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_EXTENDED_RW_OFFSET_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_G5X_EDC_TR_MODE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_G5X_EDC_TR_MODE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_G5X_EDC_TR_MODE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_VREF_TRAINING 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_VREF_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_VREF_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_TRAINING 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_CORS_INTRPLTR_TRAINING 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_CORS_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FINE_INTRPLTR_TRAINING 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FINE_INTRPLTR_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_TRIMMER_TRAINING 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_TRIMMER_TRAINING_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_TRIMMER_TRAINING_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_STOP_CLOCKS 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_STOP_CLOCKS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_STOP_CLOCKS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_EARLY_FLIP 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_EARLY_FLIP_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_EARLY_FLIP_DIABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP0_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_QIMONDA_SWAP_SUBP1_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_STALL_CMDQ 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_STALL_CMDQ_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_STALL_CMDQ_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_QUICK 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DOUBLE_CORS_RANGE 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DOUBLE_CORS_RANGE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_DOUBLE_CORS_RANGE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_RD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_RD_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_RD_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_WR 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_WR_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_FIRST_PARTIAL_WR_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_PADS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_PADS_FOUR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_WCK_PADS_EIGHT 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_INTRPLTR_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_BRLSHFT_INTRPLTR_WR_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL 0x0098897C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_START_WAIT 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_START_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_START_EN_WAIT 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_START_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_START_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_FINISH_WAIT 26:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_FINISH_WAIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_FINISH_EN_WAIT_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_REFRESH 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_REFRESH_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_REFRESH_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_WAIT_IDLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_WAIT_IDLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_LEGACY_CTRL_WAIT_IDLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2 0x0098A040 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_USE_RD_DBI_EXPECTED 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_USE_RD_DBI_EXPECTED_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_SWEEP_PHASE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_SWEEP_PHASE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_SWEEP_PHASE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_USE_BL16 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_USE_BL16_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_USE_BL16_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_WR 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_RD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_SHIFT_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_CORS_STEP_OVERRIDE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_CORS_STEP_OVERRIDE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_CORS_STEP_OVERRIDE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_WR 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_RD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_INV_PATT_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_RD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_RD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_RD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_WR 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_WR_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_PI_OFFSET_WR_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_DCC 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_DCC_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_DCC_HOLD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_DCC_TRACK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_QUICK_WCK 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_QUICK_WCK_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_QUICK_WCK_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_8UI_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_8UI_MODE_G6 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL2_WCK_8UI_MODE_G6X 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL 0x0098A070 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_BS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_BS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_BS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_CORS 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_CORS_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALT_CORS_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALF_FBPA 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALF_FBPA_EN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_HALF_FBPA_DIS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_RX_CAPTURE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_RX_CAPTURE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_RX_CAPTURE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_DELAY_ASYNC_UPD_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_BS_FOR_CA_TR 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_MISC_CTRL_BS_FOR_CA_TR_2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG 0x00988A00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_TAG 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_TAG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL_ALWAYS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL_GREATER_PIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL_GREATER_BYTE 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL_GREATER_DOUBLE_BYTE 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_STORE_OPTIMAL_GREATER_DRAM 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_FIRST_TAG 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_FIRST_TAG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_FIRST_TAG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_TAG_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM 0x00988A04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_CHAR_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_CHAR_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_CHAR_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_CHAR_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_CHAR_MAX_MAX 0x0000005F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_BURST_CNT 22:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_BURST_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_INV_EN 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_INV_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_INV_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_PATTERN_LEN 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS7 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS9 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS11 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_PATTERN_LEN_PRBS23 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_DUAL_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_DUAL_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_DUAL_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_ACCESS_UPPER32 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_ACCESS_UPPER32_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_ACCESS_UPPER32_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_USE_RESET_LAST 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_USE_RESET_LAST_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_USE_RESET_LAST_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_OVERRIDE_TRAINING 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_OVERRIDE_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_OVERRIDE_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT 0x00988AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_RD 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_WR 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_PERIODIC_RD 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_PERIODIC_RD_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_PERIODIC_WR 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT_PERIODIC_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2 0x00988AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2_ADDR_START 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2_ADDR_START_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2_ADDR_END 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_SELECT2_ADDR_END_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER 0x00988A08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MAX 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_THRESHOLD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_THRESHOLD_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x00988AC0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ4_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ5_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ6_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ7_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ8_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ9_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ10_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ11_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ12_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ13_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ14_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_LOWER_DQ15_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x00988AC8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ16_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ17_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ18_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ19_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ20_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ21_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ22_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ23_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ24_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ25_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ26_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ27_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ28_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ29_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ30_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_UPPER_DQ31_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x00988AD0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI0_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI1_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI2_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_COUNTER_MASK_MISC_DBI3_INVERTED 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL 0x00988A0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_MODE_SINGLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_MODE_SWEEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_SWEEP_START 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_SWEEP_START_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_SWEEP_START_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_START_COUNT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_START_COUNT_ZERO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_START_COUNT_ACCUMULATE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_STOP_ON_ERROR 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_STOP_ON_ERROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_STOP_ON_ERROR_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_REFRESH 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_HOLD_TRAFFIC 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_AFTER 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_HOLD_TRAFFIC_ALWAYS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_NUM_BANKS 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_NUM_BANKS_1 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_NUM_BANKS_2 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_FUNC_MTA 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_FUNC_MTA_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_FUNC_MTA_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_DBI_THRESHOLD 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_DBI_THRESHOLD_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_PATTERN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_DBI_COMPARE_MODE_DATA 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ(i) (0x00000001 + (i)) /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DQ__SIZE_1 31 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI0 0x00000020 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI1 0x00000021 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI2 0x00000022 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_DBI3 0x00000023 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC0 0x00000024 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC1 0x00000025 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC2 0x00000026 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_RD_EDC3 0x00000027 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC0 0x00000028 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC1 0x00000029 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC2 0x0000002A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_WR_EDC3 0x0000002B /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_CTRL_ANALYSIS_PIN_ALL 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST 0x00988A10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST_COUNT_1BANK_LIMIT 0x00000100 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST_COUNT_2BANK_LIMIT 0x00000200 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BURST_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_TURN 0x00988A14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_TURN__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_TURN_COUNT 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_TURN_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_TURN_COUNT_MAX 0xFFFFFFFE /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL 0x00988A18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_MIN 11:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_MAX 23:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_INTRPLTR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_DDLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_IB_TRIMMER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_INTRPLTR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_DQ_OB_TRIMMER 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_DDLL 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_QUSE_TRIMMER 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_DDLL 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_SWEEP_CTRL_SETTING_ADR_INTRPLTR 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL 0x00988AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_ENABLE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_ENABLE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_MIN 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_MAX 9:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_MAX_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_MIN 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_MIN_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_MAX 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_MAX_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_PREA 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_PREA_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_PREA_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_RANK 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_A_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_RANK 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_SET_B_RANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_REFA 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_REFA_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL_REFA_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2 0x00988ADC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_A_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_BURST_CNT_B_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CHAR_BANK_CTRL2_LOOP_CNT_FOREVER 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL 0x009889CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ADR_SETTING 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ADR_SETTING_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ADR_MAX 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ADR_MAX_INIT 0x00000018 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ENABLE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_TADR_CTRL_ENABLE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL 0x009889D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL 0x009889D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_MIN_INIT 0x00000080 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL 0x00988984 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_X8_MODE 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_X8_MODE_BOTH 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_X8_MODE_RISING_ONLY 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_X8_MODE_FALLING_ONLY 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_MIRROR 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_MIRROR_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_MIRROR_SUBP0 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_MIRROR_SUBP1 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_MIRROR_BOTH 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_REFRESH 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_REFRESH_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_REFRESH_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_REF_CNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_REF_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_1TCK 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_3TCK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_5TCK 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_31TCK 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_SKIP_CNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ADDR_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL 0x00988988 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x009889D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_MAX_INIT 0x000000F0 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_INIT 0x00000010 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_VOTE_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL 0x009889DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_MAX_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_STEP 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_DDLL_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_TRIMMER_CTRL 0x009889E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_TRIMMER_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_TRIMMER_CTRL_STEP_LN_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x0098898C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_OFFSET_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_BIG_TIMER_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_ASR_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV0 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_SELECT_DEV1 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_CTRL_EXT_MODE_X16_NORMAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x00988A1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL_SLOW_STEP_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_LEGACY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_INTRPLTR_EXIT_CTRL_MODE_OPTIMAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT 0x00988990 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_EARLY_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MIN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MIN_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MAX 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MAX_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_WCK_EDC_LIMIT_LATE_MAX_MAX 0x00000080 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL 0x009889F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_MAX_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_STEP_LN 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CORS_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL 0x009889F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_MIN_INIT 0x000000D8 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_FINE_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL 0x009889FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_CORS_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_FINE_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_BURST_COUNT 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_QUSE_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL 0x00988AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_LEG_TRIM_TRAINING_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_RPT_MODE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_RPT_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL_RPT_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2 0x00988AEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_ERR_LIMIT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_ERR_LIMIT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_BURST_COUNT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_BURST_COUNT_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_MIN_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_MAX_7 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL2_LEG_TRIM_STEP_LN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3 0x00988AFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_DLCELL_CTRL3_LEG_TRIM_OUTER_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR 0x00988AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_MODE 2:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_MODE_SERIAL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_MODE_PARALLEL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_MODE_STAGGER 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PATTERN 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PATTERN_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PATTERN_CUSTOM 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DRAM_DEVICE 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DRAM_DEVICE_X4 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DRAM_DEVICE_X8 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DRAM_DEVICE_X16 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DRAM_DEVICE_X32 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PAGE_SELECT 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_PAGE_SELECT_PAGE3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_0 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_0_MPR0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_0_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_0_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_0_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_1 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_1_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_1_MPR1 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_1_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_1_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_2 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_2_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_2_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_2_MPR2 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_2_MPR3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_3 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_3_MPR0 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_3_MPR1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_3_MPR2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_READ_ADR_3_MPR3 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_RPT_ORDER 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_RPT_ORDER_MPR_RPT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_RPT_ORDER_RPT_MPR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA 0x00988AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR0_DEFAULT 0x00000055 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR1_DEFAULT 0x00000033 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR2_DEFAULT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_CTRL_MPR_DATA_MPR3_DEFAULT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL 0x00988994 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL_CMD_CNT 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR5_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL_CMD_CNT_DDR3_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_LDFF_CTRL_CMD_CNT_GDDR6X_MAX 0x0000000f /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL 0x00988998 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_MIN 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_MAX 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_MAX_INIT 0x00000035 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_STEP_LN 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x009889E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL_RD_INIT 0x00000013 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_BRLSHFT_QUICK_CTRL_WR_INIT 0x00000011 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL 0x0098899C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_INTRPLTR_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL 0x009889A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_INTRPLTR_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL 0x009889E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_MIN 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_MAX 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_MAX_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_STEP 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_CORS_DDLL_CTRL_STEP_LN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL 0x009889EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_MIN_INIT 0x00000058 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_MAX_INIT 0x00000028 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_FINE_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL 0x009889A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_MAX_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_TRIMMER_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL 0x009889A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_AREA_BASED_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_AREA_BASED_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_QUICK 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_QUICK_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_QUICK_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MODE_ABSOLUTE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_VREF_CTRL_MODE_OFFSET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT 0x009889AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_CORS_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_FINE_INTRPLTR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_TRIMMER 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_TRIMMER_MIN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_ERR_LIMIT_TRIMMER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL 0x009889B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_EN_AVG 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL_EN_AVG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL 0x009889F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_MIN_INIT 0x00000041 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_MAX_INIT 0x0000003F /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_CMD_CNT_MAX 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_INIT 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_32 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_64 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_128 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_256 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_512 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_1024 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_DDLL_CTRL_STEP_LN_MAX 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2 0x009889B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2_SKIP_VC1_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL2_SKIP_CNT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3 0x0098A048 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_RD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_PERIODIC_CTRL3_AVG_FACTOR_WR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL 0x0098A04C /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL_EDC_TRACKING_MODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_DIS 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL_EDC_TRACKING_MODE_EN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME 29:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_EDC_CTRL_EDC_RELOCK_WAIT_TIME_10 0x0000000a /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL 0x0098A044 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_MIN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_MIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_MAX 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_MAX_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_STEP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_EN 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_AREA_BASED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_AREA_BASED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_WR_VREF_CTRL_AREA_ACCUM_MAX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x00988A20+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x00988A28+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x00988A30+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x00988A38+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x00988A40+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_IB_MISC_EDC3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x00988A48+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE0_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x00988A50+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE1_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x00988A58+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE2_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x00988A60+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ0_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ1_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ2_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ3_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ4_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ5_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ6_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_BYTE3_DQ7_INIT 0x000000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x00988A68+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI0_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI1_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI2_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_EYE_CENTER_OB_MISC_DBI3_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x00988A70+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x00988A78+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x00988A80+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x00988A88+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC(i) (0x00988A90+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC0 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC1 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC2 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC3 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_IB_MISC_EDC3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x00988A98+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE0_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x00988AA0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE1_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x00988AA8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE2_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x00988AB0+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ0_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ1_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ2_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ3_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ4_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ5_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ6_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_BYTE3_DQ7_INIT 0x000000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC(i) (0x00988AB8+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_RW_OFFSET_OB_MISC_DBI3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_SEED(i) (0x0098A000+(i)*4) /* RW-4A */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_SEED__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_SEED_VAL 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PATRAM_PRBS_SEED_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL 0x0098A060 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_READ 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_WRITE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_ADDR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_ABI 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_WCK 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_FULL_PERIODIC 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_PHASE 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_PHASE_FINE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_PHASE_CORS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_CTRL_PHASE_BS 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_FULL 0x0098A064 /* R--4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_FULL__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_FULL_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_FULL_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_PHASE 0x0098A068 /* R--4R */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_PHASE__PRIV_LEVEL_MASK 0x0098A030 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_PHASE_DATA 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_TRAINING_PROFILE_PHASE_DATA_0 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL 0x0098A074 /* RW-4R */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL__PRIV_LEVEL_MASK 0x0098A034 /* */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_DISABLED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_GDDR5_COMMANDS_ENABLED 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_PRBS_MODE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_PRBS_MODE_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_TRAINING_ARRAY_CTRL_PRBS_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG 0x0098A078 /* RW-4R */ #define NV_PFB_FBPA_MC_2_SW_CONFIG__PRIV_LEVEL_MASK 0x0098A034 /* */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PTRIM_OPT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PTRIM_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PTRIM_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_SELFREF_OPT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_SELFREF_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_SELFREF_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_MSCG_OPT 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_MSCG_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_MSCG_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_GC6_HIB_OPT 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_GC6_HIB_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_GC6_HIB_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PA_FALCON_OPT 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PA_FALCON_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_PA_FALCON_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_INTRPLTR_OFFSET_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_SW_CONFIG_EDC_TR_VREF_SAVE_AND_RESTORE_OPT_SET 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1 0x0098A07C /* RW-4R */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1__PRIV_LEVEL_MASK 0x0098A034 /* */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_TRAFFIC 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_TRAFFIC_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_TRAFFIC_MANUAL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_MANUAL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_MANUAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_ACTIVE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_ACTIVE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_THROTTLE 11:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_THROTTLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_BANK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG1_BANK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_NOISE_CFG2 0x0098A080 /* RW-4R */ #define NV_PFB_FBPA_MC_2_NOISE_CFG2__PRIV_LEVEL_MASK 0x0098A034 /* */ #define NV_PFB_FBPA_MC_2_NOISE_CFG2_BURST 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_NOISE_CFG2_BURST_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK 0x00988B04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB 0x00988B14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK 0x00988B08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCK_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB 0x00988B18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_INTRPLTR_BYTE23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE01_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_NORMAL 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_WCKB_CTRL_BYTE23_FLIP 0x00000055 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL 0x00988EE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL_SLOW_COUNT_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_WCK_STEP_CTRL_SLOW_ENABLE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CTRL 0x00988B0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CTRL 0x00988B10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CTRL_CK_INTRPLTR_BYTE01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET 0x00988B00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_IB 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_IB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_OB 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_OB_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_ADDR 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_ADDR_MIN 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_WCK 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTRPLTR_OFFSET_WCK_MIN 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x00988B20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x00988B24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x00988B28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x00988B2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x00988B30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x00988B34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x00988B38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x00988B3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x00988B40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x00988B44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x00988B48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x00988B4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x00988B50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x00988B54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x00988B58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x00988B5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x00988B60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x00988B64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x00988B68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x00988B6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x00988B70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x00988B74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x00988B78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x00988B7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x00988BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x00988BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x00988BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x00988BCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x00988BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x00988BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x00988BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x00988BDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x00988BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x00988BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x00988BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x00988BEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x00988BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x00988BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x00988BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x00988BFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x00988C00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x00988C04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x00988C08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x00988C0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x00988C10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x00988C14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x00988C18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x00988C1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x00988C20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x00988C24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x00988C28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x00988C2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x00988C30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x00988C34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x00988C38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x00988C3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x00988C40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x00988C44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x00988C48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x00988C4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x00988C50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x00988C54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x00988C58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x00988C5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x00988C60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x00988C64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x00988C68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x00988C6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x00988C70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x00988C74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x00988C78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x00988C7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x00988CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x00988CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x00988CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x00988CCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x00988CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x00988CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x00988CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x00988CDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x00988CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x00988CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x00988CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x00988CEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x00988CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x00988CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x00988CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x00988CFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x00988D00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x00988D04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x00988D08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x00988D0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x00988D10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x00988D14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x00988D18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7 30:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x00988D1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10 22:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x00988D70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x00988D74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x00988D78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x00988D7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x00988D80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x00988D84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x00988D88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x00988D8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR3_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x00988D90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR4_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x00988D94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR5_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x00988D98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD0_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD1_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD3_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x00988D9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD9_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x00988DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x00988DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD0_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD1_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD2_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD3_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD4_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD5_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD6_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT1_PAD7_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x00988DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD8_S4_GEAR 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD9_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD10_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD11_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD12_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD13_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD14_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT2_PAD15_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x00988DAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD16_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD17_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD18_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD19_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD20_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD21_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD22_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT3_PAD23_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x00988DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x00988DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x00988EE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x00988EE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE0_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE1_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE2_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1_BYTE3_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD 0x00988D28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_IB_DLCELL 0x0000000B /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_QUSE_DDLL_RANK1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_LEG_TRIM 0x0000000D /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD 0x00988D2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_WCK_CLK_OFF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_CMOS_WCKTR_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_TRAINING_SOURCE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_EDC_BRLSHFT_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQS_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_HOLD_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_ONLY 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_UPDATE_MODE_INCR_DECR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_VREF_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_LEG_TRIM_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DFE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_ABI_TRAINING_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_NONE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_INTRPLTR 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_INTRPLTR 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_DDLL 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_DDLL 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_IB_TRIM 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_OB_TRIM 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_INTRPLTR 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_DDLL 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_ADR_INTRPLTR 0x00000009 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_QUSE_DDLL 0x0000000A /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_MODE_WCK_EXIT 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_QUSE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_DISABLE_DQ_UPDATE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_PRIV_CMD_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL 0x00988D30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP0_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_SMT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RCVR_SEL_SUBP1_AMP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_CMD_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_DIGDLL_PWRD_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_TX_DCC_MODE 27:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_TX_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_PHASE0_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_PAD_CTRL_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL 0x00988D34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP0_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_SER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_TX_PWRD_CLK_INTERFACE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_ON 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_RX_BIAS_CTRL_SUBP1_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_CLK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE 30:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_E_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CLK_PAD_CTRL_WCK_DRV_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0 0x00988D38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL0_DQ30_RX_LEG_TRIM_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2 0x00988D40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_VREF_PWRD 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_VREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_E_RX_DFE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE 10:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TX_DCC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TX_E_DCC 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TX_E_DCC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_E_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_SCHMT_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RDQS_RX_LP4_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_DQ_PHASE0_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_IREF_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_INTERP_LSB_IGNORE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_E_RX_DFE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_PI_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_SETTLING_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_SEL_DEEP_STROBE_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_TEST_EN_PH0_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL2_RX_E_NRZ_DF_DFE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1 0x00988DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2 0x00988DBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1 0x00988DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2 0x00988DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1 0x00988DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2 0x00988DCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1 0x00988DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2 0x00988DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1 0x00988DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2 0x00988DDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1 0x00988DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2 0x00988DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1 0x00988DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2 0x00988DEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1 0x00988DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2 0x00988DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD8 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD9 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD10 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_RX_DFE2_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x009885A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x009885A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x009885A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x009885AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x009885B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x009885B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x009885B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x009885BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x009885C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x009885C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x009885C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x009885CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x009885D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x009885D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x009885D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x009885DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x009885E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_TX_E_PREEMPH_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL 0x009885E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_HALF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PU_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_PD_EB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_16FF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC 27:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_TX_E_PREEMPH_CTRL_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC 0x00988D44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_CMD_CONFIG 13:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_CMD_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_DQ_CONFIG 23:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_DQ_CONFIG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_LOOPBACK_RX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_MODE 28:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_FEA_RX_AC_COUPLED_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC_E_LOOPBACK_FEA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1 0x00988D48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DQ_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_WDQS_TX_USE_ONLY_PH0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DQ_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DFE_CTRL 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_DFE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_RFU 20:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_WCK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_PAD_CTRL_MISC1_CK_TX_EQ_AC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL 0x00988EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_RX_CTRL_BYTE7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL 0x00988EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE2_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE3_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE4_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE5_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE6_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_BYTE_INTERP_CTRL_BYTE7_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL 0x00988EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_RX_SUBP0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_RX_SUBP0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_SUBP0 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_SUBP0_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_RX_SUBP1 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_RX_SUBP1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_SUBP1 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_SUBP1_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP0_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_CMD_CTRL_INTERP_CLK_SUBP1_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL 0x00988EBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP0_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_CTRL_SUBP1_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL 0x00988ED0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP0_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCK23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB01_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_IREF_WCK_INTERP_CTRL_SUBP1_WCKB23_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL 0x00988EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL_CLKDIST_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL_CLKDIST_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2 0x00988EC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_VTT_LV_VAUXC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_SPARE 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CDB_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_IREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_IREF_PWRD 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CK_IREF_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_WCK_IREF_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_WCK_IREF_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_WCK_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_CMD_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG 23:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IBG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL2_DQ_ISOURCE_CTRL_IMIX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3 0x00988EEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL3_DQ_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4 0x00988EF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_BW 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST 10:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_BW 14:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VAUXP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_BW 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_E_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL4_CMD_VCLAMP_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5 0x00988EF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VCLAMP_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD 9:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD 11:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VCLAMP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD 15:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VAUXP_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD 17:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_SPARE 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_DQ_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_SPARE 21:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CNTL5_CMD_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL 0x00988EF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_DQ_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_DQ_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_CMD_MDDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MDDLL_CNTL_CMD_BYPASS_FINE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG 0x00988ECC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_CK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_WCK 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_WCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_WCK_PATTERN_MASK 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_MISC_CONFIG_WCK_PATTERN_MASK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2 0x00988ED4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_TX_DRVDN 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_TX_DRVDN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_TX_DRVUP 9:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_TX_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_E_PU40 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_E_PU40_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DRVDN_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DRVUP_BYP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_FREEZE 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DELTA_DRVR 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DELTA_DRVF 21:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR 25:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVR_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_WCK_CAL_DELTA_DRVF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_FORCE_CAL_UPDATE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CML_CLK2_FORCE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0 0x00989004 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_FBIO_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_FBIO_ENABLE_SET 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_FBIO_ENABLE_CLR 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_FBIO_IFIFO_PTR_RESET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_LOOPBK_MODE 4:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_LOOPBK_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_TX_EN_SETUP 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_TX_EN_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_BRLSHFT 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_BRLSHFT_1UI 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_BIST_MODE_DBI_LANE_REPAIR_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_DRAM_ECC 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_DRAM_ECC_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_DRAM_ECC_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_LEKAGE_STRENGTH 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG0_LEKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_1 0x00989008 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_1_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_1_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_2 0x0098900C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_2_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_SPARE_2_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL 0x00989010 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DQS_RX_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_OB_BYTE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_OB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_BYTE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_CMD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_DQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_FGCG__PROD 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_BLCG_BYTE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_BLCG_BYTE_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_BLCG_BYTE_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_EFFICIENT_RCVR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_DYNAMIC_RDQS_RCVR_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF 17:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_32 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_RX_FABRIC_PWRD_HOLDOFF_64 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_ENABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_PWR_CTRL_IB_FABRIC_CG_DISABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL 0x00989014 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_RD_PWRD_HOLDOFF_30 0x0000001E /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_WR_PWRD_HOLDOFF_22 0x00000016 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_PRIV_PWRD_HOLDOFF_12 0x0000000C /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_OFF 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BLCG_CTRL_CAL_REFRESH_PWRD_HOLDOFF_8 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG 0x00989018 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_CLK_CNTRL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_CLK_CNTRL_NORMAL 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_CLK_CNTRL_STOP 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_CLK_CNTRL_FLIP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_CFG_COMBINED_CLK_OFF_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY 0x00989020 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR 5:5 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR 7:7 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL0_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR 9:9 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR 11:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD2_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_FABRIC_PARITY_CHANNEL1_DWORD3_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY 0x00989024 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR 1:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL0_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR 3:3 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL1_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR 4:4 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_FABRIC_PARITY_CHANNEL_PRIV_ERROR_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x0098903C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x00989040 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x00989044 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x00989048 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x0098904C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x00989050 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x00989054 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x00989058 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x0098905C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x00989060 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x00989064 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x00989068 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x0098906C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x00989070 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x00989074 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x00989078 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x0098907C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x00989080 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x00989084 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x00989088 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x0098908C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x00989090 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x00989094 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x00989098 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x0098909C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x009890A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_TX_DQ_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1_BRICK_RX_DQ_PWRD_INIT 0x003FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x009890A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_DQ_PWRD_INIT 0x000FFFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_WDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_TX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_WDQS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_RDQS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_CLK_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_BYPASS_DIV2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_BRICK_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_WL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_TX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2_DDLL_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x009890A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x009890AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x009890B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x009890B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x009890B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x009890BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x009890C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x009890C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x009890C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_E_DIFF_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE 21:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_RDQS_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE 25:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_DQ_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE 0x009890CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_RFU_DQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_RFU_CMD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_TEMP 31:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG3_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG4_BRICK_SPARE 0x009890D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG4_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG4_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG4_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG5_BRICK_SPARE 0x009890D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG5_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG5_BRICK_SPARE_TEMP 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG5_BRICK_SPARE_TEMP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x009890D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x009890DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x009890E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x009890E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x009890E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x009890EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x009890F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x009890F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x009890F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x009890FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x00989100 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x00989104 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x00989108 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x0098910C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x00989110 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x00989114 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x00989118 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x0098911C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x00989120 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x00989124 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x00989128 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x0098912C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x00989130 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x00989134 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL_DATA_DLYMATCH_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x00989138 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x0098913C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_TRIM_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x00989140 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL 14:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH 18:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_DATA_DLYMATCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET 25:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_OFFSET_INIT 0x0000004A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x00989144 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x00989148 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x0098914C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x00989150 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x00989154 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL 0x00989158 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY 8:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_DELAY_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT 14:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_SAMPLE_COUNT_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS 20:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_FILTER_BITS_MAX 0x00000014 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_START_TRM 31:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL_START_TRM_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1 0x009891DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_END_COUNT_CONTINUOUS 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_IGNORE_START_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_STOP 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CALIBRATE_GO 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CLK_GATE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x00989160 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x00989164 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x00989168 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x0098916C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x00989170 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x00989174 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x00989178 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x0098917C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x00989180 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_CODE_INIT 0x00000064 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x00989184 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x00989188 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x0098918C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x00989190 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x00989194 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x00989198 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x0098919C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x009891A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_CODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_AUTO 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_SEL_BYPASS 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x009891A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_CODE_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_AUTO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_SEL_BYPASS 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN_DELTA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG 0x009891A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_DISABLE_CAL_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_FREEZE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_FREEZE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_CMD_STEP 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_CMD_STEP_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_SAMPLE_COUNT 6:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALCFG_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x009891B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x009891B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x009891BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x009891C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x009891C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x009891C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x009891CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x009891D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_CODE_INIT 0x0000FFFF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR 0x009891D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL0_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE 16:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_CODE_INIT 0x000000FF /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CMD_LINK_REPAIR_CHANNEL1_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x009891D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_TX_ERR_PWRD_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_RX_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3_BRICK_E_ERR_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x009891FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x00989200 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x00989204 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x00989208 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL0_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x0098920C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x00989210 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x00989214 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x00989218 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL 8:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG 0x0098921C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_CLK_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_ILA_TRIG_SEL_1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL 15:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_PA_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CHANNEL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_CK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_GPIO_TX_EN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL_CMD_DEBUG_BUS_TEST_MACRO_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0 0x00989224 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM 21:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_BYPASS_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_TX_DDLL_CLK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC0_WL_DDLL_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1 0x00989228 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_TRIM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_BYPASS_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_DDLL_PWRD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE 17:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_E_DIFF_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_DQ_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_RDQS_RX_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_TX_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DELAY_BROADCAST_MISC1_WL_DDLL_USE_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE1 0x00989030 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE1_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE1_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE2 0x00989034 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE2_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE2_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE3 0x00989038 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE3_REG 31:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_DONT_USE3_REG_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x009892C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x009892C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x009892CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x009892D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_BYTE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL_DDLL_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG6_BRICK_SPARE 0x009892D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG6_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG6_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE 0x009892D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG7_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE 0x009892DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG8_BRICK_SPARE_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG9_BRICK_SPARE 0x009892F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG9_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA 31:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG9_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE 0x009892E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB 31:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG10_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE 0x009892E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB 19:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_DQSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG11_BRICK_SPARE_CMD_RFU_ERRB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x00989700 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x00989704 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x00989708 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x0098970C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x00989710 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x00989714 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x00989718 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x0098971C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x00989720 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x00989724 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x00989728 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x0098972C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x00989730 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x00989734 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x00989738 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x0098973C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x00989740 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x00989744 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x00989748 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x0098974C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x00989750 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x00989754 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x00989758 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x0098975C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD9_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_CODE3_PAD10_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x00989760 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x00989764 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x00989768 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x0098976C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x00989770 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x00989774 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x00989778 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x0098977C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x00989780 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x00989784 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x00989788 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x0098978C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x00989790 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x00989794 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x00989798 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x0098979C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x009897A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x009897A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x009897A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x009897AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x009897B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x009897B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x009897B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x009897BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x009897C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x009897C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x009897C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x009897CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x009897D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x009897D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x009897D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x009897DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x009897E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x009897E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x009897E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x009897EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x009897F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x009897F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x009897F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x009897FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x00989800 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x00989804 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x00989808 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x0098980C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x00989810 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x00989814 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD0_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD1_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD2_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1_PAD3_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x00989818 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD4_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD5_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD6_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2_PAD7_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x0098981C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3_PAD8_INIT 0x00000040 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x00989860 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x00989864 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x00989868 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x0098986C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x00989870 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x00989874 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x00989878 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x0098987C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x00989880 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x00989884 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x00989888 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x0098988C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x00989890 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x00989894 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x00989898 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x0098989C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x009898A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x009898A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x009898A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x009898AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x009898B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x009898B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x009898B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7 24:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x009898BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OFFSET3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x009898D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x009898D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x009898D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x009898DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x009898E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x009898E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x009898E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x009898EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x009898F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x009898F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x009898F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x009898FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x00989900 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x00989904 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x00989908 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x0098990C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x00989910 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x00989914 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x00989918 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x0098991C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x00989920 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x00989924 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x00989928 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x0098992C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x00989930 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x00989934 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x00989938 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x0098993C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x00989940 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x00989944 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x00989948 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x0098994C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x00989950 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x00989954 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x00989958 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x0098995C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x00989960 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x00989964 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x00989968 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x0098996C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x00989970 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x00989974 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x00989978 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x0098997C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x00989980 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x00989984 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x00989988 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x0098998C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x0098A600 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x0098A604 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x0098A608 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x0098A60C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x0098A610 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x0098A614 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x0098A618 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x0098A61C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x0098A620 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x0098A624 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x0098A628 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x0098A62C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x0098A630 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x0098A634 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x0098A638 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x0098A63C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x0098A640 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x0098A644 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x0098A648 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x0098A64C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x0098A650 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x0098A654 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x0098A658 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x0098A65C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x0098A660 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x0098A664 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x0098A668 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x0098A66C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x0098A670 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x0098A674 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x0098A678 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x0098A67C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x0098A680 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x0098A684 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x0098A688 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x0098A68C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x0098A690 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x0098A694 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x0098A698 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x0098A69C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x0098A6A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x0098A6A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x0098A6A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x0098A6AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x0098A6B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x0098A6B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x0098A6B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x0098A6BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x0098A6C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x0098A6C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x0098A6C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x0098A6CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x0098A6D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x0098A6D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x0098A6D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x0098A6DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x0098A6E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x0098A6E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x0098A6E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x0098A6EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x0098A6F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x0098A6F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x0098A6F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x0098A6FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x0098A700 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x0098A704 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x0098A708 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x0098A70C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x0098A710 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x0098A714 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x0098A718 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x0098A71C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x0098A720 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x0098A724 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x0098A728 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x0098A72C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x0098A730 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x0098A734 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x0098A738 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x0098A73C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x0098A740 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x0098A744 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x0098A748 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x0098A74C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x0098A750 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x0098A754 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x0098A758 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x0098A75C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x0098A760 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x0098A764 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x0098A768 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x0098A76C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x0098A770 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x0098A774 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x0098A778 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x0098A77C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9 10:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10 16:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT 0x0098A7A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x0098A7A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT 0x0098A7A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x0098A7AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE01_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCKB_DDLLCAL_LT_BYTE23_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT 0x0098A7B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_DDLLCAL_LT_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x00989990 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x00989994 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x00989998 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x0098999C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x009899A0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x009899A4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x009899A8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x009899AC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x009899B0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x009899B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x009899B8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x009899BC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x009899C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x009899C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x009899C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x009899CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x009899D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x009899D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x009899D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x009899DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x009899E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x009899E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x009899E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7 26:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x009899EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9 12:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10 19:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x00989FC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x00989FC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x00989FC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x00989FCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x00989FD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x00989FD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x00989FD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x00989FDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x00989FE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x00989FE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x00989FE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x00989FEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x00989FF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x00989FF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x00989FF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x00989FFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x00989820 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x00989824 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x00989828 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x0098982C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x00989830 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x00989834 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x00989838 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x0098983C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL 0x00989A00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_ENABLE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SAMPLE_COUNT_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY 11:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SAMPLE_DELAY_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_STARTVAL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_STARTVAL_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_REMOVE_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SEL_ODD 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SEL_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SEL_VREFU 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_OFFSET_CAL_CTRL_SEL_VREFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_MISC_CTRL 0x00989A04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_MISC_CTRL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_MISC_CTRL_VREFN_ENC_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x00989A10 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x00989A14 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x00989A18 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x00989A1C /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x00989A20 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x00989A24 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x00989A28 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x00989A2C /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE 9:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_NOT_DONE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_STATE_DONE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX 20:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MAX_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN 31:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_FALSE 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS_MIN_TRUE 0x000001FF /* R---V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x00989A30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x00989A34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x00989A38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x00989A3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x00989A40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x00989A44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x00989A48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x00989A4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x00989A50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x00989A54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x00989A58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x00989A5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x00989A60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x00989A64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x00989A68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x00989A6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x00989A70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x00989A74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x00989A78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x00989A7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x00989A80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x00989A84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x00989A88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x00989A8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00989A90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00989A94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00989A98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00989A9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00989AA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00989AA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00989AA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00989AAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00989AB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00989AB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00989AB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00989ABC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00989AC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00989AC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00989AC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00989ACC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00989AD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00989AD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00989AD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00989ADC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00989AE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00989AE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00989AE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00989AEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00989AF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00989AF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00989AF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00989AFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00989B00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00989B04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00989B08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00989B0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00989B10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00989B14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00989B18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00989B1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00989B20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00989B24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00989B28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00989B2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00989B30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00989B34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00989B38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00989B3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00989B40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00989B44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00989B48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00989B4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00989B50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00989B54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00989B58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00989B5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00989B60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00989B64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00989B68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00989B6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00989B70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00989B74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00989B78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00989B7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00989B80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00989B84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00989B88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00989B8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00989B90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00989B94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00989B98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00989B9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00989BA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00989BA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00989BA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00989BAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00989BB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00989BB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00989BB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00989BBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00989BC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00989BC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00989BC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00989BCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00989BD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00989BD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00989BD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00989BDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00989BE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00989BE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00989BE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00989BEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00989BF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00989BF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00989BF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00989BFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00989C00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00989C04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00989C08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00989C0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00989C10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00989C14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00989C18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00989C1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00989C20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00989C24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00989C28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00989C2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00989C30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00989C34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00989C38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00989C3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00989C40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00989C44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00989C48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00989C4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00989C50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00989C54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00989C58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00989C5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00989C60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00989C64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00989C68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00989C6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00989C70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00989C74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00989C78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00989C7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00989C80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00989C84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00989C88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00989C8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00989C90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00989C94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00989C98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00989C9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00989CA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00989CA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00989CA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00989CAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00989CB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00989CB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00989CB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00989CBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00989CC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00989CC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00989CC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00989CCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00989CD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00989CD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00989CD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00989CDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00989CE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00989CE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00989CE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00989CEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00989CF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00989CF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00989CF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00989CFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00989D00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00989D04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00989D08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00989D0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00989D10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00989D14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00989D18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00989D1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00989D20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00989D24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00989D28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00989D2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00989D30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00989D34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00989D38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00989D3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00989D40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00989D44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00989D48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00989D4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00989D50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00989D54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00989D58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00989D5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00989D60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00989D64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00989D68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00989D6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00989D70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00989D74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00989D78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00989D7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00989D80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00989D84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00989D88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5 12:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6 20:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7 28:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00989D8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x00989DA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x00989DA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x00989DA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x00989DAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x00989DB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x00989DB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x00989DB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x00989DBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x00989DC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x00989DC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x00989DC8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x00989DCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x00989DD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x00989DD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x00989DD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x00989DDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x00989DE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x00989DE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x00989DE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x00989DEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x00989DF0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x00989DF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD0_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD1_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD2_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1_PAD3_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x00989DF8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD4_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD5_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD6_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2_PAD7_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x00989DFC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD8_S4_2T 0x00000004 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD9_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3_PAD10_S4_2T 0x00000005 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLLCAL 0x00989E00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLLCAL 0x00989E04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLLCAL 0x00989E08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLLCAL 0x00989E0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLLCAL 0x00989E10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLLCAL 0x00989E14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLLCAL 0x00989E18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLLCAL 0x00989E1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLLCAL__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLLCAL_16FF 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLLCAL_16FF_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF 0x00989E20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLLCAL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF 0x00989E24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF 0x00989E28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF 0x00989E2C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF 0x00989E30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF 0x00989E34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF 0x00989E38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF 0x00989E3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF 0x00989E40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF_OB 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF_OB_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_DDLL_16FF_ENABLE_PER_BIT_MULT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF 0x00989E44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF_SUBP0 9:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF_SUBP0_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF_SUBP1 25:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_16FF_SUBP1_INIT 0x00000020 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1 0x00989E48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2 0x00989E4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1 0x00989E50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2 0x00989E54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1 0x00989E58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2 0x00989E5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1 0x00989E60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2 0x00989E64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1 0x00989E68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2 0x00989E6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1 0x00989E70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2 0x00989E74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1 0x00989E78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2 0x00989E7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1 0x00989E80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH1_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2 0x00989E84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7 17:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8 23:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_PREMPH2_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU 0x00989E88 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU 0x00989E8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU 0x00989E90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU 0x00989E94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU 0x00989E98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU 0x00989E9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU 0x00989EA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU 0x00989EA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PU_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD 0x00989EA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD 0x00989EAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD 0x00989EB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD 0x00989EB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD 0x00989EB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE0_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD 0x00989EBC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE1_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD 0x00989EC0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE2_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD 0x00989EC4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6 20:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7 23:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_BYTE3_E_TBB_PD_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT 0x00989F30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_TEMP_COEFF 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_TEMP_COEFF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_IBG_CNTL 4:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_BG_CNTL 8:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_LV_CDBVAUXC 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_LV_CDBVAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_LOAD 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_LIMITER 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_SRBOOST 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_SRBOOST_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_BW 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_CDBVAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_SPARE 25:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BG_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB 0x00989F4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB 0x00989F40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB 0x00989F3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_LSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB 0x00989F44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23 7:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCK23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCK23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB01_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01 14:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB01_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23 17:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23 18:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_PWRD_WCKB23_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23 19:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1_WCK_CK2DQS_MSB_TRIM_SEL_WCKB23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS 0x00989F48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SUBP0_CK 10:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK 11:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP0_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SEL_SUBP0_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SUBP1_CK 23:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_PWRD_SUBP1_CK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CK_CK2DQS_TRIM_SEL_SUBP1_CK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1 0x00989F50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_OVERRIDE_DDLLCAL_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_DISABLE_RANK_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_UPDATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_DDLLCAL_CTRL1_CMD_DISABLE_PERIODIC_UPDATE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0 0x0098A780 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1 0x0098A784 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2 0x0098A788 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3 0x0098A78C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP0_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0 0x0098A790 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD5_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD6_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_0_PAD7_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1 0x0098A794 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD8_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD9_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD10_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD11_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD12_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD13_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD14_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_1_PAD15_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2 0x0098A798 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD16_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD17_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD18_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD19_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21 23:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23 31:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_2_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3 0x0098A79C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_DDLL_MSB_SUBP1_3_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING 0x00989F54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_RD_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_WR_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_RD_GAIN 7:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_RD_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_WR_GAIN 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_WR_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EDGE_INTRPLTR_OFFSET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EDGE_BRLSHFT 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EDGE_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_CENTER_BRLSHFT 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_CENTER_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_BLOCK_COUNT 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_BLOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EN 27:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_HUNT_MODE 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_HUNT_MODE_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_USE_CENTER_ONLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_USE_CENTER_ONLY_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_HALF_RATE_EDC 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_HALF_RATE_EDC_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING 0x00989F58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_FLIP_DIRECTION 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_FLIP_DIRECTION_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_GAIN 6:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_GAIN_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DISABLE_TRAINING_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_ACCUM 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_ACCUM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN 10:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT 19:11 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW 20:20 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW 21:21 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF 28:22 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_DEBUG_VREF_EDGE_VREF_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_VREF_EDGE_PWRD 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_VREF_EDGE_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EDGE_HSSA_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_EDGE_INTERP_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2 0x0098A7B4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_SHADOW_LOAD 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_SHADOW_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_SHADOW_SELECT 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_SHADOW_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_CDR_MASK 9:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING2_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1 0x0098A7B8 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFP_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFP_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFP_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFP_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFN_EVEN 23:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFN_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFN_ODD 31:24 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ1_VREFN_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2 0x0098A7BC /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN 7:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2_VREF_EDGE_EVEN_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD 15:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_VREF_TRACKING_READ2_VREF_EDGE_ODD_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x0098A7C8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x0098A7CC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x0098A7D0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x0098A7D4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x0098A7D8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x0098A7DC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x0098A7E0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x0098A7E4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x0098A7E8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x0098A7EC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x0098A7F0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x0098A7F4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x0098A7F8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x0098A7FC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x0098A800 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFP_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1_VREFN_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x0098A804 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_EVEN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2_VREF_EDGE_ODD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG 0x00989F5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT 11:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW 13:13 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW 14:14 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_PI_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW 15:15 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_PI_UNDERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DQ_SEL 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DQ_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL 22:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_BYTE_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DIR_SEL 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DIR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DISABLE_REFRESH_RECENTER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_DISABLE_WDQS_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL 26:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_ZERO_OUT_OFFSET_CAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW 27:27 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_IB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW 28:28 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_OB_BRLSHFT_OVERFLOW_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_BLOCK_PI_UPDATES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE 31:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG_PI_MOVEMENT_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1 0x00989F60 /* R--4R */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_EDGE_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI 13:7 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_CENTER_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_DQ_PI 20:14 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_DQ_PI_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT 26:21 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING_DEBUG1_DQ_BRLSHFT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x00989F64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x00989F68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x00989F6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x00989F70 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP0BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x00989F74 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE0_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x00989F78 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE1_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x00989F7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE2_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x00989F80 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_OFFSET_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS 12:12 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_CAL_STATUS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL 20:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_ACCUMULATOR_RESET_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB 21:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_SUBP1BYTE3_VREF_TRACKING1_EDGE_OFFSET_BKV_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14 0x00989F84 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE0 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE0_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE1 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE1_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE2 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE2_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE3 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE3_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE4 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE4_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE5 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE5_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE6 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE6_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE7 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_EDC_PIN_STATE_BYTE7_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_FORCE_PIN_STATE 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CFG14_FORCE_PIN_STATE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC 0x00989F8C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_EN_X 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_EN_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SIGNAL_SEL_X 4:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SIGNAL_SEL_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_OFFSET_X 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_OFFSET_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SELECT_X 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SELECT_X_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_EN_Y 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_EN_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SIGNAL_SEL_Y 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SIGNAL_SEL_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_OFFSET_Y 26:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_OFFSET_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SELECT_Y 29:27 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HSDAC_SELECT_Y_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0 0x0098A7C0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC0_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1 0x0098A7C4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_EN 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_EN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_SRC_SEL 3:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_SRC_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_BYP 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_BYP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_BYP_CODE 11:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_BYP_CODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_GAIN 13:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_GAIN_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_CNTL 17:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_FS_CNTL 19:18 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_FS_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_INT_TERM_E 20:20 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_CMD_HSDAC1_INT_TERM_E_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0 0x00989F90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP0_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1 0x00989F94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE1_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_BYTE_PAD_CTRL3_SUBP1_RX_DATA_TRIM_MSB_BYTE3_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS 0x00989F98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_DELTA_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_BYP_DRVUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD 22:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_TERM 23:23 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_TERM_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_WCK_CTRL_SDDRDQS_RX_IREF_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI 0x00989F9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_RX 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_TX 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_SPARE 31:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_INTERP_2UI_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x00989FA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x00989FA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x00989FA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD20_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD21_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD22_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR6_PAD23_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x00989FAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD24_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25 13:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD25_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26 21:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD26_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27 29:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_INTRPLTR7_PAD27_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x00989FB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP0_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x00989FB4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD24_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25 7:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD25_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD26_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIOTRNG_SUBP1_CMD_BRLSHFT4_PAD27_S4_2T 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1 0x00989FB8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1__PRIV_LEVEL_MASK 0x009888FC /* */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_CDR_MASK 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_CDR_MASK_INIT 0x000000AA /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_CENTER_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS 15:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_EDGE_TRANSITIONS_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_SUPPORT 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_EDC_TRACKING1_LOCK_SUPPORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK 0x0098BC7C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fbio" /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWBVF */ #define NV_PFB_FBPA_MC_2_FBIO_SERIAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWB-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG 0x0098BC90 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE_NO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE_YES 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SYNCMODE 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SYNCMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SYNCMODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SYNCMODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_LCKDET 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_LCKDET_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_LCKDET_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_LCKDET_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_LOCK_OVERRIDE 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_LOCK_OVERRIDE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_PLL_LOCK 5:5 /* R--UF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_PLL_LOCK_FALSE 0x00000000 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_PLL_LOCK_TRUE 0x00000001 /* R---V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_FSTLCK 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_FSTLCK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_FSTLCK_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_EN_FSTLCK_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_IDDQ 7:7 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE_BG 8:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_STOP_SYNCMUX 9:9 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_BYPASSPLL 10:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_BYPASSPLL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_BYPASSPLL_VCO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_BYPASSPLL_BYPASSCLK 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_CLK_EN_PADMACRO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SEL_ALT_DRAMCLK_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE 13:13 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_SWITCH_ASYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG_PTRIM_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL 0x0098BC94 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_LFRES 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_LFRES_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_KCP 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_KCP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_KVCO 20:20 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_KVCO_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CTRL_PLL_FREQLOCK 28:28 /* R--UF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF 0x0098BC98 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_MDIV 7:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_MDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_MDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_MDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_NDIV 15:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_NDIV_INIT 0x00000008 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_NDIV_MIN 0x00000008 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_NDIV_MAX 0x000000FF /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_PLDIV 21:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_PLDIV_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_PLDIV_MIN 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_COEFF_PLDIV_MAX 0x0000003F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO 0x0098BC9C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_RESET 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_TEMPERATURE 3:1 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_TEMPERATURE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET 4:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DRAM_WRST_RESET_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_READ_I1500_REG 5:5 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_READ_I1500_REG_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT 8:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_WSO_SELECT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL 13:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP0_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL 18:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP1_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL 23:19 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_GROUP2_SEL_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_DEBUG_BUS_RESET_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE 25:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_WSO_MUX_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL 29:26 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_TEST_MACRO_WSO_MUX_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST 0x0098BCA0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RX_VREF_CODE 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RX_VREF_CODE_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD 6:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RX_VREF_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL 9:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_RCVR_SEL_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL 12:10 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD 13:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_BIAS_PWRD_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE 16:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_DQ_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RFU 24:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG 0x0098BCA4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP 6:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN 13:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_INIT 0x0000005A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK 20:14 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK 27:21 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE 29:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_LEKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG1 0x0098BCA8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG1_TX_EN 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_CFG1_TX_EN_INIT 0x00FFD98A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD1 0x0098BCAC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD1_TX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD1_TX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD2 0x0098BCB0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD2_RX 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_BRICK_TEST_PWRD2_RX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE 0x0098BCCC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA 23:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQA_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG12_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG13_BRICK_SPARE 0x0098BCD0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG13_BRICK_SPARE__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB 15:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CFG13_BRICK_SPARE_TEST_RFU_DQB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG 0x0098BCD4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF 5:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_EXT_VREF_INIT 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_INT_VREF 11:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_INT_VREF_INIT 0x00000019 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD 12:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_BIAS_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_BIAS_CTRL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS 16:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_BYPASS_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV 19:17 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_DEBUG_CLK_DIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE 30:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_RX_PN_TUNE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG_MIO_DEBUG_CLK_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1 0x0098BCD8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_VREF_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK 7:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK 14:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_EXT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK 21:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEUP_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK 28:22 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_INT_TX_DRIVEDN_MSB_MASK_INIT 0x0000007F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL 31:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG1_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2 0x0098BCDC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT 0:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_DRIVER_SHORT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE 1:1 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE 3:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_E_TEST_LEAKAGE_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH 6:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_LEAKAGE_STRENGTH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW 10:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD 12:11 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST 15:13 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_DQ_OBS_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV 24:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_COMP_EXT_CODEDIV_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV 26:25 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_BRICK_CFG2_FREQ_DIV_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1 0x0098BCE0 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREG14V_CTRL 5:4 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREG10V_CTRL 7:6 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG1_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0 0x0098BCE4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC 2:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_INIT 0x00000006 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER 5:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_LIMITER_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_VAUXC_BW_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD 15:15 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTTGEN_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL 18:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_ISOURCE_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL 26:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_CDB_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG0_VTT_LV_VAUXC_MSB_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1 0x0098BCE8 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD 1:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL 6:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_BRIC_TEST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL 8:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF 11:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST 14:12 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_VTT_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_RFU 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_HBMCDB_CFG1_RFU_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0 0x0098BCEC /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL 4:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0_COMP_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_COMP_CFG0_COMP_BRICK_CFG_RFU_INIT 0x00000030 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG2 0x0098BCF4 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG2_SETUP 27:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBMPLL_CFG2_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG 0x0098BC00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_PERIOD 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_PERIOD_100MS 0x000000A5 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_PERIOD_15K 0x00003A98 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_INTERVAL 23:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_INTERVAL_10 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_INTERVAL_48 0x00000030 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_DRVDLY 26:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_DRVDLY_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_DRVDLY_5 0x00000005 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_DRVDLY_MAX 0x00000007 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_MAXDRIVE 27:27 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_MAXDRIVE_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_LIMIT_BW 28:28 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_LIMIT_BW_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MIN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_CLAMP_MAX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_AUTOCOMP 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG_AUTOCOMP_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN 0x0098BC04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_RISE_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_FALL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MIN_TERM_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX 0x0098BC08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_RISE_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_FALL_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CLAMP_MAX_TERM_1F 0x0000001F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL 0x0098BC0C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL 6:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_RISE_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN 8:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_ENABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_FALL_EN_DISABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN 9:9 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TERM_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN 16:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TEST_VAL_EXT_DRIVE_DN_INIT 0x0000004D /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_RISE_LOCK 24:24 /* R-XVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_FALL_LOCK 25:25 /* R-XVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_TERM_LOCK 26:26 /* R-XVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_RISE_SLEW_LOCK 27:27 /* R-XVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_FALL_SLEW_LOCK 28:28 /* R-XVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY 29:29 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_THERMO 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_DQS_DLY_DIRECT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_MODE 30:30 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_MODE_DRIVE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_MODE_SLEW 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_SELECT 31:31 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_HW 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SW_CTRL_SELECT_SW 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB 0x0098BC10 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_RISE_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_FALL_INIT 0x00000024 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_TERM 22:16 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_TERM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_CAL_CYCLE 31:31 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_DONE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_PENDING 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB_CAL_CYCLE_RESET 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2 0x0098BC14 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_RISE 6:0 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_RISE_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_FALL 14:8 /* R-IVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_FALL_INIT 0x00000000 /* R-I-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_SPARE 15:15 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB2_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3 0x0098BC18 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB3_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4 0x0098BC1C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4_TERM_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB4_TERM_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5 0x0098BC20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT 7:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_RISE_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT 15:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_RISE_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT 23:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_FALL_FAIL_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT 31:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_RB5_FALL_PASS_CNT_RST 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x0098BC30 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x0098BC34 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVR2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x0098BC38 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP 19:16 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_SUBP_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF_ADR_CS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x0098BC3C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVF2_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x0098BC40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT 11:8 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x0098BC44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWR_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x0098BC48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR 3:0 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF_ADR_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS 27:24 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_SLOPE_SLWF_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x0098BC4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x0098BC50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVR2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x0098BC54 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP 22:16 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_SUBP_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF_ADR_CS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x0098BC58 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVF2_DAT_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x0098BC5C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT_DQS_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT 14:8 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_DRVT_DAT_4 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x0098BC60 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWR_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x0098BC64 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR 6:0 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF_ADR_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS 30:24 /* RWISF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_OFFSET_SLWF_DQS_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2 0x0098BC68 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TERM 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TERM_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TERM_ENABLE 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE 3:3 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_INACTIVE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_TRIGGER_CAL_CYCLE_ENABLED 0x00000001 /* -W--T */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_ENABLED 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_AUTO_DISABLED 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_CYCLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_MODE_PER_STEP 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_RX_PWRD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD 2:2 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_INT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD 7:7 /* RWIVF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_EXT_PWRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE 6:6 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_OFF 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_ENABLE_ON 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT 11:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_SAMPLE_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT 15:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_LOCK_COUNT_MAX 0x0000000F /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY 31:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG2_COMP_POWERUP_DLY_1024 0x00000400 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3 0x0098BC6C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_COMP 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_COMP_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWR_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_SLWF_EN_DISABLE 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL 4:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_0 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_1 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_2 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_HBM_PRI_CALMASTER_SEL_3 0x00000003 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_TERM_MODE 5:5 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_UP 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_TERM_MODE_DN 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL 14:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_RISE_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL 22:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_FALL_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL 30:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_HBM_CALMASTER_CFG3_TERM_START_VAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG 0x0098BD00 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_SYNC_MODE 1:1 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_SYNC_MODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_SYNC_MODE_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_SYNC_MODE_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CONFIG_STOP_SYNCMUX_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL 0x0098BD04 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_RESET_LD_PULSE 22:22 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_RESET_LD_PULSE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_ENABLE_BG 23:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_ENABLE_BG_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_VREG14V_CTRL 25:24 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_VREG10V_CTRL 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2 0x0098BD08 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_SEL_TESTOUT 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_SEL_TESTOUT_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_SETUP2 27:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_TESTMODE 28:28 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_REFMPLL_CFG2_TESTMODE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG 0x0098BD20 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_IDDQ 0:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_IDDQ_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_ON 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_IDDQ_POWER_OFF 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_BYPASS 2:2 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_BYPASS_INIT 0x00000001 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_BYPASS_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_BYPASS_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_CLAMP_P0 3:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_CLAMP_P0_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_CLAMP_P0_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_CLAMP_P0_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4 4:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CONFIG_LD_PULSE_DIV4_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL 0x0098BD24 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_SETUP 15:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_SETUP_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREG14V_CTRL 24:23 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREG14V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREG10V_CTRL 26:25 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREG10V_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL 31:29 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CTRL_VREGBG_TST_CTRL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2 0x0098BD28 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2_SETUP2 11:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2_SETUP2_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_DRAMPLL_CFG2_BYPASS_BR8CLK_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0 0x0098BD40 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_CMD_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_LV_VAUXC 18:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_BW 22:19 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_BW_INIT 0x0000000F /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD 27:26 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST 30:28 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL0_BYTE_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1 0x0098BD44 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_LV_VAUXC 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_LV_VAUXC_INIT 0x00000004 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_BW 6:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_BW_INIT 0x00000002 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD 11:10 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_LOAD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST 14:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VAUXC_SRBOOST_INIT 0x00000007 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CMD_VTT_SPARE 17:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CMD_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_BYTE_VTT_SPARE 19:18 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_BYTE_VTT_SPARE_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VTT_SPARE 21:20 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_CDB_VTT_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL 29:22 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL1_VTT_REFGEN_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL 0x0098BD48 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_BG_CNTL 3:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_BG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IBG_CNTL 5:4 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IBG_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IRX_CNTL 7:6 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IRX_CNTL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IRX_SRC_SEL 10:8 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IRX_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEMP_COEF 13:11 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEMP_COEF_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_CDB_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_CDB_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_SEL 20:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_E_RES_CAL_CODE_IN 21:21 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_E_RES_CAL_CODE_IN_BYP_SEL 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL 26:22 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_TEST_CDB_CTRL_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IBG_SRC_SEL 29:27 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CDBCTRL_IBG_SRC_SEL_INIT 0x00000003 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV 0x0098BD4C /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_TEST_OUT_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_SPARE 10:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_SPARE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_PTRIM_OVRD 11:11 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_PTRIM_OVRD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_MODE_SWITCH 13:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_MODE_SWITCH_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_MODE_SWITCH_DRAMPLL 0x00000002 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_MODE_SWITCH_ONESOURCE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_MODE_SWITCH_REFMPLL 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL 15:14 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_RX_RCVR_SEL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_DPD 16:16 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_DPD_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_DPD_ENABLE 0x00000001 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_DPD_DISABLE 0x00000000 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE 17:17 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVERRIDE_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL 18:18 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_CTRL_SER_PRIV_CMD_BR8_MODE_OVRDVAL_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2 0x0098BD50 /* RW-4R */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2__PRIV_LEVEL_MASK 0x0098BC7C /* */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM 2:0 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXC_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM 5:3 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM 8:6 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VCLAMP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_BGAP_TRIM 11:9 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_BGAP_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_E_TRIM 12:12 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_E_TRIM_INIT 0x00000000 /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXC 16:13 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXC_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXC_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXP 20:17 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VAUXP_850mV 0x00000006 /* RW--V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VCLAMP 24:21 /* RWIUF */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VCLAMP_INIT 0x0000000A /* RWI-V */ #define NV_PFB_FBPA_MC_2_FBIO_VTT_CTRL2_CDB_VCLAMP_850mV 0x00000006 /* RW--V */ #endif // __ga102_dev_fbpa_h__